endchoice
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0"
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1"
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2"
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3"
-source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4"
-
endmenu
+++ /dev/null
-menuconfig ELBC_BR0_OR0
- bool "ELBC BR0/OR0"
-
-if ELBC_BR0_OR0
-
-config BR0_OR0_NAME
- string "Identifier"
-
-config BR0_OR0_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR0_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR0_PORTSIZE_16BIT
- depends on !BR0_MACHINE_FCM
- bool "16-bit"
-
-
-config BR0_PORTSIZE_32BIT
- depends on !BR0_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR0_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR0_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR0_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR0_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR0_WRITE_PROTECT
- bool "Write-protect"
-
-config BR0_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR0_MACHINE_GPCM
- bool "GPCM"
-
-config BR0_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR0_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR0_MACHINE_UPMA
- select BR0_MACHINE_UPM
- bool "UPM (A)"
-
-config BR0_MACHINE_UPMB
- select BR0_MACHINE_UPM
- bool "UPM (B)"
-
-config BR0_MACHINE_UPMC
- select BR0_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR0_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR0_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR0_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR0_AM_32_KBYTES
- depends on !BR0_MACHINE_SDRAM
- bool "32 kb"
-
-config OR0_AM_64_KBYTES
- bool "64 kb"
-
-config OR0_AM_128_KBYTES
- bool "128 kb"
-
-config OR0_AM_256_KBYTES
- bool "256 kb"
-
-config OR0_AM_512_KBYTES
- bool "512 kb"
-
-config OR0_AM_1_MBYTES
- bool "1 mb"
-
-config OR0_AM_2_MBYTES
- bool "2 mb"
-
-config OR0_AM_4_MBYTES
- bool "4 mb"
-
-config OR0_AM_8_MBYTES
- bool "8 mb"
-
-config OR0_AM_16_MBYTES
- bool "16 mb"
-
-config OR0_AM_32_MBYTES
- bool "32 mb"
-
-config OR0_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR0_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR0_AM_256_MBYTES
- bool "256 mb"
-
-config OR0_AM_512_MBYTES
- depends on BR0_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR0_AM_1_GBYTES
- bool "1 gb"
-
-config OR0_AM_2_GBYTES
- depends on BR0_MACHINE_FCM
- bool "2 gb"
-
-config OR0_AM_4_GBYTES
- depends on BR0_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR0_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR0_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR0_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR0_MACHINE_GPCM || BR0_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR0_SCY_0
- bool "No wait states"
-
-config OR0_SCY_1
- bool "1 wait state"
-
-config OR0_SCY_2
- bool "2 wait states"
-
-config OR0_SCY_3
- bool "3 wait states"
-
-config OR0_SCY_4
- bool "4 wait states"
-
-config OR0_SCY_5
- bool "5 wait states"
-
-config OR0_SCY_6
- bool "6 wait states"
-
-config OR0_SCY_7
- bool "7 wait states"
-
-config OR0_SCY_8
- depends on BR0_MACHINE_GPCM
- bool "8 wait states"
-
-config OR0_SCY_9
- depends on BR0_MACHINE_GPCM
- bool "9 wait states"
-
-config OR0_SCY_10
- depends on BR0_MACHINE_GPCM
- bool "10 wait states"
-
-config OR0_SCY_11
- depends on BR0_MACHINE_GPCM
- bool "11 wait states"
-
-config OR0_SCY_12
- depends on BR0_MACHINE_GPCM
- bool "12 wait states"
-
-config OR0_SCY_13
- depends on BR0_MACHINE_GPCM
- bool "13 wait states"
-
-config OR0_SCY_14
- depends on BR0_MACHINE_GPCM
- bool "14 wait states"
-
-config OR0_SCY_15
- depends on BR0_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM
-
-if BR0_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR0_CSNT_NORMAL
- bool "Normal"
-
-config OR0_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR0_ACS_SAME_TIME
- bool "At the same time"
-
-config OR0_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR0_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR0_XACS_NORMAL
- bool "Normal"
-
-config OR0_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR0_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR0_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR0_MACHINE_GPCM
-
-if BR0_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR0_PGS_SMALL
- bool "Small page device"
-
-config OR0_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR0_CSCT_1_CYCLE
- depends on OR0_TRLX_NORMAL
- bool "1 cycle"
-
-config OR0_CSCT_2_CYCLE
- depends on OR0_TRLX_RELAXED
- bool "2 cycles"
-
-config OR0_CSCT_4_CYCLE
- depends on OR0_TRLX_NORMAL
- bool "4 cycles"
-
-config OR0_CSCT_8_CYCLE
- depends on OR0_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR0_CST_COINCIDENT
- depends on OR0_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR0_CST_QUARTER_CLOCK
- depends on OR0_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR0_CST_HALF_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR0_CST_ONE_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR0_CHT_HALF_CLOCK
- depends on OR0_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR0_CHT_ONE_CLOCK
- depends on OR0_TRLX_NORMAL
- bool "1 clock before"
-
-config OR0_CHT_ONE_HALF_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR0_CHT_TWO_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR0_RST_THREE_QUARTER_CLOCK
- depends on OR0_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR0_RST_ONE_HALF_CLOCK
- depends on OR0_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR0_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR0_MACHINE_FCM
-
-if BR0_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR0_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR0_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR0_MACHINE_UPM
-
-if BR0_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR0_COLS_7
- bool "7"
-
-config OR0_COLS_8
- bool "8"
-
-config OR0_COLS_9
- bool "9"
-
-config OR0_COLS_10
- bool "10"
-
-config OR0_COLS_11
- bool "11"
-
-config OR0_COLS_12
- bool "12"
-
-config OR0_COLS_13
- bool "13"
-
-config OR0_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR0_ROWS_9
- bool "9"
-
-config OR0_ROWS_10
- bool "10"
-
-config OR0_ROWS_11
- bool "11"
-
-config OR0_ROWS_12
- bool "12"
-
-config OR0_ROWS_13
- bool "13"
-
-config OR0_ROWS_14
- bool "14"
-
-config OR0_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR0_PMSEL_BTB
- bool "Back-to-back"
-
-config OR0_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR0_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR0_TRLX_NORMAL
- bool "Normal"
-
-config OR0_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR0_EHTR_NORMAL
- depends on OR0_TRLX_NORMAL
- bool "Normal"
-
-config OR0_EHTR_1_CYCLE
- depends on OR0_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR0_EHTR_4_CYCLE
- depends on OR0_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR0_EHTR_8_CYCLE
- depends on OR0_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR0_EAD_NONE
- bool "None"
-
-config OR0_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR0_OR0
-
-config BR0_PORTSIZE
- hex
- default 0x800 if BR0_PORTSIZE_8BIT
- default 0x1000 if BR0_PORTSIZE_16BIT
- default 0x1800 if BR0_PORTSIZE_32BIT
-
-config BR0_ERRORCHECKING
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if BR0_ERRORCHECKING_DISABLED
- default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR0_ERRORCHECKING_BOTH
-
-config BR0_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR0_WRITE_PROTECT
- default 0x100 if BR0_WRITE_PROTECT
-
-config BR0_MACHINE
- hex
- default 0x0 if BR0_MACHINE_GPCM
- default 0x20 if BR0_MACHINE_FCM
- default 0x60 if BR0_MACHINE_SDRAM
- default 0x80 if BR0_MACHINE_UPMA
- default 0xa0 if BR0_MACHINE_UPMB
- default 0xc0 if BR0_MACHINE_UPMC
-
-config BR0_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR0_ATOMIC_NONE
- default 0x4 if BR0_ATOMIC_RAWA
- default 0x8 if BR0_ATOMIC_WARA
-
-config BR0_VALID_BIT
- hex
- default 0x0 if !ELBC_BR0_OR0
- default 0x1 if ELBC_BR0_OR0
-
-config OR0_AM
- hex
- default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM
- default 0xffff0000 if OR0_AM_64_KBYTES
- default 0xfffe0000 if OR0_AM_128_KBYTES
- default 0xfffc0000 if OR0_AM_256_KBYTES
- default 0xfff80000 if OR0_AM_512_KBYTES
- default 0xfff00000 if OR0_AM_1_MBYTES
- default 0xffe00000 if OR0_AM_2_MBYTES
- default 0xffc00000 if OR0_AM_4_MBYTES
- default 0xff800000 if OR0_AM_8_MBYTES
- default 0xff000000 if OR0_AM_16_MBYTES
- default 0xfe000000 if OR0_AM_32_MBYTES
- default 0xfc000000 if OR0_AM_64_MBYTES
- default 0xf8000000 if OR0_AM_128_MBYTES
- default 0xf0000000 if OR0_AM_256_MBYTES
- default 0xe0000000 if OR0_AM_512_MBYTES
- default 0xc0000000 if OR0_AM_1_GBYTES
- default 0x80000000 if OR0_AM_2_GBYTES
- default 0x00000000 if OR0_AM_4_GBYTES
-
-config OR0_XAM
- hex
- default 0x0 if !OR0_XAM_SET
- default 0x6000 if OR0_XAM_SET
-
-config OR0_BCTLD
- hex
- default 0x0 if OR0_BCTLD_ASSERTED
- default 0x1000 if OR0_BCTLD_NOT_ASSERTED
-
-config OR0_BI
- hex
- default 0x0 if !BR0_MACHINE_UPM
- default 0x0 if OR0_BI_BURSTSUPPORT
- default 0x100 if OR0_BI_BURSTINHIBIT
-
-config OR0_COLS
- hex
- default 0x0 if !BR0_MACHINE_SDRAM
- default 0x0 if OR0_COLS_7
- default 0x400 if OR0_COLS_8
- default 0x800 if OR0_COLS_9
- default 0xc00 if OR0_COLS_10
- default 0x1000 if OR0_COLS_11
- default 0x1400 if OR0_COLS_12
- default 0x1800 if OR0_COLS_13
- default 0x1c00 if OR0_COLS_14
-
-config OR0_ROWS
- hex
- default 0x0 if !BR0_MACHINE_SDRAM
- default 0x0 if OR0_ROWS_9
- default 0x40 if OR0_ROWS_10
- default 0x80 if OR0_ROWS_11
- default 0xc0 if OR0_ROWS_12
- default 0x100 if OR0_ROWS_13
- default 0x140 if OR0_ROWS_14
- default 0x180 if OR0_ROWS_15
-
-config OR0_PMSEL
- hex
- default 0x0 if !BR0_MACHINE_SDRAM
- default 0x0 if OR0_PMSEL_BTB
- default 0x20 if OR0_PMSEL_KEPT_OPEN
-
-config OR0_SCY
- hex
- default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM
- default 0x0 if OR0_SCY_0
- default 0x10 if OR0_SCY_1
- default 0x20 if OR0_SCY_2
- default 0x30 if OR0_SCY_3
- default 0x40 if OR0_SCY_4
- default 0x50 if OR0_SCY_5
- default 0x60 if OR0_SCY_6
- default 0x70 if OR0_SCY_7
- default 0x80 if OR0_SCY_8
- default 0x90 if OR0_SCY_9
- default 0xa0 if OR0_SCY_10
- default 0xb0 if OR0_SCY_11
- default 0xc0 if OR0_SCY_12
- default 0xd0 if OR0_SCY_13
- default 0xe0 if OR0_SCY_14
- default 0xf0 if OR0_SCY_15
-
-config OR0_PGS
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_PGS_SMALL
- default 0x400 if OR0_PGS_LARGE
-
-config OR0_CSCT
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_CSCT_1_CYCLE
- default 0x0 if OR0_CSCT_2_CYCLE
- default 0x200 if OR0_CSCT_4_CYCLE
- default 0x200 if OR0_CSCT_8_CYCLE
-
-config OR0_CST
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_CST_COINCIDENT
- default 0x100 if OR0_CST_QUARTER_CLOCK
- default 0x0 if OR0_CST_HALF_CLOCK
- default 0x100 if OR0_CST_ONE_CLOCK
-
-config OR0_CHT
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_CHT_HALF_CLOCK
- default 0x80 if OR0_CHT_ONE_CLOCK
- default 0x0 if OR0_CHT_ONE_HALF_CLOCK
- default 0x80 if OR0_CHT_TWO_CLOCK
-
-config OR0_RST
- hex
- default 0x0 if !BR0_MACHINE_FCM
- default 0x0 if OR0_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR0_RST_ONE_CLOCK
- default 0x0 if OR0_RST_ONE_HALF_CLOCK
-
-config OR0_CSNT
- hex
- default 0x0 if !BR0_MACHINE_GPCM
- default 0x0 if OR0_CSNT_NORMAL
- default 0x800 if OR0_CSNT_EARLIER
-
-config OR0_ACS
- hex
- default 0x0 if !BR0_MACHINE_GPCM
- default 0x0 if OR0_ACS_SAME_TIME
- default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER
-
-config OR0_XACS
- hex
- default 0x0 if !BR0_MACHINE_GPCM
- default 0x0 if OR0_XACS_NORMAL
- default 0x100 if OR0_XACS_EXTENDED
-
-config OR0_SETA
- hex
- default 0x0 if !BR0_MACHINE_GPCM
- default 0x0 if OR0_SETA_INTERNAL
- default 0x8 if OR0_SETA_EXTERNAL
-
-config OR0_TRLX
- hex
- default 0x0 if OR0_TRLX_NORMAL
- default 0x4 if OR0_TRLX_RELAXED
-
-config OR0_EHTR
- hex
- default 0x0 if OR0_EHTR_NORMAL
- default 0x2 if OR0_EHTR_1_CYCLE
- default 0x0 if OR0_EHTR_4_CYCLE
- default 0x2 if OR0_EHTR_8_CYCLE
-
-config OR0_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR0_EAD_NONE
- default 0x1 if OR0_EAD_EXTRA
+++ /dev/null
-menuconfig ELBC_BR1_OR1
- bool "ELBC BR1/OR1"
-
-if ELBC_BR1_OR1
-
-config BR1_OR1_NAME
- string "Identifier"
-
-config BR1_OR1_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR1_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR1_PORTSIZE_16BIT
- depends on !BR1_MACHINE_FCM
- bool "16-bit"
-
-
-config BR1_PORTSIZE_32BIT
- depends on !BR1_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR1_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR1_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR1_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR1_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR1_WRITE_PROTECT
- bool "Write-protect"
-
-config BR1_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR1_MACHINE_GPCM
- bool "GPCM"
-
-config BR1_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR1_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR1_MACHINE_UPMA
- select BR1_MACHINE_UPM
- bool "UPM (A)"
-
-config BR1_MACHINE_UPMB
- select BR1_MACHINE_UPM
- bool "UPM (B)"
-
-config BR1_MACHINE_UPMC
- select BR1_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR1_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR1_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR1_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR1_AM_32_KBYTES
- depends on !BR1_MACHINE_SDRAM
- bool "32 kb"
-
-config OR1_AM_64_KBYTES
- bool "64 kb"
-
-config OR1_AM_128_KBYTES
- bool "128 kb"
-
-config OR1_AM_256_KBYTES
- bool "256 kb"
-
-config OR1_AM_512_KBYTES
- bool "512 kb"
-
-config OR1_AM_1_MBYTES
- bool "1 mb"
-
-config OR1_AM_2_MBYTES
- bool "2 mb"
-
-config OR1_AM_4_MBYTES
- bool "4 mb"
-
-config OR1_AM_8_MBYTES
- bool "8 mb"
-
-config OR1_AM_16_MBYTES
- bool "16 mb"
-
-config OR1_AM_32_MBYTES
- bool "32 mb"
-
-config OR1_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR1_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR1_AM_256_MBYTES
- bool "256 mb"
-
-config OR1_AM_512_MBYTES
- depends on BR1_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR1_AM_1_GBYTES
- bool "1 gb"
-
-config OR1_AM_2_GBYTES
- depends on BR1_MACHINE_FCM
- bool "2 gb"
-
-config OR1_AM_4_GBYTES
- depends on BR1_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR1_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR1_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR1_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR1_MACHINE_GPCM || BR1_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR1_SCY_0
- bool "No wait states"
-
-config OR1_SCY_1
- bool "1 wait state"
-
-config OR1_SCY_2
- bool "2 wait states"
-
-config OR1_SCY_3
- bool "3 wait states"
-
-config OR1_SCY_4
- bool "4 wait states"
-
-config OR1_SCY_5
- bool "5 wait states"
-
-config OR1_SCY_6
- bool "6 wait states"
-
-config OR1_SCY_7
- bool "7 wait states"
-
-config OR1_SCY_8
- depends on BR1_MACHINE_GPCM
- bool "8 wait states"
-
-config OR1_SCY_9
- depends on BR1_MACHINE_GPCM
- bool "9 wait states"
-
-config OR1_SCY_10
- depends on BR1_MACHINE_GPCM
- bool "10 wait states"
-
-config OR1_SCY_11
- depends on BR1_MACHINE_GPCM
- bool "11 wait states"
-
-config OR1_SCY_12
- depends on BR1_MACHINE_GPCM
- bool "12 wait states"
-
-config OR1_SCY_13
- depends on BR1_MACHINE_GPCM
- bool "13 wait states"
-
-config OR1_SCY_14
- depends on BR1_MACHINE_GPCM
- bool "14 wait states"
-
-config OR1_SCY_15
- depends on BR1_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM
-
-if BR1_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR1_CSNT_NORMAL
- bool "Normal"
-
-config OR1_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR1_ACS_SAME_TIME
- bool "At the same time"
-
-config OR1_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR1_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR1_XACS_NORMAL
- bool "Normal"
-
-config OR1_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR1_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR1_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR1_MACHINE_GPCM
-
-if BR1_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR1_PGS_SMALL
- bool "Small page device"
-
-config OR1_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR1_CSCT_1_CYCLE
- depends on OR1_TRLX_NORMAL
- bool "1 cycle"
-
-config OR1_CSCT_2_CYCLE
- depends on OR1_TRLX_RELAXED
- bool "2 cycles"
-
-config OR1_CSCT_4_CYCLE
- depends on OR1_TRLX_NORMAL
- bool "4 cycles"
-
-config OR1_CSCT_8_CYCLE
- depends on OR1_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR1_CST_COINCIDENT
- depends on OR1_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR1_CST_QUARTER_CLOCK
- depends on OR1_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR1_CST_HALF_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR1_CST_ONE_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR1_CHT_HALF_CLOCK
- depends on OR1_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR1_CHT_ONE_CLOCK
- depends on OR1_TRLX_NORMAL
- bool "1 clock before"
-
-config OR1_CHT_ONE_HALF_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR1_CHT_TWO_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR1_RST_THREE_QUARTER_CLOCK
- depends on OR1_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR1_RST_ONE_HALF_CLOCK
- depends on OR1_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR1_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR1_MACHINE_FCM
-
-if BR1_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR1_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR1_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR1_MACHINE_UPM
-
-if BR1_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR1_COLS_7
- bool "7"
-
-config OR1_COLS_8
- bool "8"
-
-config OR1_COLS_9
- bool "9"
-
-config OR1_COLS_10
- bool "10"
-
-config OR1_COLS_11
- bool "11"
-
-config OR1_COLS_12
- bool "12"
-
-config OR1_COLS_13
- bool "13"
-
-config OR1_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR1_ROWS_9
- bool "9"
-
-config OR1_ROWS_10
- bool "10"
-
-config OR1_ROWS_11
- bool "11"
-
-config OR1_ROWS_12
- bool "12"
-
-config OR1_ROWS_13
- bool "13"
-
-config OR1_ROWS_14
- bool "14"
-
-config OR1_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR1_PMSEL_BTB
- bool "Back-to-back"
-
-config OR1_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR1_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR1_TRLX_NORMAL
- bool "Normal"
-
-config OR1_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR1_EHTR_NORMAL
- depends on OR1_TRLX_NORMAL
- bool "Normal"
-
-config OR1_EHTR_1_CYCLE
- depends on OR1_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR1_EHTR_4_CYCLE
- depends on OR1_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR1_EHTR_8_CYCLE
- depends on OR1_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR1_EAD_NONE
- bool "None"
-
-config OR1_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR1_OR1
-
-config BR1_PORTSIZE
- hex
- default 0x800 if BR1_PORTSIZE_8BIT
- default 0x1000 if BR1_PORTSIZE_16BIT
- default 0x1800 if BR1_PORTSIZE_32BIT
-
-config BR1_ERRORCHECKING
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if BR1_ERRORCHECKING_DISABLED
- default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR1_ERRORCHECKING_BOTH
-
-config BR1_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR1_WRITE_PROTECT
- default 0x100 if BR1_WRITE_PROTECT
-
-config BR1_MACHINE
- hex
- default 0x0 if BR1_MACHINE_GPCM
- default 0x20 if BR1_MACHINE_FCM
- default 0x60 if BR1_MACHINE_SDRAM
- default 0x80 if BR1_MACHINE_UPMA
- default 0xa0 if BR1_MACHINE_UPMB
- default 0xc0 if BR1_MACHINE_UPMC
-
-config BR1_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR1_ATOMIC_NONE
- default 0x4 if BR1_ATOMIC_RAWA
- default 0x8 if BR1_ATOMIC_WARA
-
-config BR1_VALID_BIT
- hex
- default 0x0 if !ELBC_BR1_OR1
- default 0x1 if ELBC_BR1_OR1
-
-config OR1_AM
- hex
- default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM
- default 0xffff0000 if OR1_AM_64_KBYTES
- default 0xfffe0000 if OR1_AM_128_KBYTES
- default 0xfffc0000 if OR1_AM_256_KBYTES
- default 0xfff80000 if OR1_AM_512_KBYTES
- default 0xfff00000 if OR1_AM_1_MBYTES
- default 0xffe00000 if OR1_AM_2_MBYTES
- default 0xffc00000 if OR1_AM_4_MBYTES
- default 0xff800000 if OR1_AM_8_MBYTES
- default 0xff000000 if OR1_AM_16_MBYTES
- default 0xfe000000 if OR1_AM_32_MBYTES
- default 0xfc000000 if OR1_AM_64_MBYTES
- default 0xf8000000 if OR1_AM_128_MBYTES
- default 0xf0000000 if OR1_AM_256_MBYTES
- default 0xe0000000 if OR1_AM_512_MBYTES
- default 0xc0000000 if OR1_AM_1_GBYTES
- default 0x80000000 if OR1_AM_2_GBYTES
- default 0x00000000 if OR1_AM_4_GBYTES
-
-config OR1_XAM
- hex
- default 0x0 if !OR1_XAM_SET
- default 0x6000 if OR1_XAM_SET
-
-config OR1_BCTLD
- hex
- default 0x0 if OR1_BCTLD_ASSERTED
- default 0x1000 if OR1_BCTLD_NOT_ASSERTED
-
-config OR1_BI
- hex
- default 0x0 if !BR1_MACHINE_UPM
- default 0x0 if OR1_BI_BURSTSUPPORT
- default 0x100 if OR1_BI_BURSTINHIBIT
-
-config OR1_COLS
- hex
- default 0x0 if !BR1_MACHINE_SDRAM
- default 0x0 if OR1_COLS_7
- default 0x400 if OR1_COLS_8
- default 0x800 if OR1_COLS_9
- default 0xc00 if OR1_COLS_10
- default 0x1000 if OR1_COLS_11
- default 0x1400 if OR1_COLS_12
- default 0x1800 if OR1_COLS_13
- default 0x1c00 if OR1_COLS_14
-
-config OR1_ROWS
- hex
- default 0x0 if !BR1_MACHINE_SDRAM
- default 0x0 if OR1_ROWS_9
- default 0x40 if OR1_ROWS_10
- default 0x80 if OR1_ROWS_11
- default 0xc0 if OR1_ROWS_12
- default 0x100 if OR1_ROWS_13
- default 0x140 if OR1_ROWS_14
- default 0x180 if OR1_ROWS_15
-
-config OR1_PMSEL
- hex
- default 0x0 if !BR1_MACHINE_SDRAM
- default 0x0 if OR1_PMSEL_BTB
- default 0x20 if OR1_PMSEL_KEPT_OPEN
-
-config OR1_SCY
- hex
- default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM
- default 0x0 if OR1_SCY_0
- default 0x10 if OR1_SCY_1
- default 0x20 if OR1_SCY_2
- default 0x30 if OR1_SCY_3
- default 0x40 if OR1_SCY_4
- default 0x50 if OR1_SCY_5
- default 0x60 if OR1_SCY_6
- default 0x70 if OR1_SCY_7
- default 0x80 if OR1_SCY_8
- default 0x90 if OR1_SCY_9
- default 0xa0 if OR1_SCY_10
- default 0xb0 if OR1_SCY_11
- default 0xc0 if OR1_SCY_12
- default 0xd0 if OR1_SCY_13
- default 0xe0 if OR1_SCY_14
- default 0xf0 if OR1_SCY_15
-
-config OR1_PGS
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_PGS_SMALL
- default 0x400 if OR1_PGS_LARGE
-
-config OR1_CSCT
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_CSCT_1_CYCLE
- default 0x0 if OR1_CSCT_2_CYCLE
- default 0x200 if OR1_CSCT_4_CYCLE
- default 0x200 if OR1_CSCT_8_CYCLE
-
-config OR1_CST
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_CST_COINCIDENT
- default 0x100 if OR1_CST_QUARTER_CLOCK
- default 0x0 if OR1_CST_HALF_CLOCK
- default 0x100 if OR1_CST_ONE_CLOCK
-
-config OR1_CHT
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_CHT_HALF_CLOCK
- default 0x80 if OR1_CHT_ONE_CLOCK
- default 0x0 if OR1_CHT_ONE_HALF_CLOCK
- default 0x80 if OR1_CHT_TWO_CLOCK
-
-config OR1_RST
- hex
- default 0x0 if !BR1_MACHINE_FCM
- default 0x0 if OR1_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR1_RST_ONE_CLOCK
- default 0x0 if OR1_RST_ONE_HALF_CLOCK
-
-config OR1_CSNT
- hex
- default 0x0 if !BR1_MACHINE_GPCM
- default 0x0 if OR1_CSNT_NORMAL
- default 0x800 if OR1_CSNT_EARLIER
-
-config OR1_ACS
- hex
- default 0x0 if !BR1_MACHINE_GPCM
- default 0x0 if OR1_ACS_SAME_TIME
- default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER
-
-config OR1_XACS
- hex
- default 0x0 if !BR1_MACHINE_GPCM
- default 0x0 if OR1_XACS_NORMAL
- default 0x100 if OR1_XACS_EXTENDED
-
-config OR1_SETA
- hex
- default 0x0 if !BR1_MACHINE_GPCM
- default 0x0 if OR1_SETA_INTERNAL
- default 0x8 if OR1_SETA_EXTERNAL
-
-config OR1_TRLX
- hex
- default 0x0 if OR1_TRLX_NORMAL
- default 0x4 if OR1_TRLX_RELAXED
-
-config OR1_EHTR
- hex
- default 0x0 if OR1_EHTR_NORMAL
- default 0x2 if OR1_EHTR_1_CYCLE
- default 0x0 if OR1_EHTR_4_CYCLE
- default 0x2 if OR1_EHTR_8_CYCLE
-
-config OR1_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR1_EAD_NONE
- default 0x1 if OR1_EAD_EXTRA
+++ /dev/null
-menuconfig ELBC_BR2_OR2
- bool "ELBC BR2/OR2"
-
-if ELBC_BR2_OR2
-
-config BR2_OR2_NAME
- string "Identifier"
-
-config BR2_OR2_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR2_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR2_PORTSIZE_16BIT
- depends on !BR2_MACHINE_FCM
- bool "16-bit"
-
-
-config BR2_PORTSIZE_32BIT
- depends on !BR2_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR2_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR2_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR2_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR2_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR2_WRITE_PROTECT
- bool "Write-protect"
-
-config BR2_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR2_MACHINE_GPCM
- bool "GPCM"
-
-config BR2_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR2_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR2_MACHINE_UPMA
- select BR2_MACHINE_UPM
- bool "UPM (A)"
-
-config BR2_MACHINE_UPMB
- select BR2_MACHINE_UPM
- bool "UPM (B)"
-
-config BR2_MACHINE_UPMC
- select BR2_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR2_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR2_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR2_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR2_AM_32_KBYTES
- depends on !BR2_MACHINE_SDRAM
- bool "32 kb"
-
-config OR2_AM_64_KBYTES
- bool "64 kb"
-
-config OR2_AM_128_KBYTES
- bool "128 kb"
-
-config OR2_AM_256_KBYTES
- bool "256 kb"
-
-config OR2_AM_512_KBYTES
- bool "512 kb"
-
-config OR2_AM_1_MBYTES
- bool "1 mb"
-
-config OR2_AM_2_MBYTES
- bool "2 mb"
-
-config OR2_AM_4_MBYTES
- bool "4 mb"
-
-config OR2_AM_8_MBYTES
- bool "8 mb"
-
-config OR2_AM_16_MBYTES
- bool "16 mb"
-
-config OR2_AM_32_MBYTES
- bool "32 mb"
-
-config OR2_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR2_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR2_AM_256_MBYTES
- bool "256 mb"
-
-config OR2_AM_512_MBYTES
- depends on BR2_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR2_AM_1_GBYTES
- bool "1 gb"
-
-config OR2_AM_2_GBYTES
- depends on BR2_MACHINE_FCM
- bool "2 gb"
-
-config OR2_AM_4_GBYTES
- depends on BR2_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR2_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR2_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR2_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR2_MACHINE_GPCM || BR2_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR2_SCY_0
- bool "No wait states"
-
-config OR2_SCY_1
- bool "1 wait state"
-
-config OR2_SCY_2
- bool "2 wait states"
-
-config OR2_SCY_3
- bool "3 wait states"
-
-config OR2_SCY_4
- bool "4 wait states"
-
-config OR2_SCY_5
- bool "5 wait states"
-
-config OR2_SCY_6
- bool "6 wait states"
-
-config OR2_SCY_7
- bool "7 wait states"
-
-config OR2_SCY_8
- depends on BR2_MACHINE_GPCM
- bool "8 wait states"
-
-config OR2_SCY_9
- depends on BR2_MACHINE_GPCM
- bool "9 wait states"
-
-config OR2_SCY_10
- depends on BR2_MACHINE_GPCM
- bool "10 wait states"
-
-config OR2_SCY_11
- depends on BR2_MACHINE_GPCM
- bool "11 wait states"
-
-config OR2_SCY_12
- depends on BR2_MACHINE_GPCM
- bool "12 wait states"
-
-config OR2_SCY_13
- depends on BR2_MACHINE_GPCM
- bool "13 wait states"
-
-config OR2_SCY_14
- depends on BR2_MACHINE_GPCM
- bool "14 wait states"
-
-config OR2_SCY_15
- depends on BR2_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM
-
-if BR2_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR2_CSNT_NORMAL
- bool "Normal"
-
-config OR2_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR2_ACS_SAME_TIME
- bool "At the same time"
-
-config OR2_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR2_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR2_XACS_NORMAL
- bool "Normal"
-
-config OR2_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR2_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR2_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR2_MACHINE_GPCM
-
-if BR2_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR2_PGS_SMALL
- bool "Small page device"
-
-config OR2_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR2_CSCT_1_CYCLE
- depends on OR2_TRLX_NORMAL
- bool "1 cycle"
-
-config OR2_CSCT_2_CYCLE
- depends on OR2_TRLX_RELAXED
- bool "2 cycles"
-
-config OR2_CSCT_4_CYCLE
- depends on OR2_TRLX_NORMAL
- bool "4 cycles"
-
-config OR2_CSCT_8_CYCLE
- depends on OR2_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR2_CST_COINCIDENT
- depends on OR2_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR2_CST_QUARTER_CLOCK
- depends on OR2_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR2_CST_HALF_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR2_CST_ONE_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR2_CHT_HALF_CLOCK
- depends on OR2_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR2_CHT_ONE_CLOCK
- depends on OR2_TRLX_NORMAL
- bool "1 clock before"
-
-config OR2_CHT_ONE_HALF_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR2_CHT_TWO_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR2_RST_THREE_QUARTER_CLOCK
- depends on OR2_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR2_RST_ONE_HALF_CLOCK
- depends on OR2_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR2_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR2_MACHINE_FCM
-
-if BR2_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR2_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR2_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR2_MACHINE_UPM
-
-if BR2_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR2_COLS_7
- bool "7"
-
-config OR2_COLS_8
- bool "8"
-
-config OR2_COLS_9
- bool "9"
-
-config OR2_COLS_10
- bool "10"
-
-config OR2_COLS_11
- bool "11"
-
-config OR2_COLS_12
- bool "12"
-
-config OR2_COLS_13
- bool "13"
-
-config OR2_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR2_ROWS_9
- bool "9"
-
-config OR2_ROWS_10
- bool "10"
-
-config OR2_ROWS_11
- bool "11"
-
-config OR2_ROWS_12
- bool "12"
-
-config OR2_ROWS_13
- bool "13"
-
-config OR2_ROWS_14
- bool "14"
-
-config OR2_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR2_PMSEL_BTB
- bool "Back-to-back"
-
-config OR2_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR2_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR2_TRLX_NORMAL
- bool "Normal"
-
-config OR2_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR2_EHTR_NORMAL
- depends on OR2_TRLX_NORMAL
- bool "Normal"
-
-config OR2_EHTR_1_CYCLE
- depends on OR2_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR2_EHTR_4_CYCLE
- depends on OR2_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR2_EHTR_8_CYCLE
- depends on OR2_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR2_EAD_NONE
- bool "None"
-
-config OR2_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR2_OR2
-
-config BR2_PORTSIZE
- hex
- default 0x800 if BR2_PORTSIZE_8BIT
- default 0x1000 if BR2_PORTSIZE_16BIT
- default 0x1800 if BR2_PORTSIZE_32BIT
-
-config BR2_ERRORCHECKING
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if BR2_ERRORCHECKING_DISABLED
- default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR2_ERRORCHECKING_BOTH
-
-config BR2_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR2_WRITE_PROTECT
- default 0x100 if BR2_WRITE_PROTECT
-
-config BR2_MACHINE
- hex
- default 0x0 if BR2_MACHINE_GPCM
- default 0x20 if BR2_MACHINE_FCM
- default 0x60 if BR2_MACHINE_SDRAM
- default 0x80 if BR2_MACHINE_UPMA
- default 0xa0 if BR2_MACHINE_UPMB
- default 0xc0 if BR2_MACHINE_UPMC
-
-config BR2_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR2_ATOMIC_NONE
- default 0x4 if BR2_ATOMIC_RAWA
- default 0x8 if BR2_ATOMIC_WARA
-
-config BR2_VALID_BIT
- hex
- default 0x0 if !ELBC_BR2_OR2
- default 0x1 if ELBC_BR2_OR2
-
-config OR2_AM
- hex
- default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM
- default 0xffff0000 if OR2_AM_64_KBYTES
- default 0xfffe0000 if OR2_AM_128_KBYTES
- default 0xfffc0000 if OR2_AM_256_KBYTES
- default 0xfff80000 if OR2_AM_512_KBYTES
- default 0xfff00000 if OR2_AM_1_MBYTES
- default 0xffe00000 if OR2_AM_2_MBYTES
- default 0xffc00000 if OR2_AM_4_MBYTES
- default 0xff800000 if OR2_AM_8_MBYTES
- default 0xff000000 if OR2_AM_16_MBYTES
- default 0xfe000000 if OR2_AM_32_MBYTES
- default 0xfc000000 if OR2_AM_64_MBYTES
- default 0xf8000000 if OR2_AM_128_MBYTES
- default 0xf0000000 if OR2_AM_256_MBYTES
- default 0xe0000000 if OR2_AM_512_MBYTES
- default 0xc0000000 if OR2_AM_1_GBYTES
- default 0x80000000 if OR2_AM_2_GBYTES
- default 0x00000000 if OR2_AM_4_GBYTES
-
-config OR2_XAM
- hex
- default 0x0 if !OR2_XAM_SET
- default 0x6000 if OR2_XAM_SET
-
-config OR2_BCTLD
- hex
- default 0x0 if OR2_BCTLD_ASSERTED
- default 0x1000 if OR2_BCTLD_NOT_ASSERTED
-
-config OR2_BI
- hex
- default 0x0 if !BR2_MACHINE_UPM
- default 0x0 if OR2_BI_BURSTSUPPORT
- default 0x100 if OR2_BI_BURSTINHIBIT
-
-config OR2_COLS
- hex
- default 0x0 if !BR2_MACHINE_SDRAM
- default 0x0 if OR2_COLS_7
- default 0x400 if OR2_COLS_8
- default 0x800 if OR2_COLS_9
- default 0xc00 if OR2_COLS_10
- default 0x1000 if OR2_COLS_11
- default 0x1400 if OR2_COLS_12
- default 0x1800 if OR2_COLS_13
- default 0x1c00 if OR2_COLS_14
-
-config OR2_ROWS
- hex
- default 0x0 if !BR2_MACHINE_SDRAM
- default 0x0 if OR2_ROWS_9
- default 0x40 if OR2_ROWS_10
- default 0x80 if OR2_ROWS_11
- default 0xc0 if OR2_ROWS_12
- default 0x100 if OR2_ROWS_13
- default 0x140 if OR2_ROWS_14
- default 0x180 if OR2_ROWS_15
-
-config OR2_PMSEL
- hex
- default 0x0 if !BR2_MACHINE_SDRAM
- default 0x0 if OR2_PMSEL_BTB
- default 0x20 if OR2_PMSEL_KEPT_OPEN
-
-config OR2_SCY
- hex
- default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM
- default 0x0 if OR2_SCY_0
- default 0x10 if OR2_SCY_1
- default 0x20 if OR2_SCY_2
- default 0x30 if OR2_SCY_3
- default 0x40 if OR2_SCY_4
- default 0x50 if OR2_SCY_5
- default 0x60 if OR2_SCY_6
- default 0x70 if OR2_SCY_7
- default 0x80 if OR2_SCY_8
- default 0x90 if OR2_SCY_9
- default 0xa0 if OR2_SCY_10
- default 0xb0 if OR2_SCY_11
- default 0xc0 if OR2_SCY_12
- default 0xd0 if OR2_SCY_13
- default 0xe0 if OR2_SCY_14
- default 0xf0 if OR2_SCY_15
-
-config OR2_PGS
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_PGS_SMALL
- default 0x400 if OR2_PGS_LARGE
-
-config OR2_CSCT
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_CSCT_1_CYCLE
- default 0x0 if OR2_CSCT_2_CYCLE
- default 0x200 if OR2_CSCT_4_CYCLE
- default 0x200 if OR2_CSCT_8_CYCLE
-
-config OR2_CST
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_CST_COINCIDENT
- default 0x100 if OR2_CST_QUARTER_CLOCK
- default 0x0 if OR2_CST_HALF_CLOCK
- default 0x100 if OR2_CST_ONE_CLOCK
-
-config OR2_CHT
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_CHT_HALF_CLOCK
- default 0x80 if OR2_CHT_ONE_CLOCK
- default 0x0 if OR2_CHT_ONE_HALF_CLOCK
- default 0x80 if OR2_CHT_TWO_CLOCK
-
-config OR2_RST
- hex
- default 0x0 if !BR2_MACHINE_FCM
- default 0x0 if OR2_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR2_RST_ONE_CLOCK
- default 0x0 if OR2_RST_ONE_HALF_CLOCK
-
-config OR2_CSNT
- hex
- default 0x0 if !BR2_MACHINE_GPCM
- default 0x0 if OR2_CSNT_NORMAL
- default 0x800 if OR2_CSNT_EARLIER
-
-config OR2_ACS
- hex
- default 0x0 if !BR2_MACHINE_GPCM
- default 0x0 if OR2_ACS_SAME_TIME
- default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER
-
-config OR2_XACS
- hex
- default 0x0 if !BR2_MACHINE_GPCM
- default 0x0 if OR2_XACS_NORMAL
- default 0x100 if OR2_XACS_EXTENDED
-
-config OR2_SETA
- hex
- default 0x0 if !BR2_MACHINE_GPCM
- default 0x0 if OR2_SETA_INTERNAL
- default 0x8 if OR2_SETA_EXTERNAL
-
-config OR2_TRLX
- hex
- default 0x0 if OR2_TRLX_NORMAL
- default 0x4 if OR2_TRLX_RELAXED
-
-config OR2_EHTR
- hex
- default 0x0 if OR2_EHTR_NORMAL
- default 0x2 if OR2_EHTR_1_CYCLE
- default 0x0 if OR2_EHTR_4_CYCLE
- default 0x2 if OR2_EHTR_8_CYCLE
-
-config OR2_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR2_EAD_NONE
- default 0x1 if OR2_EAD_EXTRA
+++ /dev/null
-menuconfig ELBC_BR3_OR3
- bool "ELBC BR3/OR3"
-
-if ELBC_BR3_OR3
-
-config BR3_OR3_NAME
- string "Identifier"
-
-config BR3_OR3_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR3_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR3_PORTSIZE_16BIT
- depends on !BR3_MACHINE_FCM
- bool "16-bit"
-
-
-config BR3_PORTSIZE_32BIT
- depends on !BR3_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR3_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR3_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR3_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR3_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR3_WRITE_PROTECT
- bool "Write-protect"
-
-config BR3_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR3_MACHINE_GPCM
- bool "GPCM"
-
-config BR3_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR3_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR3_MACHINE_UPMA
- select BR3_MACHINE_UPM
- bool "UPM (A)"
-
-config BR3_MACHINE_UPMB
- select BR3_MACHINE_UPM
- bool "UPM (B)"
-
-config BR3_MACHINE_UPMC
- select BR3_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR3_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR3_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR3_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR3_AM_32_KBYTES
- depends on !BR3_MACHINE_SDRAM
- bool "32 kb"
-
-config OR3_AM_64_KBYTES
- bool "64 kb"
-
-config OR3_AM_128_KBYTES
- bool "128 kb"
-
-config OR3_AM_256_KBYTES
- bool "256 kb"
-
-config OR3_AM_512_KBYTES
- bool "512 kb"
-
-config OR3_AM_1_MBYTES
- bool "1 mb"
-
-config OR3_AM_2_MBYTES
- bool "2 mb"
-
-config OR3_AM_4_MBYTES
- bool "4 mb"
-
-config OR3_AM_8_MBYTES
- bool "8 mb"
-
-config OR3_AM_16_MBYTES
- bool "16 mb"
-
-config OR3_AM_32_MBYTES
- bool "32 mb"
-
-config OR3_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR3_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR3_AM_256_MBYTES
- bool "256 mb"
-
-config OR3_AM_512_MBYTES
- depends on BR3_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR3_AM_1_GBYTES
- bool "1 gb"
-
-config OR3_AM_2_GBYTES
- depends on BR3_MACHINE_FCM
- bool "2 gb"
-
-config OR3_AM_4_GBYTES
- depends on BR3_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR3_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR3_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR3_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR3_MACHINE_GPCM || BR3_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR3_SCY_0
- bool "No wait states"
-
-config OR3_SCY_1
- bool "1 wait state"
-
-config OR3_SCY_2
- bool "2 wait states"
-
-config OR3_SCY_3
- bool "3 wait states"
-
-config OR3_SCY_4
- bool "4 wait states"
-
-config OR3_SCY_5
- bool "5 wait states"
-
-config OR3_SCY_6
- bool "6 wait states"
-
-config OR3_SCY_7
- bool "7 wait states"
-
-config OR3_SCY_8
- depends on BR3_MACHINE_GPCM
- bool "8 wait states"
-
-config OR3_SCY_9
- depends on BR3_MACHINE_GPCM
- bool "9 wait states"
-
-config OR3_SCY_10
- depends on BR3_MACHINE_GPCM
- bool "10 wait states"
-
-config OR3_SCY_11
- depends on BR3_MACHINE_GPCM
- bool "11 wait states"
-
-config OR3_SCY_12
- depends on BR3_MACHINE_GPCM
- bool "12 wait states"
-
-config OR3_SCY_13
- depends on BR3_MACHINE_GPCM
- bool "13 wait states"
-
-config OR3_SCY_14
- depends on BR3_MACHINE_GPCM
- bool "14 wait states"
-
-config OR3_SCY_15
- depends on BR3_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM
-
-if BR3_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR3_CSNT_NORMAL
- bool "Normal"
-
-config OR3_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR3_ACS_SAME_TIME
- bool "At the same time"
-
-config OR3_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR3_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR3_XACS_NORMAL
- bool "Normal"
-
-config OR3_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR3_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR3_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR3_MACHINE_GPCM
-
-if BR3_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR3_PGS_SMALL
- bool "Small page device"
-
-config OR3_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR3_CSCT_1_CYCLE
- depends on OR3_TRLX_NORMAL
- bool "1 cycle"
-
-config OR3_CSCT_2_CYCLE
- depends on OR3_TRLX_RELAXED
- bool "2 cycles"
-
-config OR3_CSCT_4_CYCLE
- depends on OR3_TRLX_NORMAL
- bool "4 cycles"
-
-config OR3_CSCT_8_CYCLE
- depends on OR3_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR3_CST_COINCIDENT
- depends on OR3_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR3_CST_QUARTER_CLOCK
- depends on OR3_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR3_CST_HALF_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR3_CST_ONE_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR3_CHT_HALF_CLOCK
- depends on OR3_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR3_CHT_ONE_CLOCK
- depends on OR3_TRLX_NORMAL
- bool "1 clock before"
-
-config OR3_CHT_ONE_HALF_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR3_CHT_TWO_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR3_RST_THREE_QUARTER_CLOCK
- depends on OR3_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR3_RST_ONE_HALF_CLOCK
- depends on OR3_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR3_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR3_MACHINE_FCM
-
-if BR3_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR3_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR3_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR3_MACHINE_UPM
-
-if BR3_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR3_COLS_7
- bool "7"
-
-config OR3_COLS_8
- bool "8"
-
-config OR3_COLS_9
- bool "9"
-
-config OR3_COLS_10
- bool "10"
-
-config OR3_COLS_11
- bool "11"
-
-config OR3_COLS_12
- bool "12"
-
-config OR3_COLS_13
- bool "13"
-
-config OR3_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR3_ROWS_9
- bool "9"
-
-config OR3_ROWS_10
- bool "10"
-
-config OR3_ROWS_11
- bool "11"
-
-config OR3_ROWS_12
- bool "12"
-
-config OR3_ROWS_13
- bool "13"
-
-config OR3_ROWS_14
- bool "14"
-
-config OR3_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR3_PMSEL_BTB
- bool "Back-to-back"
-
-config OR3_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR3_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR3_TRLX_NORMAL
- bool "Normal"
-
-config OR3_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR3_EHTR_NORMAL
- depends on OR3_TRLX_NORMAL
- bool "Normal"
-
-config OR3_EHTR_1_CYCLE
- depends on OR3_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR3_EHTR_4_CYCLE
- depends on OR3_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR3_EHTR_8_CYCLE
- depends on OR3_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR3_EAD_NONE
- bool "None"
-
-config OR3_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR3_OR3
-
-config BR3_PORTSIZE
- hex
- default 0x800 if BR3_PORTSIZE_8BIT
- default 0x1000 if BR3_PORTSIZE_16BIT
- default 0x1800 if BR3_PORTSIZE_32BIT
-
-config BR3_ERRORCHECKING
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if BR3_ERRORCHECKING_DISABLED
- default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR3_ERRORCHECKING_BOTH
-
-config BR3_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR3_WRITE_PROTECT
- default 0x100 if BR3_WRITE_PROTECT
-
-config BR3_MACHINE
- hex
- default 0x0 if BR3_MACHINE_GPCM
- default 0x20 if BR3_MACHINE_FCM
- default 0x60 if BR3_MACHINE_SDRAM
- default 0x80 if BR3_MACHINE_UPMA
- default 0xa0 if BR3_MACHINE_UPMB
- default 0xc0 if BR3_MACHINE_UPMC
-
-config BR3_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR3_ATOMIC_NONE
- default 0x4 if BR3_ATOMIC_RAWA
- default 0x8 if BR3_ATOMIC_WARA
-
-config BR3_VALID_BIT
- hex
- default 0x0 if !ELBC_BR3_OR3
- default 0x1 if ELBC_BR3_OR3
-
-config OR3_AM
- hex
- default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM
- default 0xffff0000 if OR3_AM_64_KBYTES
- default 0xfffe0000 if OR3_AM_128_KBYTES
- default 0xfffc0000 if OR3_AM_256_KBYTES
- default 0xfff80000 if OR3_AM_512_KBYTES
- default 0xfff00000 if OR3_AM_1_MBYTES
- default 0xffe00000 if OR3_AM_2_MBYTES
- default 0xffc00000 if OR3_AM_4_MBYTES
- default 0xff800000 if OR3_AM_8_MBYTES
- default 0xff000000 if OR3_AM_16_MBYTES
- default 0xfe000000 if OR3_AM_32_MBYTES
- default 0xfc000000 if OR3_AM_64_MBYTES
- default 0xf8000000 if OR3_AM_128_MBYTES
- default 0xf0000000 if OR3_AM_256_MBYTES
- default 0xe0000000 if OR3_AM_512_MBYTES
- default 0xc0000000 if OR3_AM_1_GBYTES
- default 0x80000000 if OR3_AM_2_GBYTES
- default 0x00000000 if OR3_AM_4_GBYTES
-
-config OR3_XAM
- hex
- default 0x0 if !OR3_XAM_SET
- default 0x6000 if OR3_XAM_SET
-
-config OR3_BCTLD
- hex
- default 0x0 if OR3_BCTLD_ASSERTED
- default 0x1000 if OR3_BCTLD_NOT_ASSERTED
-
-config OR3_BI
- hex
- default 0x0 if !BR3_MACHINE_UPM
- default 0x0 if OR3_BI_BURSTSUPPORT
- default 0x100 if OR3_BI_BURSTINHIBIT
-
-config OR3_COLS
- hex
- default 0x0 if !BR3_MACHINE_SDRAM
- default 0x0 if OR3_COLS_7
- default 0x400 if OR3_COLS_8
- default 0x800 if OR3_COLS_9
- default 0xc00 if OR3_COLS_10
- default 0x1000 if OR3_COLS_11
- default 0x1400 if OR3_COLS_12
- default 0x1800 if OR3_COLS_13
- default 0x1c00 if OR3_COLS_14
-
-config OR3_ROWS
- hex
- default 0x0 if !BR3_MACHINE_SDRAM
- default 0x0 if OR3_ROWS_9
- default 0x40 if OR3_ROWS_10
- default 0x80 if OR3_ROWS_11
- default 0xc0 if OR3_ROWS_12
- default 0x100 if OR3_ROWS_13
- default 0x140 if OR3_ROWS_14
- default 0x180 if OR3_ROWS_15
-
-config OR3_PMSEL
- hex
- default 0x0 if !BR3_MACHINE_SDRAM
- default 0x0 if OR3_PMSEL_BTB
- default 0x20 if OR3_PMSEL_KEPT_OPEN
-
-config OR3_SCY
- hex
- default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM
- default 0x0 if OR3_SCY_0
- default 0x10 if OR3_SCY_1
- default 0x20 if OR3_SCY_2
- default 0x30 if OR3_SCY_3
- default 0x40 if OR3_SCY_4
- default 0x50 if OR3_SCY_5
- default 0x60 if OR3_SCY_6
- default 0x70 if OR3_SCY_7
- default 0x80 if OR3_SCY_8
- default 0x90 if OR3_SCY_9
- default 0xa0 if OR3_SCY_10
- default 0xb0 if OR3_SCY_11
- default 0xc0 if OR3_SCY_12
- default 0xd0 if OR3_SCY_13
- default 0xe0 if OR3_SCY_14
- default 0xf0 if OR3_SCY_15
-
-config OR3_PGS
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_PGS_SMALL
- default 0x400 if OR3_PGS_LARGE
-
-config OR3_CSCT
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_CSCT_1_CYCLE
- default 0x0 if OR3_CSCT_2_CYCLE
- default 0x200 if OR3_CSCT_4_CYCLE
- default 0x200 if OR3_CSCT_8_CYCLE
-
-config OR3_CST
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_CST_COINCIDENT
- default 0x100 if OR3_CST_QUARTER_CLOCK
- default 0x0 if OR3_CST_HALF_CLOCK
- default 0x100 if OR3_CST_ONE_CLOCK
-
-config OR3_CHT
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_CHT_HALF_CLOCK
- default 0x80 if OR3_CHT_ONE_CLOCK
- default 0x0 if OR3_CHT_ONE_HALF_CLOCK
- default 0x80 if OR3_CHT_TWO_CLOCK
-
-config OR3_RST
- hex
- default 0x0 if !BR3_MACHINE_FCM
- default 0x0 if OR3_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR3_RST_ONE_CLOCK
- default 0x0 if OR3_RST_ONE_HALF_CLOCK
-
-config OR3_CSNT
- hex
- default 0x0 if !BR3_MACHINE_GPCM
- default 0x0 if OR3_CSNT_NORMAL
- default 0x800 if OR3_CSNT_EARLIER
-
-config OR3_ACS
- hex
- default 0x0 if !BR3_MACHINE_GPCM
- default 0x0 if OR3_ACS_SAME_TIME
- default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER
-
-config OR3_XACS
- hex
- default 0x0 if !BR3_MACHINE_GPCM
- default 0x0 if OR3_XACS_NORMAL
- default 0x100 if OR3_XACS_EXTENDED
-
-config OR3_SETA
- hex
- default 0x0 if !BR3_MACHINE_GPCM
- default 0x0 if OR3_SETA_INTERNAL
- default 0x8 if OR3_SETA_EXTERNAL
-
-config OR3_TRLX
- hex
- default 0x0 if OR3_TRLX_NORMAL
- default 0x4 if OR3_TRLX_RELAXED
-
-config OR3_EHTR
- hex
- default 0x0 if OR3_EHTR_NORMAL
- default 0x2 if OR3_EHTR_1_CYCLE
- default 0x0 if OR3_EHTR_4_CYCLE
- default 0x2 if OR3_EHTR_8_CYCLE
-
-config OR3_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR3_EAD_NONE
- default 0x1 if OR3_EAD_EXTRA
+++ /dev/null
-menuconfig ELBC_BR4_OR4
- bool "ELBC BR4/OR4"
-
-if ELBC_BR4_OR4
-
-config BR4_OR4_NAME
- string "Identifier"
-
-config BR4_OR4_BASE
- hex "Port base"
-
-choice
- prompt "Port size"
-
-config BR4_PORTSIZE_8BIT
- bool "8-bit"
-
-config BR4_PORTSIZE_16BIT
- depends on !BR4_MACHINE_FCM
- bool "16-bit"
-
-
-config BR4_PORTSIZE_32BIT
- depends on !BR4_MACHINE_FCM
- depends on ARCH_MPC8360 || ARCH_MPC8379
- bool "32-bit"
-
-endchoice
-
-if BR4_MACHINE_FCM
-
-choice
- prompt "Data Error Checking"
-
-config BR4_ERRORCHECKING_DISABLED
- bool "Disabled"
-
-config BR4_ERRORCHECKING_ECC_CHECKING
- bool "ECC checking / No ECC generation"
-
-config BR4_ERRORCHECKING_BOTH
- bool "ECC checking and generation"
-
-endchoice
-
-endif
-
-config BR4_WRITE_PROTECT
- bool "Write-protect"
-
-config BR4_MACHINE_UPM
- bool
-
-choice
- prompt "Machine select"
-
-config BR4_MACHINE_GPCM
- bool "GPCM"
-
-config BR4_MACHINE_FCM
- depends on !ARCH_MPC832X && !ARCH_MPC8360
- bool "FCM"
-
-config BR4_MACHINE_SDRAM
- depends on ARCH_MPC8360
- bool "SDRAM"
-
-config BR4_MACHINE_UPMA
- select BR4_MACHINE_UPM
- bool "UPM (A)"
-
-config BR4_MACHINE_UPMB
- select BR4_MACHINE_UPM
- bool "UPM (B)"
-
-config BR4_MACHINE_UPMC
- select BR4_MACHINE_UPM
- bool "UPM (C)"
-
-endchoice
-
-if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
-
-choice
- prompt "Atomic operations"
-
-config BR4_ATOMIC_NONE
- bool "No atomic operations"
-
-config BR4_ATOMIC_RAWA
- bool "Read-after-write-atomic"
-
-config BR4_ATOMIC_WARA
- bool "Write-after-read-atomic"
-
-endchoice
-
-endif
-
-if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM
-
-choice
- prompt "Address mask"
-
-config OR4_AM_32_KBYTES
- depends on !BR4_MACHINE_SDRAM
- bool "32 kb"
-
-config OR4_AM_64_KBYTES
- bool "64 kb"
-
-config OR4_AM_128_KBYTES
- bool "128 kb"
-
-config OR4_AM_256_KBYTES
- bool "256 kb"
-
-config OR4_AM_512_KBYTES
- bool "512 kb"
-
-config OR4_AM_1_MBYTES
- bool "1 mb"
-
-config OR4_AM_2_MBYTES
- bool "2 mb"
-
-config OR4_AM_4_MBYTES
- bool "4 mb"
-
-config OR4_AM_8_MBYTES
- bool "8 mb"
-
-config OR4_AM_16_MBYTES
- bool "16 mb"
-
-config OR4_AM_32_MBYTES
- bool "32 mb"
-
-config OR4_AM_64_MBYTES
- bool "64 mb"
-
-# XXX: Some boards define 128MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR4_AM_128_MBYTES
- bool "128 mb"
-
-# XXX: Some boards define 256MB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR4_AM_256_MBYTES
- bool "256 mb"
-
-config OR4_AM_512_MBYTES
- depends on BR4_MACHINE_FCM
- bool "512 mb"
-
-# XXX: Some boards define 1GB AM with GPCM, even though it should not be
-# possible according to the manuals
-config OR4_AM_1_GBYTES
- bool "1 gb"
-
-config OR4_AM_2_GBYTES
- depends on BR4_MACHINE_FCM
- bool "2 gb"
-
-config OR4_AM_4_GBYTES
- depends on BR4_MACHINE_FCM
- bool "4 gb"
-
-endchoice
-
-config OR4_XAM_SET
- bool "Set unused bytes after address mask"
-choice
- prompt "Buffer control disable"
-
-config OR4_BCTLD_ASSERTED
- bool "Asserted"
-
-config OR4_BCTLD_NOT_ASSERTED
- bool "Not asserted"
-
-endchoice
-
-endif
-
-if BR4_MACHINE_GPCM || BR4_MACHINE_FCM
-
-choice
- prompt "Cycle length in bus clocks"
-
-config OR4_SCY_0
- bool "No wait states"
-
-config OR4_SCY_1
- bool "1 wait state"
-
-config OR4_SCY_2
- bool "2 wait states"
-
-config OR4_SCY_3
- bool "3 wait states"
-
-config OR4_SCY_4
- bool "4 wait states"
-
-config OR4_SCY_5
- bool "5 wait states"
-
-config OR4_SCY_6
- bool "6 wait states"
-
-config OR4_SCY_7
- bool "7 wait states"
-
-config OR4_SCY_8
- depends on BR4_MACHINE_GPCM
- bool "8 wait states"
-
-config OR4_SCY_9
- depends on BR4_MACHINE_GPCM
- bool "9 wait states"
-
-config OR4_SCY_10
- depends on BR4_MACHINE_GPCM
- bool "10 wait states"
-
-config OR4_SCY_11
- depends on BR4_MACHINE_GPCM
- bool "11 wait states"
-
-config OR4_SCY_12
- depends on BR4_MACHINE_GPCM
- bool "12 wait states"
-
-config OR4_SCY_13
- depends on BR4_MACHINE_GPCM
- bool "13 wait states"
-
-config OR4_SCY_14
- depends on BR4_MACHINE_GPCM
- bool "14 wait states"
-
-config OR4_SCY_15
- depends on BR4_MACHINE_GPCM
- bool "15 wait states"
-
-endchoice
-
-endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM
-
-if BR4_MACHINE_GPCM
-
-choice
- prompt "Chip select negotiation time"
-
-config OR4_CSNT_NORMAL
- bool "Normal"
-
-config OR4_CSNT_EARLIER
- bool "Earlier"
-
-endchoice
-
-choice
- prompt "Address to chip-select setup"
-
-config OR4_ACS_SAME_TIME
- bool "At the same time"
-
-config OR4_ACS_HALF_CYCLE_EARLIER
- bool "Half of a bus clock cycle earlier"
-
-config OR4_ACS_QUARTER_CYCLE_EARLIER
- bool "Half/Quarter of a bus clock cycle earlier"
-
-endchoice
-
-choice
- prompt "Extra address to check-select setup"
-
-config OR4_XACS_NORMAL
- bool "Normal"
-
-config OR4_XACS_EXTENDED
- bool "Extended"
-
-endchoice
-
-choice
- prompt "External address termination"
-
-config OR4_SETA_INTERNAL
- bool "Access is terminated internally"
-
-config OR4_SETA_EXTERNAL
- bool "Access is terminated externally"
-
-endchoice
-
-endif # BR4_MACHINE_GPCM
-
-if BR4_MACHINE_FCM
-
-choice
- prompt "NAND Flash EEPROM page size"
-
-config OR4_PGS_SMALL
- bool "Small page device"
-
-config OR4_PGS_LARGE
- bool "Large page device"
-
-endchoice
-
-choice
- prompt "Chip select to command time"
-
-config OR4_CSCT_1_CYCLE
- depends on OR4_TRLX_NORMAL
- bool "1 cycle"
-
-config OR4_CSCT_2_CYCLE
- depends on OR4_TRLX_RELAXED
- bool "2 cycles"
-
-config OR4_CSCT_4_CYCLE
- depends on OR4_TRLX_NORMAL
- bool "4 cycles"
-
-config OR4_CSCT_8_CYCLE
- depends on OR4_TRLX_RELAXED
- bool "8 cycles"
-
-endchoice
-
-choice
- prompt "Command setup time"
-
-config OR4_CST_COINCIDENT
- depends on OR4_TRLX_NORMAL
- bool "Coincident with any command"
-
-config OR4_CST_QUARTER_CLOCK
- depends on OR4_TRLX_NORMAL
- bool "0.25 clocks after"
-
-config OR4_CST_HALF_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "0.5 clocks after"
-
-config OR4_CST_ONE_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "1 clock after"
-
-endchoice
-
-choice
- prompt "Command hold time"
-
-config OR4_CHT_HALF_CLOCK
- depends on OR4_TRLX_NORMAL
- bool "0.5 clocks before"
-
-config OR4_CHT_ONE_CLOCK
- depends on OR4_TRLX_NORMAL
- bool "1 clock before"
-
-config OR4_CHT_ONE_HALF_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "1.5 clocks before"
-
-config OR4_CHT_TWO_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "2 clocks before"
-
-endchoice
-
-choice
- prompt "Reset setup time"
-
-config OR4_RST_THREE_QUARTER_CLOCK
- depends on OR4_TRLX_NORMAL
- bool "0.75 clocks prior"
-
-config OR4_RST_ONE_HALF_CLOCK
- depends on OR4_TRLX_RELAXED
- bool "0.5 clocks prior"
-
-config OR4_RST_ONE_CLOCK
- bool "1 clock prior"
-
-endchoice
-
-endif # BR4_MACHINE_FCM
-
-if BR4_MACHINE_UPM
-
-choice
- prompt "Burst inhibit"
-
-config OR4_BI_BURSTSUPPORT
- bool "Support burst access"
-
-config OR4_BI_BURSTINHIBIT
- bool "Inhibit burst access"
-
-endchoice
-
-endif # BR4_MACHINE_UPM
-
-if BR4_MACHINE_SDRAM
-
-choice
- prompt "Number of column address lines"
-
-config OR4_COLS_7
- bool "7"
-
-config OR4_COLS_8
- bool "8"
-
-config OR4_COLS_9
- bool "9"
-
-config OR4_COLS_10
- bool "10"
-
-config OR4_COLS_11
- bool "11"
-
-config OR4_COLS_12
- bool "12"
-
-config OR4_COLS_13
- bool "13"
-
-config OR4_COLS_14
- bool "14"
-
-endchoice
-
-choice
- prompt "Number of rows address lines"
-
-config OR4_ROWS_9
- bool "9"
-
-config OR4_ROWS_10
- bool "10"
-
-config OR4_ROWS_11
- bool "11"
-
-config OR4_ROWS_12
- bool "12"
-
-config OR4_ROWS_13
- bool "13"
-
-config OR4_ROWS_14
- bool "14"
-
-config OR4_ROWS_15
- bool "15"
-
-endchoice
-
-choice
- prompt "Page mode select"
-
-config OR4_PMSEL_BTB
- bool "Back-to-back"
-
-config OR4_PMSEL_KEPT_OPEN
- bool "Page kept open until page miss or refresh"
-
-endchoice
-
-endif # BR4_MACHINE_SDRAM
-
-choice
- prompt "Relaxed timing"
-
-config OR4_TRLX_NORMAL
- bool "Normal"
-
-config OR4_TRLX_RELAXED
- bool "Relaxed"
-
-endchoice
-
-choice
- prompt "Extended hold time"
-
-config OR4_EHTR_NORMAL
- depends on OR4_TRLX_NORMAL
- bool "Normal"
-
-config OR4_EHTR_1_CYCLE
- depends on OR4_TRLX_NORMAL
- bool "1 idle clock cycle inserted"
-
-config OR4_EHTR_4_CYCLE
- depends on OR4_TRLX_RELAXED
- bool "4 idle clock cycles inserted"
-
-config OR4_EHTR_8_CYCLE
- depends on OR4_TRLX_RELAXED
- bool "8 idle clock cycles inserted"
-
-endchoice
-
-if !ARCH_MPC8308
-
-choice
- prompt "External address latch delay"
-
-config OR4_EAD_NONE
- bool "None"
-
-config OR4_EAD_EXTRA
- bool "Extra"
-
-endchoice
-
-endif # !ARCH_MPC8308
-
-endif # ELBC_BR4_OR4
-
-config BR4_PORTSIZE
- hex
- default 0x800 if BR4_PORTSIZE_8BIT
- default 0x1000 if BR4_PORTSIZE_16BIT
- default 0x1800 if BR4_PORTSIZE_32BIT
-
-config BR4_ERRORCHECKING
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if BR4_ERRORCHECKING_DISABLED
- default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING
- default 0x400 if BR4_ERRORCHECKING_BOTH
-
-config BR4_WRITE_PROTECT_BIT
- hex
- default 0x0 if !BR4_WRITE_PROTECT
- default 0x100 if BR4_WRITE_PROTECT
-
-config BR4_MACHINE
- hex
- default 0x0 if BR4_MACHINE_GPCM
- default 0x20 if BR4_MACHINE_FCM
- default 0x60 if BR4_MACHINE_SDRAM
- default 0x80 if BR4_MACHINE_UPMA
- default 0xa0 if BR4_MACHINE_UPMB
- default 0xc0 if BR4_MACHINE_UPMC
-
-config BR4_ATOMIC
- hex
- default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
- default 0x0 if BR4_ATOMIC_NONE
- default 0x4 if BR4_ATOMIC_RAWA
- default 0x8 if BR4_ATOMIC_WARA
-
-config BR4_VALID_BIT
- hex
- default 0x0 if !ELBC_BR4_OR4
- default 0x1 if ELBC_BR4_OR4
-
-config OR4_AM
- hex
- default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM
- default 0xffff0000 if OR4_AM_64_KBYTES
- default 0xfffe0000 if OR4_AM_128_KBYTES
- default 0xfffc0000 if OR4_AM_256_KBYTES
- default 0xfff80000 if OR4_AM_512_KBYTES
- default 0xfff00000 if OR4_AM_1_MBYTES
- default 0xffe00000 if OR4_AM_2_MBYTES
- default 0xffc00000 if OR4_AM_4_MBYTES
- default 0xff800000 if OR4_AM_8_MBYTES
- default 0xff000000 if OR4_AM_16_MBYTES
- default 0xfe000000 if OR4_AM_32_MBYTES
- default 0xfc000000 if OR4_AM_64_MBYTES
- default 0xf8000000 if OR4_AM_128_MBYTES
- default 0xf0000000 if OR4_AM_256_MBYTES
- default 0xe0000000 if OR4_AM_512_MBYTES
- default 0xc0000000 if OR4_AM_1_GBYTES
- default 0x80000000 if OR4_AM_2_GBYTES
- default 0x00000000 if OR4_AM_4_GBYTES
-
-config OR4_XAM
- hex
- default 0x0 if !OR4_XAM_SET
- default 0x6000 if OR4_XAM_SET
-
-config OR4_BCTLD
- hex
- default 0x0 if OR4_BCTLD_ASSERTED
- default 0x1000 if OR4_BCTLD_NOT_ASSERTED
-
-config OR4_BI
- hex
- default 0x0 if !BR4_MACHINE_UPM
- default 0x0 if OR4_BI_BURSTSUPPORT
- default 0x100 if OR4_BI_BURSTINHIBIT
-
-config OR4_COLS
- hex
- default 0x0 if !BR4_MACHINE_SDRAM
- default 0x0 if OR4_COLS_7
- default 0x400 if OR4_COLS_8
- default 0x800 if OR4_COLS_9
- default 0xc00 if OR4_COLS_10
- default 0x1000 if OR4_COLS_11
- default 0x1400 if OR4_COLS_12
- default 0x1800 if OR4_COLS_13
- default 0x1c00 if OR4_COLS_14
-
-config OR4_ROWS
- hex
- default 0x0 if !BR4_MACHINE_SDRAM
- default 0x0 if OR4_ROWS_9
- default 0x40 if OR4_ROWS_10
- default 0x80 if OR4_ROWS_11
- default 0xc0 if OR4_ROWS_12
- default 0x100 if OR4_ROWS_13
- default 0x140 if OR4_ROWS_14
- default 0x180 if OR4_ROWS_15
-
-config OR4_PMSEL
- hex
- default 0x0 if !BR4_MACHINE_SDRAM
- default 0x0 if OR4_PMSEL_BTB
- default 0x20 if OR4_PMSEL_KEPT_OPEN
-
-config OR4_SCY
- hex
- default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM
- default 0x0 if OR4_SCY_0
- default 0x10 if OR4_SCY_1
- default 0x20 if OR4_SCY_2
- default 0x30 if OR4_SCY_3
- default 0x40 if OR4_SCY_4
- default 0x50 if OR4_SCY_5
- default 0x60 if OR4_SCY_6
- default 0x70 if OR4_SCY_7
- default 0x80 if OR4_SCY_8
- default 0x90 if OR4_SCY_9
- default 0xa0 if OR4_SCY_10
- default 0xb0 if OR4_SCY_11
- default 0xc0 if OR4_SCY_12
- default 0xd0 if OR4_SCY_13
- default 0xe0 if OR4_SCY_14
- default 0xf0 if OR4_SCY_15
-
-config OR4_PGS
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_PGS_SMALL
- default 0x400 if OR4_PGS_LARGE
-
-config OR4_CSCT
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_CSCT_1_CYCLE
- default 0x0 if OR4_CSCT_2_CYCLE
- default 0x200 if OR4_CSCT_4_CYCLE
- default 0x200 if OR4_CSCT_8_CYCLE
-
-config OR4_CST
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_CST_COINCIDENT
- default 0x100 if OR4_CST_QUARTER_CLOCK
- default 0x0 if OR4_CST_HALF_CLOCK
- default 0x100 if OR4_CST_ONE_CLOCK
-
-config OR4_CHT
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_CHT_HALF_CLOCK
- default 0x80 if OR4_CHT_ONE_CLOCK
- default 0x0 if OR4_CHT_ONE_HALF_CLOCK
- default 0x80 if OR4_CHT_TWO_CLOCK
-
-config OR4_RST
- hex
- default 0x0 if !BR4_MACHINE_FCM
- default 0x0 if OR4_RST_THREE_QUARTER_CLOCK
- default 0x8 if OR4_RST_ONE_CLOCK
- default 0x0 if OR4_RST_ONE_HALF_CLOCK
-
-config OR4_CSNT
- hex
- default 0x0 if !BR4_MACHINE_GPCM
- default 0x0 if OR4_CSNT_NORMAL
- default 0x800 if OR4_CSNT_EARLIER
-
-config OR4_ACS
- hex
- default 0x0 if !BR4_MACHINE_GPCM
- default 0x0 if OR4_ACS_SAME_TIME
- default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER
- default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER
-
-config OR4_XACS
- hex
- default 0x0 if !BR4_MACHINE_GPCM
- default 0x0 if OR4_XACS_NORMAL
- default 0x100 if OR4_XACS_EXTENDED
-
-config OR4_SETA
- hex
- default 0x0 if !BR4_MACHINE_GPCM
- default 0x0 if OR4_SETA_INTERNAL
- default 0x8 if OR4_SETA_EXTERNAL
-
-config OR4_TRLX
- hex
- default 0x0 if OR4_TRLX_NORMAL
- default 0x4 if OR4_TRLX_RELAXED
-
-config OR4_EHTR
- hex
- default 0x0 if OR4_EHTR_NORMAL
- default 0x2 if OR4_EHTR_1_CYCLE
- default 0x0 if OR4_EHTR_4_CYCLE
- default 0x2 if OR4_EHTR_8_CYCLE
-
-config OR4_EAD
- hex
- default 0x0 if ARCH_MPC8308
- default 0x0 if OR4_EAD_NONE
- default 0x1 if OR4_EAD_EXTRA
CONFIG_LBLAW2_BASE=0xF0000000
CONFIG_LBLAW2_NAME="VSC7385"
CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_LBLAW2_BASE=0xE0700000
CONFIG_LBLAW2_NAME="FPGA1"
CONFIG_LBLAW2_LENGTH_1_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA0"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_SCY_5=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="FPGA1"
-CONFIG_BR2_OR2_BASE=0xE0700000
-CONFIG_BR2_PORTSIZE_16BIT=y
-CONFIG_OR2_AM_1_MBYTES=y
-CONFIG_OR2_SCY_5=y
-CONFIG_OR2_CSNT_EARLIER=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_LBLAW3_BASE=0xA0000000
CONFIG_LBLAW3_NAME="PAXE"
CONFIG_LBLAW3_LENGTH_512_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_64_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PAXE"
-CONFIG_BR3_OR3_BASE=0xA0000000
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_2=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_ELBC_BR4_OR4=y
-CONFIG_BR4_OR4_NAME="BFTIC3"
-CONFIG_BR4_OR4_BASE=0xB0000000
-CONFIG_OR4_AM_256_MBYTES=y
-CONFIG_OR4_SCY_2=y
-CONFIG_OR4_CSNT_EARLIER=y
-CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR4_TRLX_RELAXED=y
-CONFIG_OR4_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_LBLAW3_BASE=0xA0000000
CONFIG_LBLAW3_NAME="PAXE"
CONFIG_LBLAW3_LENGTH_512_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_64_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PAXE"
-CONFIG_BR3_OR3_BASE=0xA0000000
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_2=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_LBLAW3_BASE=0xB0000000
CONFIG_LBLAW3_NAME="APP2"
CONFIG_LBLAW3_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_4=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_LBLAW2_BASE=0xA0000000
CONFIG_LBLAW2_NAME="APP1"
CONFIG_LBLAW2_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_LBLAW3_BASE=0xB0000000
CONFIG_LBLAW3_NAME="APP2"
CONFIG_LBLAW3_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_4=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_LBLAW2_BASE=0xA0000000
CONFIG_LBLAW2_NAME="APP1"
CONFIG_LBLAW2_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_LBLAW3_BASE=0xB0000000
CONFIG_LBLAW3_NAME="APP2"
CONFIG_LBLAW3_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_OR2_SCY_2=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_2=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_TRLX_RELAXED=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
projects / u-boot.git / commitdiff