rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPL

Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index c7855135906f724a5ad3461e3aa5c111e6b77a98..8cccd7e22659c9c7efb41a575788471da6525617 100644 (file)
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -12,6 +12,54 @@
        };
 };
 
+&emmc_bus8 {
+       bootph-all;
+};
+
+&emmc_clk {
+       bootph-all;
+};
+
+&emmc_cmd {
+       bootph-all;
+};
+
+&emmc_datastrobe {
+       bootph-all;
+};
+
+&pinctrl {
+       bootph-all;
+};
+
+&pcfg_pull_none {
+       bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+       bootph-all;
+};
+
+&pcfg_pull_up {
+       bootph-all;
+};
+
+&sdmmc0_bus4 {
+       bootph-all;
+};
+
+&sdmmc0_clk {
+       bootph-all;
+};
+
+&sdmmc0_cmd {
+       bootph-all;
+};
+
+&sdmmc0_det {
+       bootph-all;
+};
+
 &sdhci {
        cap-mmc-highspeed;
        mmc-ddr-1_8v;
@@ -28,6 +76,10 @@
        status = "disabled";
 };
 
+&uart2m0_xfer {
+       bootph-all;
+};
+
 &uart2 {
        clock-frequency = <24000000>;
        bootph-all;

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 5126feb6b11dc3861212fc7d3f25345f4cb57f56..2e556dc2c1a211233a52c18805512717cd496728 100644 (file)
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -63,6 +63,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y