+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Author: Shaveta Leekha <shaveta@freescale.com>
- */
-
-#include "idt8t49n222a_serdes_clk.h"
-#include <log.h>
-#include <linux/delay.h>
-
-#define DEVICE_ID_REG 0x00
-
-static int check_pll_status(u8 idt_addr)
-{
- u8 val = 0;
- int ret;
-
- ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
- if (ret < 0) {
- printf("IDT:0x%x could not read status register from device.\n",
- idt_addr);
- return ret;
- }
-
- if (val & 0x04) {
- debug("idt8t49n222a PLL is LOCKED: %x\n", val);
- } else {
- printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
- return -1;
- }
-
- return 0;
-}
-
-int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
- enum serdes_refclk refclk1,
- enum serdes_refclk refclk2, u8 feedback)
-{
- u8 dev_id = 0;
- int i, ret;
-
- debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
- idt_addr);
-
- ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
- if (ret < 0) {
- debug("IDT:0x%x could not read DEV_ID from device.\n",
- idt_addr);
- return ret;
- }
-
- if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
- debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
- idt_addr);
- }
-
- if (serdes_num != 1 && serdes_num != 2) {
- debug("serdes_num should be 1 for SerDes1 and"
- " 2 for SerDes2.\n");
- return -1;
- }
-
- if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
- || (refclk1 != SERDES_REFCLK_122_88
- && refclk2 == SERDES_REFCLK_122_88)) {
- debug("Only one refclk at 122.88MHz is not supported."
- " Please set both refclk1 & refclk2 to 122.88MHz"
- " or both not to 122.88MHz.\n");
- return -1;
- }
-
- if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
- && refclk1 != SERDES_REFCLK_125
- && refclk1 != SERDES_REFCLK_156_25) {
- debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
- " or 156.25MHz.\n");
- return -1;
- }
-
- if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
- && refclk2 != SERDES_REFCLK_125
- && refclk2 != SERDES_REFCLK_156_25) {
- debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
- " or 156.25MHz.\n");
- return -1;
- }
-
- if (feedback != 0 && feedback != 1) {
- debug("valid values for feedback are 0(default) or 1.\n");
- return -1;
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
- */
- if (refclk1 == SERDES_REFCLK_122_88 &&
- refclk2 == SERDES_REFCLK_122_88) {
- printf("Setting refclk1:122.88 and refclk2:122.88\n");
- for (i = 0; i < NUM_IDT_REGS; i++)
- i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
- idt_conf_122_88[i][1]);
-
- if (feedback) {
- for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
- i2c_reg_write(idt_addr,
- idt_conf_122_88_feedback[i][0],
- idt_conf_122_88_feedback[i][1]);
- }
- }
-
- if (refclk1 != SERDES_REFCLK_122_88 &&
- refclk2 != SERDES_REFCLK_122_88) {
- for (i = 0; i < NUM_IDT_REGS; i++)
- i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
- idt_conf_not_122_88[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 100MHz Refclk2 = 125MHz
- */
- if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
- printf("Setting refclk1:100 and refclk2:125\n");
- i2c_reg_write(idt_addr, 0x11, 0x10);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 125MHz Refclk2 = 125MHz
- */
- if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
- printf("Setting refclk1:125 and refclk2:125\n");
- i2c_reg_write(idt_addr, 0x10, 0x10);
- i2c_reg_write(idt_addr, 0x11, 0x10);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 125MHz Refclk2 = 100MHz
- */
- if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
- printf("Setting refclk1:125 and refclk2:100\n");
- i2c_reg_write(idt_addr, 0x10, 0x10);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 156.25MHz Refclk2 = 156.25MHz
- */
- if (refclk1 == SERDES_REFCLK_156_25 &&
- refclk2 == SERDES_REFCLK_156_25) {
- printf("Setting refclk1:156.25 and refclk2:156.25\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
- idt_conf_156_25[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 100MHz Refclk2 = 156.25MHz
- */
- if (refclk1 == SERDES_REFCLK_100 &&
- refclk2 == SERDES_REFCLK_156_25) {
- printf("Setting refclk1:100 and refclk2:156.25\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
- idt_conf_100_156_25[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 125MHz Refclk2 = 156.25MHz
- */
- if (refclk1 == SERDES_REFCLK_125 &&
- refclk2 == SERDES_REFCLK_156_25) {
- printf("Setting refclk1:125 and refclk2:156.25\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
- idt_conf_125_156_25[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 156.25MHz Refclk2 = 100MHz
- */
- if (refclk1 == SERDES_REFCLK_156_25 &&
- refclk2 == SERDES_REFCLK_100) {
- printf("Setting refclk1:156.25 and refclk2:100\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
- idt_conf_156_25_100[i][1]);
- }
-
- /* Configuring IDT for output refclks as
- * Refclk1 = 156.25MHz Refclk2 = 125MHz
- */
- if (refclk1 == SERDES_REFCLK_156_25 &&
- refclk2 == SERDES_REFCLK_125) {
- printf("Setting refclk1:156.25 and refclk2:125\n");
- for (i = 0; i < NUM_IDT_REGS_156_25; i++)
- i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
- idt_conf_156_25_125[i][1]);
- }
-
- /* waiting for maximum of 1 second if PLL doesn'r get locked
- * initially. then check the status again.
- */
- if (check_pll_status(idt_addr)) {
- mdelay(1000);
- if (check_pll_status(idt_addr))
- return -1;
- }
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Author: Shaveta Leekha <shaveta@freescale.com>
- */
-
-#ifndef __IDT8T49N222A_SERDES_CLK_H_
-#define __IDT8T49N222A_SERDES_CLK_H_ 1
-
-#include <common.h>
-#include <i2c.h>
-#include "qixis.h"
-#include "../b4860qds/b4860qds_qixis.h"
-#include <errno.h>
-
-#define NUM_IDT_REGS 23
-#define NUM_IDT_REGS_FEEDBACK 12
-#define NUM_IDT_REGS_156_25 11
-
-/* CLK */
-enum serdes_refclk {
- SERDES_REFCLK_100, /* refclk 100Mhz */
- SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
- SERDES_REFCLK_125, /* refclk 125Mhz */
- SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
- SERDES_REFCLK_NONE = -1,
-};
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
- */
-static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
- {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
- {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
- {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
- {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
- {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
- {0x16, 0xA0} };
-
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
- */
-static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
- {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
- {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
- {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
- {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
- {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
- {0x16, 0xA0} };
-
-/* Reconfiguration values for some of IDT registers for
- * Output Refclks:
- * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
- * and with feedback as 1
- */
-static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
- {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
- {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
- {0x14, 0x00}, {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
- */
-static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 100MHz Refclk2 : 156.25MHz
- */
-static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 125MHz Refclk2 : 156.25MHz
- */
-static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 156.25MHz Refclk2 : 100MHz
- */
-static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 156.25MHz Refclk2 : 125MHz
- */
-static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
- {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
- {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
- {0x15, 0xE8} };
-
-int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
- enum serdes_refclk refclk1,
- enum serdes_refclk refclk2, u8 feedback);
-
-#endif /*__IDT8T49N222A_SERDES_CLK_H_ */
projects / u-boot.git / commitdiff