# Temporary for false positive in checkpatch
--ignore COMPLEX_MACRO
-# For CONFIG_SYS_I2C_NOPROBES
+# For CFG_SYS_I2C_NOPROBES
--ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
# For simple_strtoul
default y if TFABOOT
help
Typically, we use an initial stack pointer address that is calculated
- by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
- statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
+ by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the
+ statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the
build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different
but statica calculation is performed. However, some platforms will
take a different approach. Say Y here to define the address statically
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
- It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
+ It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new
malloc() region in SDRAM once it is inited.
config TPL_SYS_MALLOC_F_LEN
$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
- @# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
+ @# CFG_SYS_TIMER_RATE has brackets in it for some boards which
@# confuses this rule. Use if() to send just a single character which
@# is enable to tell 'deprecated' that one of these symbols exists
- $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x))
+ $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
@# Check that this build does not use CONFIG options that we do not
# U-Boot entry point, needed for booting of full-blown U-Boot
# from the SPL U-Boot version.
#
-ifndef CONFIG_SYS_UBOOT_START
-CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
+ifndef CFG_SYS_UBOOT_START
+CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
endif
# Boards with more complex image requirements can provide an .its source file
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
else
MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
endif
UBOOT_BIN := u-boot.bin
MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot.bin.lzma: u-boot.bin FORCE
CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the
- same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
+ same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
- MIPS CPU options:
be swapped if a flash programmer is used.
- ARM options:
- CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+ CFG_SYS_EXCEPTION_VECTORS_HIGH
Select high exception vectors of the ARM core, e.g., do not
clear the V bit of the c1 register of CP15.
the defaults discussed just above.
- Cache Configuration for ARM:
- CONFIG_SYS_PL310_BASE - Physical base address of PL310
+ CFG_SYS_PL310_BASE - Physical base address of PL310
controller register space
- Serial Ports:
- GPIO Support:
CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
- The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
+ The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of
chip-ngpio pairs that tell the PCA953X driver the number of
pins supported by a particular chip.
CONFIG_SYS_I2C_DIRECT_BUS
define this, if you don't use i2c muxes on your hardware.
- if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
+ if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
omit this define.
- CONFIG_SYS_I2C_MAX_HOPS
+ CFG_SYS_I2C_MAX_HOPS
define how many muxes are maximal consecutively connected
on one i2c bus. If you not use i2c muxes, omit this
define.
- CONFIG_SYS_I2C_BUSES
+ CFG_SYS_I2C_BUSES
hold a list of buses you want to use, only used if
CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
- a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
+ a board with CFG_SYS_I2C_MAX_HOPS = 1 and
CFG_SYS_NUM_I2C_BUSES = 9:
- CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
+ CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
active. To switch to a different bus, use the 'i2c dev' command.
Note that bus numbering is zero-based.
- CONFIG_SYS_I2C_NOPROBES
+ CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS
e.g.
#undef CONFIG_I2C_MULTI_BUS
- #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
+ #define CFG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
#define CONFIG_I2C_MULTI_BUS
- #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
+ #define CFG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
- CONFIG_SYS_RTC_BUS_NUM
+ CFG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC.
If not defined, then U-Boot assumes that RTC is on I2C bus 0.
configuration if the INIT_B line goes low (which
indicated a CRC error).
- CONFIG_SYS_FPGA_WAIT_INIT
+ CFG_SYS_FPGA_WAIT_INIT
Maximum time to wait for the INIT_B line to de-assert
after PROB_B has been de-asserted during a Virtex II
FPGA configuration sequence. The default time is 500
ms.
- CONFIG_SYS_FPGA_WAIT_BUSY
+ CFG_SYS_FPGA_WAIT_BUSY
Maximum time to wait for BUSY to de-assert during
Virtex II FPGA configuration. The default is 5 ms.
- CONFIG_SYS_FPGA_WAIT_CONFIG
+ CFG_SYS_FPGA_WAIT_CONFIG
Time to wait after FPGA configuration. The default is
200 ms.
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
-- CONFIG_SYS_BAUDRATE_TABLE:
+- CFG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
-- CONFIG_SYS_MEM_RESERVE_SECURE
+- CFG_SYS_MEM_RESERVE_SECURE
Only implemented for ARMv8 for now.
- If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
+ If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
is substracted from total RAM and won't be reported to OS.
This memory can be used as secure memory. A variable
gd->arch.secure_ram is used to track the location. In systems
- CFG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
-- CONFIG_SYS_FLASH_BASE:
+- CFG_SYS_FLASH_BASE:
Physical start address of Flash memory.
- CONFIG_SYS_MALLOC_LEN:
boards which do not use the full malloc in SPL (which is
enabled with CONFIG_SYS_SPL_MALLOC).
-- CONFIG_SYS_BOOTMAPSZ:
+- CFG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
the Linux kernel (bd_info, boot arguments, FDT blob if
used) must be put below this limit, unless "bootm_low"
environment variable is defined and non-zero. In such case
all data for the Linux kernel must be between "bootm_low"
- and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment
+ and "bootm_low" + CFG_SYS_BOOTMAPSZ. The environment
variable "bootm_mapsize" will override the value of
- CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
+ CFG_SYS_BOOTMAPSZ. If CFG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
- CONFIG_SYS_BOOT_GET_CMDLINE:
Default (power-on reset) physical address of CCSR on Freescale
PowerPC SOCs.
-- CONFIG_SYS_CCSRBAR:
+- CFG_SYS_CCSRBAR:
Virtual address of CCSR. On a 32-bit build, this is typically
the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
-- CONFIG_SYS_CCSRBAR_PHYS:
+- CFG_SYS_CCSRBAR_PHYS:
Physical address of CCSR. CCSR can be relocated to a new
physical address, if desired. In this case, this macro should
be set to that address. Otherwise, it should be set to the
is typically relocated on 36-bit builds. It is recommended
that this macro be defined via the _HIGH and _LOW macros:
- #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
- * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
+ #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH
+ * 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
-- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
- Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically
+- CFG_SYS_CCSRBAR_PHYS_HIGH:
+ Bits 33-36 of CFG_SYS_CCSRBAR_PHYS. This value is typically
either 0 (32-bit build) or 0xF (36-bit build). This macro is
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
-- CONFIG_SYS_CCSRBAR_PHYS_LOW:
- Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is
+- CFG_SYS_CCSRBAR_PHYS_LOW:
+ Lower 32-bits of CFG_SYS_CCSRBAR_PHYS. This macro is
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only]
-- CONFIG_SYS_INIT_RAM_ADDR:
+- CFG_SYS_INIT_RAM_ADDR:
Start address of memory area that can be used for
initial data and stack; please note that this must be
cause you grief during the initial boot! It is frequently not
used.
- CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
+ CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value
you will find in any recent u-boot distribution in
walnut.h should work for you. I'd set it to a value larger
#include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
+#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE
#endif
/*
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
-#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
#else
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_HZ_CLOCK
+#ifndef CFG_SYS_HZ_CLOCK
static inline u32 read_cntfrq(void)
{
u32 frq;
gd->arch.tbl = 0;
gd->arch.tbu = 0;
-#ifdef CONFIG_SYS_HZ_CLOCK
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#ifdef CFG_SYS_HZ_CLOCK
+ gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else
gd->arch.timer_rate_hz = read_cntfrq();
#endif
int arch_cpu_init(void)
{
- void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
- (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
- CONFIG_SYS_IFC_ADDR);
+ CFG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
static void __secure ls1_fsm_setup(void)
{
- void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
static void __secure ls1_start_fsm(void)
{
- void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
{
ulong tmo;
ulong start = get_timer_masked();
- ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
+ ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;
* The number of reference clock ticks that correspond to 10ms is normally
* defined in the SysTick Calibration register's TENMS field. However, on some
* devices this is wrong, so this driver allows the clock rate to be defined
- * using CONFIG_SYS_HZ_CLOCK.
+ * using CFG_SYS_HZ_CLOCK.
*/
#include <common.h>
/*
* If the TENMS field is inexact or wrong, specify the clock rate using
- * CONFIG_SYS_HZ_CLOCK.
+ * CFG_SYS_HZ_CLOCK.
*/
-#if defined(CONFIG_SYS_HZ_CLOCK)
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#if defined(CFG_SYS_HZ_CLOCK)
+ gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else
gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
#endif
CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+ { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
CONFIG_SYS_FSL_IFC_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#ifdef CONFIG_FSL_IFC
- /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+ /* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+ CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
{}, /* space holder for secure mem */
#endif
{},
if (el == 3)
gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
else
- gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
+ gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
}
}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
if (el == 3) {
/*
gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
final_map[index].virt = gd->arch.secure_ram & ~0x3;
final_map[index].phys = final_map[index].virt;
- final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
+ final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
tlb_addr_save = gd->arch.tlb_addr;
ea_size = gd->ram_size;
}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
/* Check if we have enough space for secure memory */
- if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
- ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
+ ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
else
printf("Error: No enough space for secure memory.\n");
#endif
* gd->arch.secure_ram should be done to avoid running it repeatedly.
*/
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
debug("No need to run again, skip %s\n", __func__);
#endif
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
+ CFG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->bd->bi_dram[0].size >
- CONFIG_SYS_MEM_RESERVE_SECURE) {
+ CFG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[0].size -=
- CONFIG_SYS_MEM_RESERVE_SECURE;
+ CFG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
- gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
}
-#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
+#endif /* CFG_SYS_MEM_RESERVE_SECURE */
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
/* Assign memory for MC */
}
#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
debug("%s is called. gd->ram_size is reduced to %lu\n",
__func__, (ulong)gd->ram_size);
#endif
} else {
mmu_change_region_attr(
CFG_SYS_SDRAM_BASE,
- CONFIG_SYS_DDR_BLOCK1_SIZE,
+ CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
#endif
- if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
+ if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
CONFIG_SYS_DDR_BLOCK2_SIZE) {
mmu_change_region_attr(
- CONFIG_SYS_DDR_BLOCK2_BASE,
+ CFG_SYS_DDR_BLOCK2_BASE,
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK3_BASE,
gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE -
+ CFG_SYS_DDR_BLOCK1_SIZE -
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
#endif
{
mmu_change_region_attr(
- CONFIG_SYS_DDR_BLOCK2_BASE,
+ CFG_SYS_DDR_BLOCK2_BASE,
gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE,
+ CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
Environment Variables
=====================
mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
- the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+ the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value
- CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+ CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
from the location where it is stored(NOR, NAND, SD, SATA, USB)during
#include <fsl_sec.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
#include <asm/arch-fsl-layerscape/fsl_portals.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
porsr1 = in_be32(&gur->porsr1);
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
- out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+ out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1);
out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif
out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
| SCFG_RD_QOS1_PFE2_QOS));
- ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
- out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+ ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+ out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
ecccr2 | (unsigned int)DISABLE_PFE_ECC);
}
#endif
#endif
dram_init();
#ifdef CONFIG_SPL_FSL_LS_PPA
-#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifndef CFG_SYS_MEM_RESERVE_SECURE
#error Need secure RAM for PPA
#endif
/*
goto out;
}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
/*
* The SEC Firmware must be stored in secure memory.
* Append SEC Firmware to secure mmu table.
sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
gd->arch.tlb_size;
#else
-#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
+#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
#endif
/* Align SEC Firmware base address to 4K */
* Reserve secure memory
* To be aligned with MMU block size
*/
-#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
+#define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
-#define CONFIG_SYS_PAGE_SIZE 0x10000
+#define CFG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#elif defined(CONFIG_ARCH_LS1088A)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#define CONFIG_SYS_PAGE_SIZE 0x10000
+#define CFG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#endif
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
-#define CONFIG_SYS_PAGE_SIZE 0x10000
+#define CFG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SEC */
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 7
#define CFG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A)
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SMMU Defintions */
#define SMMU_BASE 0x09000000
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
- CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+ CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(compat, streamid) \
SET_SCFG_ICID(compat, streamid, sata_icid,\
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
- CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+ CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(sata_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
#include <linux/bitops.h>
#endif
-#define CONFIG_SYS_DCSRBAR 0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
+#define CFG_SYS_DCSRBAR 0x20000000
+#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
+#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
+#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
+#define CFG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
-#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
-#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
-
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
-#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
- CONFIG_SYS_BMAN_MEM_BASE)
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
+#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
+#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
+
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0x508000000
+#define CFG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
+ CFG_SYS_BMAN_MEM_BASE)
+#define CFG_SYS_BMAN_MEM_SIZE 0x08000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x10000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x10000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0x3E80
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0x500000000
+#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_SIZE 0x08000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x10000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0x3680
#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
#define TP_INIT_PER_CLUSTER 4
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR 0x01000000
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0x01000000
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW 0x01000000
#endif
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
- CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
+#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#endif
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
-#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
+#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
/* SFP */
-#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
+#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
#endif
/* Security Monitor */
-#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
+#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)
#define CFG_SYS_NS16550_CLK 13000000
#endif
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
/* NAND */
/* USB OHCI */
#if defined(CONFIG_USB_OHCI_LPC32XX)
-#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
+#define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE
#endif
#endif /* _LPC32XX_CONFIG_H */
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
-#define CONFIG_SYS_DCSRBAR 0x20000000
+#define CFG_SYS_DCSRBAR 0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
-#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
+#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000)
+#define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
+#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
-#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
-#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
+#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
+#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
-#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
-#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
-#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
+#define CFG_SYS_TSEC1_OFFSET 0x01d10000
+#define CFG_SYS_MDIO1_OFFSET 0x01d24000
-#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
#define DCFG_DCSR_PORCR1 0
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR CONFIG_SYS_IMMR
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf
#else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
#endif
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
- CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
{ .compat = name, \
.id = { idA }, .num_ids = 1, \
.reg_offset = off + CONFIG_SYS_IMMR, \
- .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
}
#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
{ .compat = name, \
.id = { idA, idB }, .num_ids = 2, \
.reg_offset = off + CONFIG_SYS_IMMR, \
- .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
}
/*
* Generic timer support
*/
#ifdef CONFIG_MX31_CLK32
-#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32
+#define CFG_SYS_TIMER_RATE CONFIG_MX31_CLK32
#else
-#define CONFIG_SYS_TIMER_RATE 32768
+#define CFG_SYS_TIMER_RATE 32768
#endif
#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
+#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif
#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
-#define CONFIG_SYS_TCLK 24000000
+#define CFG_SYS_TCLK 24000000
#endif
unsigned long tlb_emerg;
#endif
#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
#define MEM_RESERVE_SECURE_SECURED 0x1
#define MEM_RESERVE_SECURE_MAINTAINED 0x2
#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)
struct bd_info *bd = gd->bd;
bdinfo_print_num_l("arch_number", bd->bi_arch_number);
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
bdinfo_print_num_ll("Secure ram",
gd->arch.secure_ram &
#include <config.h>
#include <common.h>
-struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
static void pl310_cache_sync(void)
{
debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
/*
* Record allocated tlb_addr in case gd->tlb_addr to be overwritten
* with location within secure ram.
*/
_start:
-#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
- .word CONFIG_SYS_DV_NOR_BOOT_CFG
+#ifdef CFG_SYS_DV_NOR_BOOT_CFG
+ .word CFG_SYS_DV_NOR_BOOT_CFG
#endif
ARM_VECTORS
#endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */
{
switch (css) {
case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
+ return CFG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
{
unsigned freq, mckr;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+ main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
gd->arch.main_clk_rate_hz = main_clock;
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
}
.word AT91_ASM_MC_SMC_CSR0
.word CONFIG_SYS_SMC_CSR0_VAL
.word AT91_ASM_PMC_PLLAR
- .word CONFIG_SYS_PLLAR_VAL
+ .word CFG_SYS_PLLAR_VAL
.word AT91_ASM_PMC_PLLBR
.word CONFIG_SYS_PLLBR_VAL
.word AT91_ASM_PMC_MCKR
- .word CONFIG_SYS_MCKR_VAL
+ .word CFG_SYS_MCKR_VAL
SMRDATAE:
/* here there's a delay */
SMRDATA1:
.word AT91_ASM_PIOC_BSR
.word CONFIG_SYS_PIOC_BSR_VAL
.word AT91_ASM_PIOC_PDR
- .word CONFIG_SYS_PIOC_PDR_VAL
+ .word CFG_SYS_PIOC_PDR_VAL
.word AT91_ASM_MC_EBI_CSA
.word CONFIG_SYS_EBI_CSA_VAL
.word AT91_ASM_MC_SDRAMC_CR
- .word CONFIG_SYS_SDRC_CR_VAL
+ .word CFG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL
+ .word CFG_SYS_SDRC_MR_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL1
+ .word CFG_SYS_SDRC_MR_VAL1
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL2
+ .word CFG_SYS_SDRC_MR_VAL2
.word CFG_SYS_SDRAM1
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL
+ .word CFG_SYS_SDRC_TR_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL3
+ .word CFG_SYS_SDRC_MR_VAL3
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
SMRDATA1E:
DECLARE_GLOBAL_DATA_PTR;
/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
+#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
int timer_init(void)
{
u32 endtime;
signed long diff;
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+ tmo = CFG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= 1000;
{
switch (css) {
case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
+ return CFG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
{
unsigned freq, mckr;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+ main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
gd->arch.main_clk_rate_hz = main_clock;
#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
}
void arch_preboot_os(void)
#ifdef CONFIG_ATMEL_LEGACY
#include <asm/arch/at91sam9_matrix.h>
#endif
-#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
-#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
+#ifndef CFG_SYS_MATRIX_EBICSA_VAL
+#define CFG_SYS_MATRIX_EBICSA_VAL CFG_SYS_MATRIX_EBI0CSA_VAL
#endif
.globl lowlevel_init
ldr r1, =(AT91_ASM_PMC_MOR)
ldr r2, =(AT91_ASM_PMC_SR)
/* Main oscillator Enable register PMC_MOR: */
- ldr r0, =CONFIG_SYS_MOR_VAL
+ ldr r0, =CFG_SYS_MOR_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_ASM_PMC_PLLAR)
- ldr r0, =CONFIG_SYS_PLLAR_VAL
+ ldr r0, =CFG_SYS_PLLAR_VAL
str r0, [r1]
/* Reading the PMC Status register to detect when the PLLA is locked */
ldr r1, =(AT91_ASM_PMC_MCKR)
/* -Master Clock Controller register PMC_MCKR */
- ldr r0, =CONFIG_SYS_MCKR1_VAL
+ ldr r0, =CFG_SYS_MCKR1_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop
- ldr r0, =CONFIG_SYS_MCKR2_VAL
+ ldr r0, =CFG_SYS_MCKR2_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
SMRDATA:
.word AT91_ASM_WDT_MR
- .word CONFIG_SYS_WDTC_WDMR_VAL
+ .word CFG_SYS_WDTC_WDMR_VAL
/* configure PIOx as EBI0 D[16-31] */
#if defined(CONFIG_AT91SAM9263)
.word AT91_ASM_PIOD_PDR
- .word CONFIG_SYS_PIOD_PDR_VAL1
+ .word CFG_SYS_PIOD_PDR_VAL1
.word AT91_ASM_PIOD_PUDR
- .word CONFIG_SYS_PIOD_PPUDR_VAL
+ .word CFG_SYS_PIOD_PPUDR_VAL
.word AT91_ASM_PIOD_ASR
- .word CONFIG_SYS_PIOD_PPUDR_VAL
+ .word CFG_SYS_PIOD_PPUDR_VAL
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
|| defined(CONFIG_AT91SAM9G20)
.word AT91_ASM_PIOC_PDR
- .word CONFIG_SYS_PIOC_PDR_VAL1
+ .word CFG_SYS_PIOC_PDR_VAL1
.word AT91_ASM_PIOC_PUDR
- .word CONFIG_SYS_PIOC_PPUDR_VAL
+ .word CFG_SYS_PIOC_PPUDR_VAL
#endif
.word AT91_ASM_MATRIX_CSA0
- .word CONFIG_SYS_MATRIX_EBICSA_VAL
+ .word CFG_SYS_MATRIX_EBICSA_VAL
/* flash */
.word AT91_ASM_SMC_MODE0
- .word CONFIG_SYS_SMC0_MODE0_VAL
+ .word CFG_SYS_SMC0_MODE0_VAL
.word AT91_ASM_SMC_CYCLE0
- .word CONFIG_SYS_SMC0_CYCLE0_VAL
+ .word CFG_SYS_SMC0_CYCLE0_VAL
.word AT91_ASM_SMC_PULSE0
- .word CONFIG_SYS_SMC0_PULSE0_VAL
+ .word CFG_SYS_SMC0_PULSE0_VAL
.word AT91_ASM_SMC_SETUP0
- .word CONFIG_SYS_SMC0_SETUP0_VAL
+ .word CFG_SYS_SMC0_SETUP0_VAL
SMRDATA1:
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL1
+ .word CFG_SYS_SDRC_MR_VAL1
.word AT91_ASM_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL1
+ .word CFG_SYS_SDRC_TR_VAL1
.word AT91_ASM_SDRAMC_CR
- .word CONFIG_SYS_SDRC_CR_VAL
+ .word CFG_SYS_SDRC_CR_VAL
.word AT91_ASM_SDRAMC_MDR
- .word CONFIG_SYS_SDRC_MDR_VAL
+ .word CFG_SYS_SDRC_MDR_VAL
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL2
+ .word CFG_SYS_SDRC_MR_VAL2
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL1
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL3
+ .word CFG_SYS_SDRC_MR_VAL3
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL2
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL9
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL4
+ .word CFG_SYS_SDRC_MR_VAL4
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL10
.word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL5
+ .word CFG_SYS_SDRC_MR_VAL5
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL11
.word AT91_ASM_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL2
+ .word CFG_SYS_SDRC_TR_VAL2
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL12
/* User reset enable*/
.word AT91_ASM_RSTC_MR
- .word CONFIG_SYS_RSTC_RMR_VAL
+ .word CFG_SYS_RSTC_RMR_VAL
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
.word AT91_ASM_MATRIX_MCFG
{
switch (css) {
case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
+ return CFG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
{
unsigned freq, mckr;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+ main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
gd->arch.main_clk_rate_hz = main_clock;
clk_source = regval & AT91_PMC_PCR_GCKCSS;
switch (clk_source) {
case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
- freq = CONFIG_SYS_AT91_SLOW_CLOCK;
+ freq = CFG_SYS_AT91_SLOW_CLOCK;
break;
case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
freq = gd->arch.main_clk_rate_hz;
#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
#if defined(CONFIG_CLK_CCF)
return 0;
#else
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
#endif
}
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines
#endif
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffe3c
/*
* Other misc defines
#define ATMEL_CPU_NAME get_cpu_name()
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c
+#define CFG_SYS_TIMER_COUNTER 0xfffffe4c
/*
* Other misc defines
#define cpu_is_sama5d2 _cpu_is_sama5d2
/* PIT Timer(PIT_PIIR) */
-#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
+#define CFG_SYS_TIMER_COUNTER 0xf804803c
#ifndef __ASSEMBLY__
unsigned int get_chip_id(void);
#define CPU_HAS_PCR
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
+#define CFG_SYS_TIMER_COUNTER 0xfffffe3c
/*
* PMECC table in ROM
(get_extension_chip_id() == ARCH_EXID_SAMA5D44))
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
+#define CFG_SYS_TIMER_COUNTER 0xfc06863c
/*
* No PMECC Galois table in ROM
at91_pllicpr_init(0x00);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
- at91_plla_init(CONFIG_SYS_AT91_PLLA);
+ at91_plla_init(CFG_SYS_AT91_PLLA);
/* PCK = PLLA = 2 * MCK */
- at91_mck_init(CONFIG_SYS_MCKR);
+ at91_mck_init(CFG_SYS_MCKR);
/* Switch MCK on PLLA output */
- at91_mck_init(CONFIG_SYS_MCKR_CSS);
+ at91_mck_init(CFG_SYS_MCKR_CSS);
-#if defined(CONFIG_SYS_AT91_PLLB)
+#if defined(CFG_SYS_AT91_PLLB)
/* Configure PLLB */
- at91_pllb_init(CONFIG_SYS_AT91_PLLB);
+ at91_pllb_init(CFG_SYS_AT91_PLLB);
#endif
/* Enable External Reset */
/* Initialize matrix */
matrix_init();
- gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
+ gd->arch.mck_rate_hz = CFG_SYS_MASTER_CLOCK;
/*
* init timer long enough for using in spl.
*/
/* PMC configuration */
at91_pmc_init();
- at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
matrix_init();
int pll_out;
unsigned int pll_base;
- pll_out = CONFIG_SYS_OSCIN_FREQ;
+ pll_out = CFG_SYS_OSCIN_FREQ;
if (id == DAVINCI_AUXCLK_CLKID)
goto out;
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
}
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
- writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+ writel(CFG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
- if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+ if (CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
/* DDR2 */
clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
(1 << DDR_SLEW_DDR_PDENA_BIT) |
* At the same time, set the TIMUNLOCK bit to allow changing
* the timing registers
*/
- tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
+ tmp = CFG_SYS_DA850_DDR2_SDBCR;
tmp &= ~DV_DDR_BOOTUNLOCK;
tmp |= DV_DDR_TIMUNLOCK;
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/* write memory configuration and timing */
- if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+ if (!(CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
/* MOBILE DDR only*/
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+ writel(CFG_SYS_DA850_DDR2_SDBCR2,
&dv_ddr2_regs_ctrl->sdbcr2);
}
- writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
- writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+ writel(CFG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+ writel(CFG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
/* clear the TIMUNLOCK bit and write the value of the CL field */
tmp &= ~DV_DDR_TIMUNLOCK;
* LPMODEN and MCLKSTOPEN must be set!
* Without this bits set, PSC don;t switch states !!
*/
- writel(CONFIG_SYS_DA850_DDR2_SDRCR |
+ writel(CFG_SYS_DA850_DDR2_SDRCR |
(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
&dv_ddr2_regs_ctrl->sdrcr);
/* disable self refresh */
clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
- writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+ writel(CFG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
return 0;
}
writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
dv_maskbits(&davinci_syscfg_regs->suspsrc,
- CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
+ CFG_SYS_DA850_SYSCFG_SUSPSRC);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
#if defined(CONFIG_SYS_DA850_PLL_INIT)
/* PLL setup */
- da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
- da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
+ da850_pll_init(davinci_pllc0_regs, CFG_SYS_DA850_PLL0_PLLM);
+ da850_pll_init(davinci_pllc1_regs, CFG_SYS_DA850_PLL1_PLLM);
#endif
/* setup CSn config */
#if defined(CONFIG_SYS_DA850_CS2CFG)
DECLARE_GLOBAL_DATA_PTR;
static struct davinci_timer * const timer =
- (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
+ (struct davinci_timer *)CFG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL 0xffffffff
writel(0x0, &timer->tim34);
writel(TIMER_LOAD_VAL, &timer->prd34);
writel(2 << 22, &timer->tcr);
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+ gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV;
gd->arch.timer_reset_value = 0;
return(0);
{
int upto, todo;
int i, timeout = 100;
- struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
+ struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE;
set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
/* set the spi1 GPIO */
int end;
/* Calculate the image set end,
- * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000),
- * we use CONFIG_SYS_UBOOT_BASE
+ * if it is less than CFG_SYS_UBOOT_BASE(0x8281000),
+ * we use CFG_SYS_UBOOT_BASE
* Otherwise, use the calculated address
*/
end = get_imageset_end((void *)NULL, QSPI_NOR_DEV);
- if (end <= CONFIG_SYS_UBOOT_BASE)
- end = CONFIG_SYS_UBOOT_BASE;
+ if (end <= CFG_SYS_UBOOT_BASE)
+ end = CFG_SYS_UBOOT_BASE;
else
end = ROUND(end, SZ_1K);
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
setup_pll PLL3_BASE_ADDR, 216
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
- ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ ldr r1, =CFG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */
mov r10, lr
mov r4, #0 /* Fix R4 to 0 */
-#if defined(CONFIG_SYS_MAIN_PWR_ON)
+#if defined(CFG_SYS_MAIN_PWR_ON)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #1 << 23
$(call if_changed,mkfitimage)
MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
if (argc < 2)
return CMD_RET_USAGE;
- freq = CONFIG_SYS_HZ_CLOCK;
+ freq = CFG_SYS_HZ_CLOCK;
addr = hextoul(argv[1], NULL);
/* MSMC segment size shift bits */
#define KS2_MSMC_SEG_SIZE_SHIFT 12
#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
-#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \
+#define KS2_MSMC_DST_SEG_BASE (CFG_SYS_LPAE_SDRAM_BASE >> \
KS2_MSMC_SEG_SIZE_SHIFT)
/* Device speed */
/* Use common timer */
#ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
-#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
+#define CFG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
+#define CFG_SYS_TIMER_RATE CFG_SYS_TCLK
#endif
#endif /* _KW_CONFIG_H */
#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
/* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
+#define CFG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_KW88F6192_H */
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
/* TCLK Core Clock definition */
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \
+#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \
166666667 : 200000000)
#endif /* _ASM_ARCH_KW88F6281_H */
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
/* The L2 cache is already disabled at this point */
void v7_outer_cache_disable(void)
{
struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
-#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
+#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
#define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100))
#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
#define BOOT_FROM_UART 0x30
#define BOOT_FROM_SPI 0x38
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
+#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
200000000 : 166000000)
#elif defined(CONFIG_ARMADA_38X)
/* SAR values for Armada 38x */
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
-#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
+#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
200000000 : 250000000)
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
-#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+#define CFG_SYS_TCLK 200000000 /* 200MHz */
#elif defined(CONFIG_ARMADA_XP)
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+#define CFG_SYS_TCLK 250000000 /* 250MHz */
#endif
#endif /* _MVEBU_SOC_H */
* Disable L2 cache
*
* NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
- * but CONFIG_SYS_PL310_BASE is already calculated from base
+ * but CFG_SYS_PL310_BASE is already calculated from base
* address SOC_REGS_PHY_BASE.
*/
- ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
+ ldr r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
ldr r0, [r1, #L2X0_CTRL_OFF]
bic r0, #L2X0_CTRL_EN
str r0, [r1, #L2X0_CTRL_OFF]
void set_pl310_ctrl(u32 enable)
{
- struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
writel(enable, &pl310->pl310_ctrl);
}
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
- -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
#if defined(CONFIG_NOR)
case MTD_DEV_TYPE_NOR:
gpmc_regs = gpmc_regs_nor;
- base = CONFIG_SYS_FLASH_BASE;
- size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
- ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
- ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
- ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
+ base = CFG_SYS_FLASH_BASE;
+ size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
+ ((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+ ((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
+ ((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
GPMC_SIZE_16M)));
break;
#endif
#if defined(CONFIG_CMD_ONENAND)
case MTD_DEV_TYPE_ONENAND:
gpmc_regs = gpmc_regs_onenand;
- base = CONFIG_SYS_ONENAND_BASE;
+ base = CFG_SYS_ONENAND_BASE;
size = GPMC_SIZE_128M;
break;
#endif
DECLARE_GLOBAL_DATA_PTR;
-static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+static struct gptimer *timer_base = (struct gptimer *)CFG_SYS_TIMERBASE;
static ulong get_timer_masked(void);
/*
#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE
/* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
+#define CFG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_88F5182_H */
static inline ulong read_timer(void)
{
return readl(CNTMR_VAL_REG(UBOOT_CNTR))
- / (CONFIG_SYS_TCLK / 1000);
+ / (CFG_SYS_TCLK / 1000);
}
DECLARE_GLOBAL_DATA_PTR;
} else {
/* we have an overflow ... */
timestamp += lastdec +
- (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+ (TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now;
}
lastdec = now;
ulong delayticks;
current = uboot_cntr_val();
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+ delayticks = (usec * (CFG_SYS_TCLK / 1000000));
if (current < delayticks) {
delayticks -= current;
#define MSTP11_BITS 0x00000000
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 4
#define R8A7790_CUT_ES2X 2
#define IS_R8A7790_ES2() \
*/
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define MSTP11_BITS 0x00000008
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 1
#endif /* __ASM_ARCH_R8A7792_H */
*/
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define MSTP11_BITS 0x000001C0
/* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define R8A7794_CUT_ES2 2
#define IS_R8A7794_ES2() \
{
u64 timer = get_cpu_global_timer();
- timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
- do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
+ timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1));
+ do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK));
return timer;
}
u64 wait;
start = get_cpu_global_timer();
- wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
+ wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2);
do {
current = get_cpu_global_timer();
} while ((current - start) < wait);
ulong get_tbclk(void)
{
- return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
+ return (ulong)(CFG_SYS_CPU_CLK >> 2);
}
#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
#endif
struct bsel bsel_str[] = {
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
/* If we're still in OCRAM, don't set the XN bit on it */
if (!(gd->flags & GD_FLG_RELOC)) {
set_section_dcache(
- CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+ CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
DCACHE_WRITETHROUGH);
}
DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ (struct pl310_regs *)CFG_SYS_PL310_BASE;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =
DECLARE_GLOBAL_DATA_PTR;
#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
-#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+#define BOOTROM_SHARED_MEM_ADDR (CFG_SYS_INIT_RAM_ADDR + \
SOCFPGA_PHYS_OCRAM_SIZE - \
BOOTROM_SHARED_MEM_SIZE)
#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
#define TIMER_LOAD_VAL 0xFFFFFFFF
-static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+static const struct socfpga_timer *timer_base = (void *)CFG_SYS_TIMERBASE;
/*
* Timer initialization
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_disable(void)
{
- struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
/*
* Linux expects the L2 cache to be turned off by the bootloader.
#include "arm-mpcore.h"
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
-#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
+#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1)
static void *get_global_timer_base(void)
{
ulong tmr_ctrl_val;
/* 1st disable the Timer */
- tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+ tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~TIMER_ENABLE;
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+ *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/*
* The Timer Control Register has one Undefined/Shouldn't Use Bit
* Tmr Siz : 16 Bit Counter
* Tmr in Wrapping Mode
*/
- tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+ tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+ *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
return 0;
}
u32 wdog_module = 0;
/* set timeout and enable watchdog */
- wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module |= (wdog_module / 8192);
out_be16(&wdp->mr, wdog_module);
out_be16(&wdog->cr, 0);
#endif
- out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+ out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */
out_8(&gpio->par_cs, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+ out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
- out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
- out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
- out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
#endif
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#endif
icache_enable();
while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
;
- gd->bus_clk = CONFIG_SYS_CLK;
+ gd->bus_clk = CFG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_SYS_I2C_FSL
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
- cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
+ cpu_model, prn, strmhz(buf, CFG_SYS_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
- pin, prn, strmhz(buf, CONFIG_SYS_CLK));
+ pin, prn, strmhz(buf, CFG_SYS_CLK));
return 0;
}
char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
return 0;
};
#endif /* CONFIG_DISPLAY_CPUINFO */
char buf[32];
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
unsigned char resetsource = mbar_readLong(SIM_RSR);
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
printf("Reset:%s%s\n",
{
fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#else
#warning "Chip Select 0 are not initialized/used"
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
init_fbcs();
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG =
- CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG =
+ CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#ifdef CONFIG_SYS_I2C2_OFFSET
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+ sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR);
gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
- out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
+ out_be16(&sysctrl->sc_scr, CFG_SYS_SCR);
+ out_be16(&sysctrl->sc_spr, CFG_SYS_SPR);
/* Setup Ports: */
- out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
- out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
- out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
- out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
- out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
- out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
- out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
+ out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT);
+ out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR);
+ out_be16(&gpio->gpio_padat, CFG_SYS_PADAT);
+ out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT);
+ out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR);
+ out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT);
+ out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT);
/* Memory Controller: */
out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
- MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
- MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+ MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) |
+ MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
#ifdef CONFIG_SYS_PFPAR
MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
-#ifdef CONFIG_SYS_PJPAR
- MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
+#ifdef CFG_SYS_PJPAR
+ MCFGPIO_PJPAR = CFG_SYS_PJPAR;
#endif
#ifdef CONFIG_SYS_PSDPAR
MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
-#ifdef CONFIG_SYS_PASPAR
- MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
+#ifdef CFG_SYS_PASPAR
+ MCFGPIO_PASPAR = CFG_SYS_PASPAR;
#endif
-#ifdef CONFIG_SYS_PEHLPAR
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+#ifdef CFG_SYS_PEHLPAR
+ MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
#endif
#ifdef CONFIG_SYS_PQSPAR
MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
#ifdef CONFIG_SYS_PTDPAR
MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
-#ifdef CONFIG_SYS_PUAPAR
- MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
+#ifdef CFG_SYS_PUAPAR
+ MCFGPIO_PUAPAR = CFG_SYS_PUAPAR;
#endif
#if defined(CONFIG_SYS_DDRD)
MCFGPIO_DDRD = CONFIG_SYS_DDRD;
#endif
-#ifdef CONFIG_SYS_DDRUA
- MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
+#ifdef CFG_SYS_DDRUA
+ MCFGPIO_DDRUA = CFG_SYS_DDRUA;
#endif
/* FlexBus Chipselect */
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+ MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
- MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+ MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR;
}
return 0;
}
* which is their primary function.
* ~Jeremy
*/
- mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
- mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
- mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
- mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
- mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
- mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
+ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN);
+ mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN);
+ mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT);
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT);
/*
* dBug Compliance:
#if defined(CONFIG_M5208)
pll_t *pll = (pll_t *) MMAP_PLL;
- out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
- out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
+ out_8(&pll->odr, CFG_SYS_PLL_ODR);
+ out_8(&pll->fdr, CFG_SYS_PLL_FDR);
#endif
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
-#ifndef CONFIG_SYS_PLL_BYPASS
+#ifndef CFG_SYS_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
-#ifdef CONFIG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
- pllcr = CONFIG_SYS_PLLCR;
+ pllcr = CFG_SYS_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
+#endif /* #ifndef CFG_SYS_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
;
#endif
- gd->cpu_clk = CONFIG_SYS_CLK;
+ gd->cpu_clk = CFG_SYS_CLK;
#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
defined(CONFIG_M5271) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
*/
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long _start - CONFIG_TEXT_BASE
#else
.long _START
.text
-#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
+#if defined(CFG_SYS_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
#if defined(CONFIG_M5208)
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.c %d0, %MBAR
/*** The 5249 has MBAR2 as well ***/
-#ifdef CONFIG_SYS_MBAR2
+#ifdef CFG_SYS_MBAR2
/* Get MBAR2 address */
- move.l #(CONFIG_SYS_MBAR2 + 1), %d0
+ move.l #(CFG_SYS_MBAR2 + 1), %d0
/* Set MBAR2 */
movec %d0, #0xc0e
#endif
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* Initialize RAMBAR1: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#if defined(CONFIG_M5282)
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
/*
* Setup code in SRAM to initialize FLASHBAR,
* if start from internal Flash
*/
- move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
- move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
+ move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0
+ move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1
+ move.l #(CFG_SYS_INIT_RAM_ADDR), %a2
_copy_flash:
move.l (%a0)+, (%a2)+
cmp.l %a0, %a1
bgt.s _copy_flash
- jmp CONFIG_SYS_INIT_RAM_ADDR
+ jmp CFG_SYS_INIT_RAM_ADDR
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
- move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+ move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
- move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+ move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
-#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
+#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */
#endif
#endif
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
- move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
+ move.l #CFG_SYS_INT_FLASH_BASE, %d0
#else
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif
#ifdef CONFIG_M5275
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
char buf[32];
printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CPU_CLK));
+ strmhz(buf, CFG_SYS_CPU_CLK));
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
{
csm_t *csm = (csm_t *)(MMAP_CSM);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
- defined(CONFIG_SYS_CS0_CTRL))
- out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
- out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \
+ defined(CFG_SYS_CS0_CTRL))
+ out_be16(&csm->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&csm->csmr0, CFG_SYS_CS0_MASK);
+ out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0);
#else
#warning "Chip Select 0 are not initialized/used"
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
- defined(CONFIG_SYS_CS1_CTRL))
- out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
- out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \
+ defined(CFG_SYS_CS1_CTRL))
+ out_be16(&csm->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&csm->csmr1, CFG_SYS_CS1_MASK);
+ out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
- defined(CONFIG_SYS_CS2_CTRL))
- out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
- out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \
+ defined(CFG_SYS_CS2_CTRL))
+ out_be16(&csm->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&csm->csmr2, CFG_SYS_CS2_MASK);
+ out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
- defined(CONFIG_SYS_CS3_CTRL))
- out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
- out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \
+ defined(CFG_SYS_CS3_CTRL))
+ out_be16(&csm->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&csm->csmr3, CFG_SYS_CS3_MASK);
+ out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
defined(CONFIG_SYS_CS4_CTRL))
int get_clocks(void)
{
#if defined(CONFIG_M5307)
- gd->bus_clk = CONFIG_SYS_CLK;
- gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+ gd->bus_clk = CFG_SYS_CLK;
+ gd->cpu_clk = CFG_SYS_CPU_CLK;
#endif
return 0;
/* Flash offset is 0 until we setup CS0 */
.long 0x00000000
#if defined(CONFIG_M5307) && \
- (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+ (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long _start - CONFIG_TEXT_BASE
#else
.long _START
move.w #0x2700,%sr
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.c %d0, %MBAR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0
move.c %d0, %RAMBAR
/* DS 4.8.2 (Cache Organization) invalidate and disable cache */
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
#endif
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
u32 wdog_module = 0;
/* set timeout and enable watchdog */
- wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
#ifdef CONFIG_M5329
out_be16(&wdp->mr, wdog_module / 8192);
#else
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
- out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
- out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
+ out_be32(&rtcex->gocu, CFG_SYS_RTC_CNT);
+ out_be32(&rtcex->gocl, CFG_SYS_RTC_SETUP);
#endif
#ifdef CONFIG_MCFFEC
/* Port configuration */
out_8(&gpio->par_cs, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
/* Latch chipselect */
setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
clrbits_8(&gpio->par_feci2c, 0x00ff);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
-#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
+#elif defined(CFG_SYS_UART2_ALT3_GPIO)
clrbits_be16(&gpio->par_ssi, 0x0f00);
setbits_be16(&gpio->par_ssi,
GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
- gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
+ gd->bus_clk = clock_pll(CFG_SYS_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
#ifdef CONFIG_SYS_I2C_FSL
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
/* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
#endif
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
#if !defined(CONFIG_SERIAL_BOOT)
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
/* Latch chipselect */
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
/* FlexBus Chipselect */
init_fbcs();
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
* also move to the new location.
*/
- if (CONFIG_SYS_CS0_BASE != 0)
- setvbr(CONFIG_SYS_CS0_BASE);
+ if (CFG_SYS_CS0_BASE != 0)
+ setvbr(CFG_SYS_CS0_BASE);
#endif
icache_enable();
#if defined(CONFIG_SERIAL_BOOT)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_TEXT_BASE + \
- CONFIG_SYS_INIT_RAM_ADDR)
+ CFG_SYS_INIT_RAM_ADDR)
#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_TEXT_BASE)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_TEXT_BASE + \
- CONFIG_SYS_INIT_RAM_ADDR)
+ CFG_SYS_INIT_RAM_ADDR)
#endif
.text
#ifdef CONFIG_SYS_NAND_BOOT
/* for assembly stack */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
#endif
#ifdef CONFIG_CF_SBF
- move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
+ move.l #CFG_SYS_INIT_RAM_ADDR, %d0
movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
move.l %d0, (%a2)
/* invalidate and disable cache */
- move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+ move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR2
movec %d0, %ACR3
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
/* Must disable global address */
move.l #0xFC008000, %a1
- move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #(CFG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
- move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #(CFG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
- move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+ move.l #(CFG_SYS_CS0_MASK), (%a1)
#endif
#endif /* CONFIG_CF_SBF */
move.l (%a1)+, %d5
move.l (%a1), %a4
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
- move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0
+ move.l #(CFG_SYS_SBFHDR_SIZE), %d4
move.l #0xFC05C02C, %a1 /* dspi status */
movec %d0, %ACR2
movec %d0, %ACR3
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
/* Must disable global address */
move.l #0xFC008000, %a1
- move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #(CFG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
- move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #(CFG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
- move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+ move.l #(CFG_SYS_CS0_MASK), (%a1)
#endif
/* NAND port configuration */
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
move.l %d0, (%a2)
/* invalidate and disable cache */
- move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+ move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR2
movec %d0, %ACR3
#else
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
#endif /* CONFIG_CF_V4 */
-#ifndef CONFIG_SYS_CACHE_ICACR
-#define CONFIG_SYS_CACHE_ICACR 0
+#ifndef CFG_SYS_CACHE_ICACR
+#define CFG_SYS_CACHE_ICACR 0
#endif
-#ifndef CONFIG_SYS_CACHE_DCACR
-#ifdef CONFIG_SYS_CACHE_ICACR
-#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR
+#ifndef CFG_SYS_CACHE_DCACR
+#ifdef CFG_SYS_CACHE_ICACR
+#define CFG_SYS_CACHE_DCACR CFG_SYS_CACHE_ICACR
#else
-#define CONFIG_SYS_CACHE_DCACR 0
+#define CFG_SYS_CACHE_DCACR 0
#endif
#endif
-#ifndef CONFIG_SYS_CACHE_ACR0
-#define CONFIG_SYS_CACHE_ACR0 0
+#ifndef CFG_SYS_CACHE_ACR0
+#define CFG_SYS_CACHE_ACR0 0
#endif
-#ifndef CONFIG_SYS_CACHE_ACR1
-#define CONFIG_SYS_CACHE_ACR1 0
+#ifndef CFG_SYS_CACHE_ACR1
+#define CFG_SYS_CACHE_ACR1 0
#endif
-#ifndef CONFIG_SYS_CACHE_ACR2
-#define CONFIG_SYS_CACHE_ACR2 0
+#ifndef CFG_SYS_CACHE_ACR2
+#define CFG_SYS_CACHE_ACR2 0
#endif
#ifndef CONFIG_SYS_CACHE_ACR3
#include <asm/m520x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
#include <asm/m5235.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
#include <asm/immap_5249.h>
#include <asm/m5249.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
#include <asm/m5249.h>
#include <asm/m5253.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
#include <asm/m5271.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
#include <asm/m5272.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (192)
#include <asm/m5282.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#include <asm/m5307.h>
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
- (CONFIG_SYS_UART_PORT * 0x40))
+ (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
#include <asm/m5329.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-#if (CONFIG_SYS_UART_PORT < 4)
+#if (CFG_SYS_UART_PORT < 4)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
- (CONFIG_SYS_UART_PORT * 0x4000))
+ (CFG_SYS_UART_PORT * 0x4000))
#else
#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
- ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+ ((CFG_SYS_UART_PORT - 4) * 0x4000))
#endif
#define MMAP_DSPI MMAP_DSPI0
#define FEC1_TX_INIT 31
#endif
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
#ifdef CONFIG_SLTTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
#ifdef CONFIG_PCI
#define CFG_SYS_PCI_BAR0 (0x40000000)
#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
-#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
+#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR)
#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M547x */
#ifndef __IMMAP_520X__
#define __IMMAP_520X__
-#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
-#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
-#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000)
+#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000)
+#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000)
+#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000)
+#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00088000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x0008C000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00090000)
+#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000A8000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
#ifndef __IMMAP_5235__
#define __IMMAP_5235__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
+#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400)
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/qspi.h>
#ifndef __IMMAP_5253__
#define __IMMAP_5253__
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000)
-#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000)
+#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_I2C0 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_CAN0 (CFG_SYS_MBAR + 0x00010000)
+#define MMAP_CAN1 (CFG_SYS_MBAR + 0x00011000)
-#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C)
-#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440)
-#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00)
+#define MMAP_PAR (CFG_SYS_MBAR2 + 0x0000019C)
+#define MMAP_I2C1 (CFG_SYS_MBAR2 + 0x00000440)
+#define MMAP_UART2 (CFG_SYS_MBAR2 + 0x00000C00)
#include <asm/coldfire/ata.h>
#include <asm/coldfire/flexbus.h>
#ifndef __IMMAP_5271__
#define __IMMAP_5271__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
+#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#ifndef __IMMAP_5272__
#define __IMMAP_5272__
-#define MMAP_CFG (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000020)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x000000A0)
-#define MMAP_PWM (CONFIG_SYS_MBAR + 0x000000C0)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x000000E0)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_TMR0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_TMR1 (CONFIG_SYS_MBAR + 0x00000220)
-#define MMAP_TMR2 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_TMR3 (CONFIG_SYS_MBAR + 0x00000260)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_PLIC (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840)
-#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_CFG (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC (CFG_SYS_MBAR + 0x00000020)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x000000A0)
+#define MMAP_PWM (CFG_SYS_MBAR + 0x000000C0)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x000000E0)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_TMR0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_TMR1 (CFG_SYS_MBAR + 0x00000220)
+#define MMAP_TMR2 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_TMR3 (CFG_SYS_MBAR + 0x00000260)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_PLIC (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_FEC (CFG_SYS_MBAR + 0x00000840)
+#define MMAP_USB (CFG_SYS_MBAR + 0x00001000)
#include <asm/coldfire/pwm.h>
#ifndef __IMMAP_5275__
#define __IMMAP_5275__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800)
-#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FEC0FIFO (CFG_SYS_MBAR + 0x00001400)
+#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00001800)
+#define MMAP_FEC1FIFO (CFG_SYS_MBAR + 0x00001C00)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000)
+#define MMAP_RCM (CFG_SYS_MBAR + 0x00110000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x00110004)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_USB (CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_PWM0 (CFG_SYS_MBAR + 0x001D0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000)
+#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAMC (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_DMA3 (CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000)
+#define MMAP_QADC (CFG_SYS_MBAR + 0x00190000)
+#define MMAP_GPTMRA (CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_GPTMRB (CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN (CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_CFMC (CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CFMMEM (CFG_SYS_MBAR + 0x04000000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#ifndef __IMMAP_5301X__
#define __IMMAP_5301X__
-#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000)
-#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
-#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000)
-#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
-#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000)
-#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000)
-#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000)
-#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000)
-#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000)
-#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000)
-#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
-#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
-#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000)
-#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000)
-#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000)
+#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000)
+#define MMAP_MPU (CFG_SYS_MBAR + 0x00014000)
+#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000)
+#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00034000)
+#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x0004C000)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000)
+#define MMAP_DSPI (CFG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00088000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x0008C000)
+#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00090000)
+#define MMAP_EPORT1 (CFG_SYS_MBAR + 0x00094000)
+#define MMAP_VOICOD (CFG_SYS_MBAR + 0x0009C000)
+#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000)
+#define MMAP_RTC (CFG_SYS_MBAR + 0x000A8000)
+#define MMAP_SIM (CFG_SYS_MBAR + 0x000AC000)
+#define MMAP_USBOTG (CFG_SYS_MBAR + 0x000B0000)
+#define MMAP_USBH (CFG_SYS_MBAR + 0x000B4000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000B8000)
+#define MMAP_SSI (CFG_SYS_MBAR + 0x000BC000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x000C0000)
+#define MMAP_RNG (CFG_SYS_MBAR + 0x000C4000)
+#define MMAP_IIM (CFG_SYS_MBAR + 0x000C8000)
+#define MMAP_ESDHC (CFG_SYS_MBAR + 0x000CC000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#ifndef __IMMAP_5307__
#define __IMMAP_5307__
-#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244)
+#define MMAP_SIM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DRAMC (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000244)
typedef struct sim {
u8 rsr;
/*
* useful definitions for reading/writing MBAR offset memory
*/
-#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
-#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x))
-#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y
-#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y
-#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y
+#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x))
+#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
+#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x))
+#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y
+#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR2 + x)) = y
+#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR2 + x)) = y
/*
* Size of internal RAM
#ifndef _MCF5271_H_
#define _MCF5271_H_
-#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
-#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
-#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
-#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x))
+#define mbar_readShort(x) *((volatile unsigned short *) (CFG_SYS_MBAR + x))
+#define mbar_readByte(x) *((volatile unsigned char *) (CFG_SYS_MBAR + x))
+#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
#define MCF_FMPLL_SYNCR 0x120000
#define MCF_FMPLL_SYNSR 0x120004
/* General Purpose I/O Module GPIO */
-#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000))
-#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001))
-#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002))
-#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003))
-#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004))
-#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005))
-#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006))
-#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007))
-#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008))
-#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009))
-#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A))
-#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B))
-#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C))
-#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D))
-#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E))
-#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F))
-#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010))
-#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011))
-
-#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014))
-#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015))
-#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016))
-#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017))
-#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018))
-#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019))
-#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A))
-#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B))
-#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C))
-#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D))
-#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E))
-#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F))
-#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020))
-#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021))
-#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022))
-#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023))
-#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024))
-#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025))
-
-#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
-#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
-#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
-#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
-#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
-#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
-#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
-#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
-#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
-#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
-#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
-#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
-#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
-#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
-#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
-#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
-#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
-#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
-
-#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
-#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
-#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
-#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
-#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
-#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
-#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
-#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
-#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
-#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
-#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
-#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
-#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
-#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
-#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
-#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
-#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
-#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
-
-#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C))
-#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D))
-#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E))
-#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F))
-#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040))
-#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041))
-#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042))
-#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043))
-#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044))
-#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045))
-#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046))
-#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047))
-#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048))
-#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049))
-#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A))
-#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B))
-#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C))
-#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D))
-
-#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050))
-#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051))
-#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052))
-#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054))
-#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055))
-#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056))
-#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058))
-#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059))
-#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A))
-#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B))
-#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C))
+#define MCFGPIO_PORTA (*(vu_char *) (CFG_SYS_MBAR+0x100000))
+#define MCFGPIO_PORTB (*(vu_char *) (CFG_SYS_MBAR+0x100001))
+#define MCFGPIO_PORTC (*(vu_char *) (CFG_SYS_MBAR+0x100002))
+#define MCFGPIO_PORTD (*(vu_char *) (CFG_SYS_MBAR+0x100003))
+#define MCFGPIO_PORTE (*(vu_char *) (CFG_SYS_MBAR+0x100004))
+#define MCFGPIO_PORTF (*(vu_char *) (CFG_SYS_MBAR+0x100005))
+#define MCFGPIO_PORTG (*(vu_char *) (CFG_SYS_MBAR+0x100006))
+#define MCFGPIO_PORTH (*(vu_char *) (CFG_SYS_MBAR+0x100007))
+#define MCFGPIO_PORTJ (*(vu_char *) (CFG_SYS_MBAR+0x100008))
+#define MCFGPIO_PORTDD (*(vu_char *) (CFG_SYS_MBAR+0x100009))
+#define MCFGPIO_PORTEH (*(vu_char *) (CFG_SYS_MBAR+0x10000A))
+#define MCFGPIO_PORTEL (*(vu_char *) (CFG_SYS_MBAR+0x10000B))
+#define MCFGPIO_PORTAS (*(vu_char *) (CFG_SYS_MBAR+0x10000C))
+#define MCFGPIO_PORTQS (*(vu_char *) (CFG_SYS_MBAR+0x10000D))
+#define MCFGPIO_PORTSD (*(vu_char *) (CFG_SYS_MBAR+0x10000E))
+#define MCFGPIO_PORTTC (*(vu_char *) (CFG_SYS_MBAR+0x10000F))
+#define MCFGPIO_PORTTD (*(vu_char *) (CFG_SYS_MBAR+0x100010))
+#define MCFGPIO_PORTUA (*(vu_char *) (CFG_SYS_MBAR+0x100011))
+
+#define MCFGPIO_DDRA (*(vu_char *) (CFG_SYS_MBAR+0x100014))
+#define MCFGPIO_DDRB (*(vu_char *) (CFG_SYS_MBAR+0x100015))
+#define MCFGPIO_DDRC (*(vu_char *) (CFG_SYS_MBAR+0x100016))
+#define MCFGPIO_DDRD (*(vu_char *) (CFG_SYS_MBAR+0x100017))
+#define MCFGPIO_DDRE (*(vu_char *) (CFG_SYS_MBAR+0x100018))
+#define MCFGPIO_DDRF (*(vu_char *) (CFG_SYS_MBAR+0x100019))
+#define MCFGPIO_DDRG (*(vu_char *) (CFG_SYS_MBAR+0x10001A))
+#define MCFGPIO_DDRH (*(vu_char *) (CFG_SYS_MBAR+0x10001B))
+#define MCFGPIO_DDRJ (*(vu_char *) (CFG_SYS_MBAR+0x10001C))
+#define MCFGPIO_DDRDD (*(vu_char *) (CFG_SYS_MBAR+0x10001D))
+#define MCFGPIO_DDREH (*(vu_char *) (CFG_SYS_MBAR+0x10001E))
+#define MCFGPIO_DDREL (*(vu_char *) (CFG_SYS_MBAR+0x10001F))
+#define MCFGPIO_DDRAS (*(vu_char *) (CFG_SYS_MBAR+0x100020))
+#define MCFGPIO_DDRQS (*(vu_char *) (CFG_SYS_MBAR+0x100021))
+#define MCFGPIO_DDRSD (*(vu_char *) (CFG_SYS_MBAR+0x100022))
+#define MCFGPIO_DDRTC (*(vu_char *) (CFG_SYS_MBAR+0x100023))
+#define MCFGPIO_DDRTD (*(vu_char *) (CFG_SYS_MBAR+0x100024))
+#define MCFGPIO_DDRUA (*(vu_char *) (CFG_SYS_MBAR+0x100025))
+
+#define MCFGPIO_PORTAP (*(vu_char *) (CFG_SYS_MBAR+0x100028))
+#define MCFGPIO_PORTBP (*(vu_char *) (CFG_SYS_MBAR+0x100029))
+#define MCFGPIO_PORTCP (*(vu_char *) (CFG_SYS_MBAR+0x10002A))
+#define MCFGPIO_PORTDP (*(vu_char *) (CFG_SYS_MBAR+0x10002B))
+#define MCFGPIO_PORTEP (*(vu_char *) (CFG_SYS_MBAR+0x10002C))
+#define MCFGPIO_PORTFP (*(vu_char *) (CFG_SYS_MBAR+0x10002D))
+#define MCFGPIO_PORTGP (*(vu_char *) (CFG_SYS_MBAR+0x10002E))
+#define MCFGPIO_PORTHP (*(vu_char *) (CFG_SYS_MBAR+0x10002F))
+#define MCFGPIO_PORTJP (*(vu_char *) (CFG_SYS_MBAR+0x100030))
+#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_SYS_MBAR+0x100031))
+#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_SYS_MBAR+0x100032))
+#define MCFGPIO_PORTELP (*(vu_char *) (CFG_SYS_MBAR+0x100033))
+#define MCFGPIO_PORTASP (*(vu_char *) (CFG_SYS_MBAR+0x100034))
+#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_SYS_MBAR+0x100035))
+#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_SYS_MBAR+0x100036))
+#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_SYS_MBAR+0x100037))
+#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_SYS_MBAR+0x100038))
+#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_SYS_MBAR+0x100039))
+
+#define MCFGPIO_SETA (*(vu_char *) (CFG_SYS_MBAR+0x100028))
+#define MCFGPIO_SETB (*(vu_char *) (CFG_SYS_MBAR+0x100029))
+#define MCFGPIO_SETC (*(vu_char *) (CFG_SYS_MBAR+0x10002A))
+#define MCFGPIO_SETD (*(vu_char *) (CFG_SYS_MBAR+0x10002B))
+#define MCFGPIO_SETE (*(vu_char *) (CFG_SYS_MBAR+0x10002C))
+#define MCFGPIO_SETF (*(vu_char *) (CFG_SYS_MBAR+0x10002D))
+#define MCFGPIO_SETG (*(vu_char *) (CFG_SYS_MBAR+0x10002E))
+#define MCFGPIO_SETH (*(vu_char *) (CFG_SYS_MBAR+0x10002F))
+#define MCFGPIO_SETJ (*(vu_char *) (CFG_SYS_MBAR+0x100030))
+#define MCFGPIO_SETDD (*(vu_char *) (CFG_SYS_MBAR+0x100031))
+#define MCFGPIO_SETEH (*(vu_char *) (CFG_SYS_MBAR+0x100032))
+#define MCFGPIO_SETEL (*(vu_char *) (CFG_SYS_MBAR+0x100033))
+#define MCFGPIO_SETAS (*(vu_char *) (CFG_SYS_MBAR+0x100034))
+#define MCFGPIO_SETQS (*(vu_char *) (CFG_SYS_MBAR+0x100035))
+#define MCFGPIO_SETSD (*(vu_char *) (CFG_SYS_MBAR+0x100036))
+#define MCFGPIO_SETTC (*(vu_char *) (CFG_SYS_MBAR+0x100037))
+#define MCFGPIO_SETTD (*(vu_char *) (CFG_SYS_MBAR+0x100038))
+#define MCFGPIO_SETUA (*(vu_char *) (CFG_SYS_MBAR+0x100039))
+
+#define MCFGPIO_CLRA (*(vu_char *) (CFG_SYS_MBAR+0x10003C))
+#define MCFGPIO_CLRB (*(vu_char *) (CFG_SYS_MBAR+0x10003D))
+#define MCFGPIO_CLRC (*(vu_char *) (CFG_SYS_MBAR+0x10003E))
+#define MCFGPIO_CLRD (*(vu_char *) (CFG_SYS_MBAR+0x10003F))
+#define MCFGPIO_CLRE (*(vu_char *) (CFG_SYS_MBAR+0x100040))
+#define MCFGPIO_CLRF (*(vu_char *) (CFG_SYS_MBAR+0x100041))
+#define MCFGPIO_CLRG (*(vu_char *) (CFG_SYS_MBAR+0x100042))
+#define MCFGPIO_CLRH (*(vu_char *) (CFG_SYS_MBAR+0x100043))
+#define MCFGPIO_CLRJ (*(vu_char *) (CFG_SYS_MBAR+0x100044))
+#define MCFGPIO_CLRDD (*(vu_char *) (CFG_SYS_MBAR+0x100045))
+#define MCFGPIO_CLREH (*(vu_char *) (CFG_SYS_MBAR+0x100046))
+#define MCFGPIO_CLREL (*(vu_char *) (CFG_SYS_MBAR+0x100047))
+#define MCFGPIO_CLRAS (*(vu_char *) (CFG_SYS_MBAR+0x100048))
+#define MCFGPIO_CLRQS (*(vu_char *) (CFG_SYS_MBAR+0x100049))
+#define MCFGPIO_CLRSD (*(vu_char *) (CFG_SYS_MBAR+0x10004A))
+#define MCFGPIO_CLRTC (*(vu_char *) (CFG_SYS_MBAR+0x10004B))
+#define MCFGPIO_CLRTD (*(vu_char *) (CFG_SYS_MBAR+0x10004C))
+#define MCFGPIO_CLRUA (*(vu_char *) (CFG_SYS_MBAR+0x10004D))
+
+#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100050))
+#define MCFGPIO_PFPAR (*(vu_char *) (CFG_SYS_MBAR+0x100051))
+#define MCFGPIO_PEPAR (*(vu_short *)(CFG_SYS_MBAR+0x100052))
+#define MCFGPIO_PJPAR (*(vu_char *) (CFG_SYS_MBAR+0x100054))
+#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100055))
+#define MCFGPIO_PASPAR (*(vu_short *)(CFG_SYS_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_SYS_MBAR+0x100058))
+#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_SYS_MBAR+0x100059))
+#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005C))
/* Bit level definitions and macros */
#define MCFGPIO_PORT7 (0x80)
/* System Conrol Module SCM */
-#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008))
-#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010))
-#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011))
-#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012))
-#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013))
-
-#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C))
-#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020))
-#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024))
-#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025))
-#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026))
-#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027))
-#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028))
-#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A))
-#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B))
-#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C))
-#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E))
-#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030))
-#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031))
+#define MCFSCM_RAMBAR (*(vu_long *) (CFG_SYS_MBAR+0x00000008))
+#define MCFSCM_CRSR (*(vu_char *) (CFG_SYS_MBAR+0x00000010))
+#define MCFSCM_CWCR (*(vu_char *) (CFG_SYS_MBAR+0x00000011))
+#define MCFSCM_LPICR (*(vu_char *) (CFG_SYS_MBAR+0x00000012))
+#define MCFSCM_CWSR (*(vu_char *) (CFG_SYS_MBAR+0x00000013))
+
+#define MCFSCM_MPARK (*(vu_long *) (CFG_SYS_MBAR+0x0000001C))
+#define MCFSCM_MPR (*(vu_char *) (CFG_SYS_MBAR+0x00000020))
+#define MCFSCM_PACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000024))
+#define MCFSCM_PACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000025))
+#define MCFSCM_PACR2 (*(vu_char *) (CFG_SYS_MBAR+0x00000026))
+#define MCFSCM_PACR3 (*(vu_char *) (CFG_SYS_MBAR+0x00000027))
+#define MCFSCM_PACR4 (*(vu_char *) (CFG_SYS_MBAR+0x00000028))
+#define MCFSCM_PACR5 (*(vu_char *) (CFG_SYS_MBAR+0x0000002A))
+#define MCFSCM_PACR6 (*(vu_char *) (CFG_SYS_MBAR+0x0000002B))
+#define MCFSCM_PACR7 (*(vu_char *) (CFG_SYS_MBAR+0x0000002C))
+#define MCFSCM_PACR8 (*(vu_char *) (CFG_SYS_MBAR+0x0000002E))
+#define MCFSCM_GPACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000030))
+#define MCFSCM_GPACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000031))
#define MCFSCM_CRSR_EXT (0x80)
#define MCFSCM_CRSR_CWDR (0x20)
/* Reset Controller Module RCM */
-#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000))
-#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001))
+#define MCFRESET_RCR (*(vu_char *) (CFG_SYS_MBAR+0x00110000))
+#define MCFRESET_RSR (*(vu_char *) (CFG_SYS_MBAR+0x00110001))
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
/* Chip Configuration Module CCM */
-#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004))
-#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008))
-#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A))
+#define MCFCCM_CCR (*(vu_short *)(CFG_SYS_MBAR+0x00110004))
+#define MCFCCM_RCON (*(vu_short *)(CFG_SYS_MBAR+0x00110008))
+#define MCFCCM_CIR (*(vu_short *)(CFG_SYS_MBAR+0x0011000A))
/* Bit level definitions and macros */
#define MCFCCM_CCR_LOAD (0x8000)
/* Clock Module */
-#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000))
-#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002))
+#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_SYS_MBAR+0x120000))
+#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_SYS_MBAR+0x120002))
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
#define MCFCLOCK_SYNSR_LOCK 0x08
-#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040))
-#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048))
-#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c))
-#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050))
-#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054))
+#define MCFSDRAMC_DCR (*(vu_short *)(CFG_SYS_MBAR+0x00000040))
+#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_SYS_MBAR+0x00000048))
+#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_SYS_MBAR+0x0000004c))
+#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000050))
+#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000054))
#define MCFSDRAMC_DCR_NAM (0x2000)
#define MCFSDRAMC_DCR_COC (0x1000)
#define MCFSDRAMC_DMR_UD (0x00000002)
#define MCFSDRAMC_DMR_V (0x00000001)
-#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000))
-#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002))
-#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
-#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
+#define MCFWTM_WCR (*(vu_short *)(CFG_SYS_MBAR+0x00140000))
+#define MCFWTM_WMR (*(vu_short *)(CFG_SYS_MBAR+0x00140002))
+#define MCFWTM_WCNTR (*(vu_short *)(CFG_SYS_MBAR+0x00140004))
+#define MCFWTM_WSR (*(vu_short *)(CFG_SYS_MBAR+0x00140006))
/*********************************************************************
* General Purpose Timer (GPT) Module
*********************************************************************/
-#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000))
-#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001))
-#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002))
-#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003))
-#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004))
-#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006))
-#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008))
-#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009))
-#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B))
-#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C))
-#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D))
-#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E))
-#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F))
-#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010))
-#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012))
-#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014))
-#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016))
-#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018))
-#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019))
-#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A))
-#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D))
-#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E))
-
-#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000))
-#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001))
-#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002))
-#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003))
-#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004))
-#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006))
-#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008))
-#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009))
-#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B))
-#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C))
-#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D))
-#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E))
-#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F))
-#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010))
-#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012))
-#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014))
-#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016))
-#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018))
-#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019))
-#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A))
-#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D))
-#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E))
+#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1A0000))
+#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1A0001))
+#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1A0002))
+#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1A0003))
+#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1A0004))
+#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0006))
+#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1A0008))
+#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0009))
+#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000B))
+#define MCFGPTA_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1A000C))
+#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000D))
+#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1A000E))
+#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000F))
+#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1A0010))
+#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1A0012))
+#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1A0014))
+#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1A0016))
+#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1A0018))
+#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1A0019))
+#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1A001A))
+#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1A001D))
+#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1A001E))
+
+#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1B0000))
+#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1B0001))
+#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1B0002))
+#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1B0003))
+#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1B0004))
+#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0006))
+#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1B0008))
+#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0009))
+#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000B))
+#define MCFGPTB_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1B000C))
+#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000D))
+#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1B000E))
+#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000F))
+#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1B0010))
+#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1B0012))
+#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1B0014))
+#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1B0016))
+#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1B0018))
+#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1B0019))
+#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1B001A))
+#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1B001D))
+#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1B001E))
/* Bit level definitions and macros */
#define MCFGPT_GPTIOS_IOS3 (0x08)
/* Coldfire Flash Module CFM */
-#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000))
+#define MCFCFM_MCR (*(vu_short *)(CFG_SYS_MBAR+0x1D0000))
#define MCFCFM_MCR_LOCK (0x0400)
#define MCFCFM_MCR_PVIE (0x0200)
#define MCFCFM_MCR_AEIE (0x0100)
#define MCFCFM_MCR_CCIE (0x0040)
#define MCFCFM_MCR_KEYACC (0x0020)
-#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002))
+#define MCFCFM_CLKD (*(vu_char *)(CFG_SYS_MBAR+0x1D0002))
-#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008))
+#define MCFCFM_SEC (*(vu_long*) (CFG_SYS_MBAR+0x1D0008))
#define MCFCFM_SEC_KEYEN (0x80000000)
#define MCFCFM_SEC_SECSTAT (0x40000000)
-#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010))
-#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014))
-#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018))
-#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020))
+#define MCFCFM_PROT (*(vu_long*) (CFG_SYS_MBAR+0x1D0010))
+#define MCFCFM_SACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0014))
+#define MCFCFM_DACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0018))
+#define MCFCFM_USTAT (*(vu_char*) (CFG_SYS_MBAR+0x1D0020))
#define MCFCFM_USTAT_CBEIF 0x80
#define MCFCFM_USTAT_CCIF 0x40
#define MCFCFM_USTAT_PVIOL 0x20
#define MCFCFM_USTAT_ACCERR 0x10
#define MCFCFM_USTAT_BLANK 0x04
-#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024))
+#define MCFCFM_CMD (*(vu_char*) (CFG_SYS_MBAR+0x1D0024))
#define MCFCFM_CMD_ERSVER 0x05
#define MCFCFM_CMD_PGERSVER 0x06
#define MCFCFM_CMD_PGM 0x20
{
struct bd_info *bd = gd->bd;
- bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
+ bd->bi_mbar_base = CFG_SYS_MBAR; /* base of internal registers */
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
struct bd_info *bd = gd->bd;
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
-#if defined(CONFIG_SYS_MBAR)
+#if defined(CFG_SYS_MBAR)
bdinfo_print_num_l("mbar", bd->bi_mbar_base);
#endif
bdinfo_print_mhz("cpufreq", bd->bi_intfreq);
*cf_icache_status = 1;
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
- __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
+ __asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2));
__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
#if defined(CONFIG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
#endif
#else
- __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
- __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+ __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
+ __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
#endif
- __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
+ __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_ICACR));
}
void icache_disable(void)
{
u32 temp;
- temp = CONFIG_SYS_ICACHE_INV;
+ temp = CFG_SYS_ICACHE_INV;
if (*cf_icache_status)
- temp |= CONFIG_SYS_CACHE_ICACR;
+ temp |= CFG_SYS_CACHE_ICACR;
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
}
*cf_dcache_status = 1;
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
- __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
- __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+ __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
+ __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
#if defined(CONFIG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
#endif
#endif
- __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
+ __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_DCACR));
}
void dcache_disable(void)
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
u32 temp;
- temp = CONFIG_SYS_DCACHE_INV;
+ temp = CFG_SYS_DCACHE_INV;
if (*cf_dcache_status)
- temp |= CONFIG_SYS_CACHE_DCACR;
+ temp |= CFG_SYS_CACHE_DCACR;
if (*cf_icache_status)
- temp |= CONFIG_SYS_CACHE_ICACR;
+ temp |= CFG_SYS_CACHE_ICACR;
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
#endif
#ifndef CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_SP_OFFSET)
+ CFG_SYS_INIT_SP_OFFSET)
#endif
#define SP_ADDR_TEMP 0xbe10dff0
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
SCCR_TSECCM |
#endif
-#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
SCCR_TSEC1CM |
#endif
-#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
SCCR_TSEC2CM |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
SCCR_USBMPHCM |
#endif
-#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
SCCR_USBDRCM |
#endif
-#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
SCCR_SATACM |
#endif
0;
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
#endif
-#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
- (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+ (CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
#endif
-#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
- (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+ (CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
#endif
-#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
- (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+ (CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
#endif
-#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
- (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
+ (CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
#endif
0;
setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
/* System General Purpose Register */
-#ifdef CONFIG_SYS_SICRH
+#ifdef CFG_SYS_SICRH
#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
- __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
+ __raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH,
&im->sysconf.sicrh);
#else
- __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
+ __raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh);
#endif
#endif
-#ifdef CONFIG_SYS_SICRL
- __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
+#ifdef CFG_SYS_SICRL
+ __raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl);
#endif
-#ifdef CONFIG_SYS_GPR1
- __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#ifdef CFG_SYS_GPR1
+ __raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1);
#endif
-#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
- __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
+#ifdef CFG_SYS_DDRCDR /* DDR control driver register */
+ __raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
-#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
- __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
+#ifdef CFG_SYS_OBIR /* Output buffer impedance register */
+ __raw_writel(CFG_SYS_OBIR, &im->sysconf.obir);
#endif
#if !defined(CONFIG_PINCTRL)
printf(", %s MHz)", strmhz(buf, gd->mem_clk));
-#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
+#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE)
puts("\nSDRAM: ");
- print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+ print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
#endif
}
return 0;
}
-#ifdef CONFIG_SYS_DDRCDR_VALUE
+#ifdef CFG_SYS_DDRCDR_VALUE
/*
* Adjust DDR II IO voltage biasing. It just makes it work.
*/
if(spd.mem_type == SPD_MEMTYPE_DDR2) {
- immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+ immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
}
udelay(50000);
#endif
ddr->sdram_mode =
(0
| (1 << (16 + 10)) /* DQS Differential disable */
-#ifdef CONFIG_SYS_DDR_MODE_WEAK
+#ifdef CFG_SYS_DDR_MODE_WEAK
| (1 << (16 + 1)) /* weak driver (~60%) */
#endif
| (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
}
-#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
+ ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
#endif
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
im->sysconf.spcr |= SPCR_TBEN;
/* DDR control driver register */
-#ifdef CONFIG_SYS_DDRCDR
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
+#ifdef CFG_SYS_DDRCDR
+ im->sysconf.ddrcdr = CFG_SYS_DDRCDR;
#endif
/* Output buffer impedance register */
-#ifdef CONFIG_SYS_OBIR
- im->sysconf.obir = CONFIG_SYS_OBIR;
+#ifdef CFG_SYS_OBIR
+ im->sysconf.obir = CFG_SYS_OBIR;
#endif
/*
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
#if defined(CONFIG_WATCHDOG)
/* Initialise the Watchdog values and reset it (if req) */
/*------------------------------------------------------*/
- lis r4, CONFIG_SYS_WATCHDOG_VALUE
+ lis r4, CFG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
stw r4, SWCRR(r3)
lock_ram_in_cache:
/* Allocate Initial RAM in data cache.
*/
- lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
- (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
+ (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
dcbz r0, r3
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
- (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
+ (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3
dcbi r0, r3
* LBIU Local Access Widow 0 will not cover this memory space. So, we
* need another window to map in it.
*/
- lis r4, (CONFIG_SYS_FLASH_BASE)@h
- ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
- stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
+ lis r4, (CFG_SYS_FLASH_BASE)@h
+ ori r4, r4, (CFG_SYS_FLASH_BASE)@l
+ stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_SYS_FLASH_BASE */
- /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
+ /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR1 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
- li r5, CONFIG_SYS_FLASH_SIZE
+ li r5, CFG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b
lwz r4, BR0(r3)
li r5, 0x7FFF
and r4, r4, r5
- lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
- ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
+ lis r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@h
+ ori r5, r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@l
or r5, r5, r4
- stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
+ stw r5, BR0(r3) /* r5 <= (CFG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
lwz r4, OR0(r3)
- lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
+ lis r5, ~((CFG_SYS_FLASH_SIZE << 4) - 1)
or r4, r4, r5
stw r4, OR0(r3)
- lis r4, (CONFIG_SYS_FLASH_BASE)@h
- ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
- stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
+ lis r4, (CFG_SYS_FLASH_BASE)@h
+ ori r4, r4, (CFG_SYS_FLASH_BASE)@l
+ stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_SYS_FLASH_BASE */
- /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
+ /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR0 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
- li r5, CONFIG_SYS_FLASH_SIZE
+ li r5, CFG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b
#ifdef CONFIG_ARCH_MPC8308
-#ifndef CONFIG_SYS_SICRL
-#define CONFIG_SYS_SICRL (\
+#ifndef CFG_SYS_SICRL
+#define CFG_SYS_SICRL (\
CONFIG_SICRL_SPI |\
CONFIG_SICRL_UART |\
CONFIG_SICRL_IRQ |\
)
#endif
-#ifndef CONFIG_SYS_SICRH
-#define CONFIG_SYS_SICRH (\
+#ifndef CFG_SYS_SICRH
+#define CFG_SYS_SICRH (\
CONFIG_SICRH_ESDHC_A |\
CONFIG_SICRH_ESDHC_B |\
CONFIG_SICRH_ESDHC_C |\
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),
*/
static void check_erratum_a4849(uint32_t svr)
{
- void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
+ void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000;
unsigned int i;
#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
*/
static void check_erratum_a007212(void)
{
- u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
+ u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
if (in_be32(plldgdcr) & 0x1fe) {
/* check if PLL ratio is set by workaround */
/* Common ddr init for non-corenet fsl 85xx platforms */
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
- !defined(CONFIG_SYS_INIT_L2_ADDR)
+ !defined(CFG_SYS_INIT_L2_ADDR)
int dram_init(void)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
#endif /* CONFIG_SYS_RAMBOOT */
#endif
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+#if CONFIG_POST & CFG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
/* invalid the TLBs for DDR and setup new ones to cover p_addr */
static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
{
- u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
unsigned long epn;
u32 tsize, valid, ptr;
int ddr_esel;
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
#if !defined(CONFIG_PHYS_64BIT) || \
- !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
- (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
+ (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
test_cap = p_size;
#else
test_cap = gd->ram_size;
p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
if (reset_tlb(p_addr, p_size, phys_offset) == -1)
return -1;
- *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ *vstart = CFG_SYS_DDR_SDRAM_BASE;
*size = (u32) p_size;
printf("Testing 0x%08llx - 0x%08llx\n",
(u64)(*vstart) + (*phys_offset),
{
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
- *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ *vstart = CFG_SYS_DDR_SDRAM_BASE;
*size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
*phys_offset = 0;
#if !defined(CONFIG_PHYS_64BIT) || \
- !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
- (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
+ (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
puts("Cannot test more than ");
print_size(CONFIG_MAX_MEM_MAPPED,
for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
- struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
+ struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR);
if (law.index == -1) {
printf("\nFatal error happened\n");
{
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_pll_ratio;
- u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
- u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
- u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
+ u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
+ u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28);
+ u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80);
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
- u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
- u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
+ u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40);
+ u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48);
#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
- u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
- u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
+ u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60);
+ u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68);
#endif
#endif
/*
ulong cpu_init_f(void)
{
extern void m8560_cpm_reset (void);
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
/* Disable the LAW created for NOR flash by the PBI commands */
- law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
+ law = find_law(CFG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
disable_law(law.index);
/* Invalidate the CPC before DDR gets enabled */
invalidate_cpc();
- #ifdef CONFIG_SYS_DCSRBAR_PHYS
+ #ifdef CFG_SYS_DCSRBAR_PHYS
/* set DCSRCR so that DCSR space is 1G */
setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
in_be32(&gur->dcsrcr);
asm("msync;isync");
cache_ctl = l2cache->l2ctl;
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR)
if (cache_ctl & MPC85xx_L2CTL_L2E) {
/* Clear L2 SRAM memory-mapped base address */
out_be32(&l2cache->l2srbar0, 0x0);
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
puts("already enabled");
-#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
+#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE)
u32 l2srbar = l2cache->l2srbar0;
if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
- && l2srbar >= CONFIG_SYS_FLASH_BASE) {
- l2srbar = CONFIG_SYS_INIT_L2_ADDR;
+ && l2srbar >= CFG_SYS_FLASH_BASE) {
+ l2srbar = CFG_SYS_INIT_L2_ADDR;
l2cache->l2srbar0 = l2srbar;
- printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
+ printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR);
}
-#endif /* CONFIG_SYS_INIT_L2_ADDR */
+#endif /* CFG_SYS_INIT_L2_ADDR */
puts("\n");
} else {
asm("msync;isync");
#endif
/* enable the cache */
- mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
+ mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0);
- if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
+ if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
;
print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
int cpu_init_r(void)
{
__maybe_unused u32 svr = get_svr();
-#ifdef CONFIG_SYS_LBC_LCRR
+#ifdef CFG_SYS_LBC_LCRR
fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) {
int i;
- __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
+ __be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c;
for (i = 0; i < 12; i++) {
p += i + (i > 5 ? 11 : 0);
out_be32(p, 0x2);
}
- p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
+ p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108;
out_be32(p, 0x34);
}
#endif
{
if (SVR_MAJ(svr) < 3) {
void *p;
- p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+ p = (void *)CFG_SYS_DCSRBAR + 0x20520;
setbits_be32(p, 1 << (31 - 14));
}
}
#endif
-#ifdef CONFIG_SYS_LBC_LCRR
+#ifdef CFG_SYS_LBC_LCRR
/*
* Modify the CLKDIV field of LCRR register to improve the writing
* speed for NOR flash.
*/
- clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
+ clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR);
__raw_readl(&lbc->lcrr);
isync();
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
*/
if (IS_SVR_REV(get_svr(), 1, 0)) {
struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
- (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
+ (CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET);
setbits_be32(&dcfg->ecccr1,
(DCSR_DCFG_ECC_DISABLE_USB1 |
DCSR_DCFG_ECC_DISABLE_USB2));
#ifdef CONFIG_A003399_NOR_WORKAROUND
void setup_ifc(void)
{
- struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ struct fsl_ifc ifc_regs = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
u32 _mas0, _mas1, _mas2, _mas3, _mas7;
- phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
+ phys_addr_t flash_phys = CFG_SYS_FLASH_BASE_PHYS;
/*
* Adjust the TLB we were running out of to match the phys addr of the
* chip select we are adjusting and will return to.
*/
- flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
+ flash_phys += (~CFG_SYS_AMASK0) + 1 - 4*1024*1024;
_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's physical address is going to change as
- * CONFIG_SYS_FLASH_BASE_PHYS.
+ * CFG_SYS_FLASH_BASE_PHYS.
*/
_mas0 = MAS0_TLBSEL(1) |
MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
#endif
/* Change flash's physical address */
- ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
- ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
- ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+ ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CFG_SYS_CSPR0);
+ ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CFG_SYS_CSOR0);
+ ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CFG_SYS_AMASK0);
return;
}
#ifdef CONFIG_ARCH_QEMU_E500
/*
- * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
+ * CFG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
*/
gd->fdt_blob = fdt;
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
- mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
- mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
- mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
+ mas2 = FSL_BOOKE_MAS2(CFG_SYS_CCSRBAR, MAS2_I|MAS2_G);
+ mas3 = FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
+ mas7 = FSL_BOOKE_MAS7(CFG_SYS_CCSRBAR_PHYS);
write_tlb(mas0, mas1, mas2, mas3, mas7);
}
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_SPL_MMC_BOOT
- off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
- CONFIG_SYS_MMC_U_BOOT_SIZE);
+ off = fdt_add_mem_rsv(blob, CFG_SYS_MMC_U_BOOT_START,
+ CFG_SYS_MMC_U_BOOT_SIZE);
if (off < 0)
printf("Failed to reserve memory for SD deep sleep: %s\n",
fdt_strerror(off));
#elif defined(CONFIG_SPL_SPI_BOOT)
- off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
- CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
+ off = fdt_add_mem_rsv(blob, CFG_SYS_SPI_FLASH_U_BOOT_START,
+ CFG_SYS_SPI_FLASH_U_BOOT_SIZE);
if (off < 0)
printf("Failed to reserve memory for SPI deep sleep: %s\n",
fdt_strerror(off));
static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
unsigned long freq)
{
- phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
+ phys_addr_t phys = offset + CFG_SYS_CCSRBAR_PHYS;
int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
if (off >= 0) {
ft_fixup_dpaa_clks(blob);
-#if defined(CONFIG_SYS_BMAN_MEM_PHYS)
+#if defined(CFG_SYS_BMAN_MEM_PHYS)
fdt_portal(blob, "fsl,bman-portal", "bman-portals",
- (u64)CONFIG_SYS_BMAN_MEM_PHYS,
- CONFIG_SYS_BMAN_MEM_SIZE);
+ (u64)CFG_SYS_BMAN_MEM_PHYS,
+ CFG_SYS_BMAN_MEM_SIZE);
fdt_fixup_bportals(blob);
#endif
-#if defined(CONFIG_SYS_QMAN_MEM_PHYS)
+#if defined(CFG_SYS_QMAN_MEM_PHYS)
fdt_portal(blob, "fsl,qman-portal", "qman-portals",
- (u64)CONFIG_SYS_QMAN_MEM_PHYS,
- CONFIG_SYS_QMAN_MEM_SIZE);
+ (u64)CFG_SYS_QMAN_MEM_PHYS,
+ CFG_SYS_QMAN_MEM_SIZE);
fdt_fixup_qportals(blob);
#endif
* beginning of CCSR.
*/
#define CCSR_VIRT_TO_PHYS(x) \
- (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
+ (CFG_SYS_CCSRBAR_PHYS + ((x) - CFG_SYS_CCSRBAR))
static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
{
return 0;
}
- if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
- msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
+ if (addr != CFG_SYS_CCSRBAR_PHYS) {
+ msg("CCSR", CFG_SYS_CCSRBAR_PHYS, addr);
/* No point in checking anything else */
return 0;
}
* the 'reg' property to be wrong, so check it here. For now, we
* only check for "fsl,elbc" nodes.
*/
-#ifdef CONFIG_SYS_LBC_ADDR
+#ifdef CFG_SYS_LBC_ADDR
off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
if (off > 0) {
const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
if (reg) {
- uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
+ uint64_t uaddr = CCSR_VIRT_TO_PHYS(CFG_SYS_LBC_ADDR);
addr = fdt_translate_address(fdt, off, reg);
if (uaddr != addr) {
memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
struct ccsr_sfp_regs __iomem *sfp_regs =
- (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+ (struct ccsr_sfp_regs __iomem *)(CFG_SYS_SFP_ADDR);
u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
u32 bc_status, fc_status, dc_status, pll_sr2;
serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
}
#endif
-#ifndef CONFIG_SYS_DCSRBAR_PHYS
-#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
-#define CONFIG_SYS_DCSRBAR 0x80000000
+#ifndef CFG_SYS_DCSRBAR_PHYS
+#define CFG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
+#define CFG_SYS_DCSRBAR 0x80000000
#define __DCSR_NOT_DEFINED_BY_CONFIG
#endif
*/
{
#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
- struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
+ struct law_entry law = find_law(CFG_SYS_DCSRBAR_PHYS);
int law_index;
if (law.index == -1)
- law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
+ law_index = set_next_law(CFG_SYS_DCSRBAR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
else
- set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
+ set_law(law.index, CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
LAW_TRGT_IF_DCSR);
#endif
- u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
+ u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114;
out_be32(p, rcw5);
#ifdef __DCSR_NOT_DEFINED_BY_CONFIG
if (law.index == -1)
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO( 1, 2, 1, 0),
SET_QP_INFO( 3, 4, 2, 1),
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
mtspr SPRN_L2CSR1,r3
#endif
- lis r3,CONFIG_SYS_INIT_L2CSR0@h
- ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
+ lis r3,CFG_SYS_INIT_L2CSR0@h
+ ori r3,r3,CFG_SYS_INIT_L2CSR0@l
mtspr SPRN_L2CSR0,r3
isync
2:
#ifndef CONFIG_PME_PLAT_CLK_DIV
switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
case 1:
- sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
+ sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK];
break;
case 2:
- sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
+ sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 2;
break;
case 3:
- sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
+ sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 3;
break;
case 4:
- sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
+ sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 4;
break;
case 6:
- sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
+ sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 2;
break;
case 7:
- sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
+ sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 3;
break;
default:
printf("Error: Unknown PME clock select!\n");
}
#else
- sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
+ sys_info->freq_pme = sys_info->freq_systembus / CFG_SYS_PME_CLK;
#endif
#endif
#ifndef CONFIG_FM_PLAT_CLK_DIV
switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
case 1:
- sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
+ sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK];
break;
case 2:
- sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
+ sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 2;
break;
case 3:
- sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
+ sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 3;
break;
case 4:
- sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
+ sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 4;
break;
case 5:
sys_info->freq_fman[0] = sys_info->freq_systembus;
break;
case 6:
- sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
+ sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 2;
break;
case 7:
- sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
+ sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 3;
break;
default:
printf("Error: Unknown FMan1 clock select!\n");
break;
}
#if (CFG_SYS_NUM_FMAN) == 2
-#ifdef CONFIG_SYS_FM2_CLK
+#ifdef CFG_SYS_FM2_CLK
#define FM2_CLK_SEL 0x00000038
#define FM2_CLK_SHIFT 3
rcw_tmp = in_be32(&gur->rcwsr[15]);
switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
case 1:
- sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
+ sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1];
break;
case 2:
- sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
+ sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 2;
break;
case 3:
- sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
+ sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 3;
break;
case 4:
- sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
+ sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 4;
break;
case 5:
sys_info->freq_fman[1] = sys_info->freq_systembus;
break;
case 6:
- sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
+ sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 2;
break;
case 7:
- sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
+ sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 3;
break;
default:
printf("Error: Unknown FMan2 clock select!\n");
#endif
#endif /* CFG_SYS_NUM_FMAN == 2 */
#else
- sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
+ sys_info->freq_fman[0] = sys_info->freq_systembus / CFG_SYS_FM1_CLK;
#endif
#endif
ulong cpu_init_f(void)
{
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
- out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
+ out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR);
/* set MBECCDIS=1, SBECCDIS=1 */
out_be32(&l2cache->l2errdis,
.Lconf_pair_start:
.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
- .long CONFIG_SYS_INIT_L2_ADDR
+ .long CFG_SYS_INIT_L2_ADDR
.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
mtspr SPRN_BUCSR,r0
#endif
-#if defined(CONFIG_SYS_INIT_DBCR)
+#if defined(CFG_SYS_INIT_DBCR)
lis r1,0xffff
ori r1,r1,0xffff
mtspr DBSR,r1 /* Clear all status bits */
- lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
- ori r0,r0,CONFIG_SYS_INIT_DBCR@l
+ lis r0,CFG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
+ ori r0,r0,CFG_SYS_INIT_DBCR@l
mtspr DBCR0,r0
#endif
* As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
* long-term TLBs, so we use TLB0 here.
*/
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS)
-#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
-#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
+#if !defined(CFG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CFG_SYS_CCSRBAR_PHYS_LOW)
+#error "CFG_SYS_CCSRBAR_PHYS_HIGH and CFG_SYS_CCSRBAR_PHYS_LOW) must be defined."
#endif
create_ccsr_new_tlb:
/*
* Create a TLB for the new location of CCSR. Register R8 is reserved
- * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
+ * for the virtual address of this TLB (CFG_SYS_CCSRBAR).
*/
- lis r8, CONFIG_SYS_CCSRBAR@h
- ori r8, r8, CONFIG_SYS_CCSRBAR@l
- lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
- ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
+ lis r8, CFG_SYS_CCSRBAR@h
+ ori r8, r8, CFG_SYS_CCSRBAR@l
+ lis r9, (CFG_SYS_CCSRBAR + 0x1000)@h
+ ori r9, r9, (CFG_SYS_CCSRBAR + 0x1000)@l
create_tlb0_entry 0, \
0, BOOKE_PAGESZ_4K, \
- CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
- CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
- CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+ CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
+ CFG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
+ CFG_SYS_CCSRBAR_PHYS_HIGH, r3
/*
* Create a TLB for the current location of CCSR. Register R9 is reserved
- * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
+ * for the virtual address of this TLB (CFG_SYS_CCSRBAR + 0x1000).
*/
create_ccsr_old_tlb:
create_tlb0_entry 1, \
0, BOOKE_PAGESZ_4K, \
- CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
+ CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
0, r3 /* The default CCSR address is always a 32-bit number */
#ifdef CONFIG_FSL_CORENET
-#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
+#define CCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_4K 0xb
#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
#define CCSRAR_C 0x80000000 /* Commit */
* On CoreNet systems, we create the temporary LAW using a special LAW
* target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
*/
- lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
- ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
- lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
- ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+ lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h
+ ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l
+ lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h
+ ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l
lis r2, CCSRBAR_LAWAR@h
ori r2, r2, CCSRBAR_LAWAR@l
* instruction.
*/
write_new_ccsrbar:
- lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
- ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
- lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
- ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+ lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h
+ ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l
+ lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h
+ ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l
lis r2, CCSRAR_C@h
ori r2, r2, CCSRAR_C@l
lwz r0, 0(r9)
isync
-/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
-#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
- (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
+/* CFG_SYS_CCSRBAR_PHYS right shifted by 12 */
+#define CCSRBAR_PHYS_RS12 ((CFG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
+ (CFG_SYS_CCSRBAR_PHYS_LOW >> 12))
/* Write the new value to CCSRBAR. */
lis r0, CCSRBAR_PHYS_RS12@h
/* Delete the temporary TLBs */
delete_temp_tlbs:
- delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
- delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
+ delete_tlb0_entry 0, CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
+ delete_tlb0_entry 1, CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
-#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
+#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) */
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
create_ccsr_l2_tlb:
*/
create_tlb0_entry 0, \
0, BOOKE_PAGESZ_4K, \
- CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
- CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
- CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+ CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
+ CFG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
+ CFG_SYS_CCSRBAR_PHYS_HIGH, r3
enable_l2_cluster_l2:
/* enable L2 cache */
- lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
- ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
+ lis r3, (CFG_SYS_CCSRBAR + 0xC20000)@h
+ ori r3, r3, (CFG_SYS_CCSRBAR + 0xC20000)@l
li r4, 33 /* stash id */
stw r4, 4(r3)
lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
beq 1b
delete_ccsr_l2_tlb:
- delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
+ delete_tlb0_entry 0, CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
#endif
/*
andi. r1,r3,L1CSR0_DCE@l
beq 2b
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
-#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
+#define DCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_1M 0x13
#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
rlwimi r0, r8, 16, MAS0_ESEL_MSK
lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
- lis r7, CONFIG_SYS_CCSRBAR@h
- ori r7, r7, CONFIG_SYS_CCSRBAR@l
+ lis r7, CFG_SYS_CCSRBAR@h
+ ori r7, r7, CFG_SYS_CCSRBAR@l
ori r2, r7, MAS2_I|MAS2_G
- lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
- ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
- lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
- ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+ lis r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
+ ori r3, r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
+ lis r4, CFG_SYS_CCSRBAR_PHYS_HIGH@h
+ ori r4, r4, CFG_SYS_CCSRBAR_PHYS_HIGH@l
mtspr MAS0, r0
mtspr MAS1, r1
mtspr MAS2, r2
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
- CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CFG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
/*
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
- CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#else
#endif
/* create a temp mapping in AS=1 to the stack */
-#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
- defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
+#if defined(CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
+ defined(CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
create_tlb1_entry 14, \
1, BOOKE_PAGESZ_16K, \
- CONFIG_SYS_INIT_RAM_ADDR, 0, \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
+ CFG_SYS_INIT_RAM_ADDR, 0, \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
#else
create_tlb1_entry 14, \
1, BOOKE_PAGESZ_16K, \
- CONFIG_SYS_INIT_RAM_ADDR, 0, \
- CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CFG_SYS_INIT_RAM_ADDR, 0, \
+ CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#endif
/* Allocate Initial RAM in data cache.
*/
- lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
- ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+ lis r3,CFG_SYS_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l
mfspr r2, L1CFG0
andi. r2, r2, 0x1ff
/* cache size * 1024 / (2 * L1 line size) */
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
- lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
- ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+ lis r3,(CFG_SYS_INIT_RAM_ADDR)@h
+ ori r3,r3,((CFG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
#endif
/* End of RAM */
- lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
- ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+ lis r4,(CFG_SYS_INIT_RAM_ADDR)@h
+ ori r4,r4,(CFG_SYS_INIT_RAM_SIZE)@l
li r0,0
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
- ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
+ lis r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
+ ori r3,r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
mfspr r4,L1CFG0
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
sync
/* Invalidate the TLB entries for the cache */
- lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
- ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+ lis r3,CFG_SYS_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l
tlbivax 0,r3
addi r3,r3,0x1000
tlbivax 0,r3
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),
unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
unsigned int memsize_in_meg)
{
- unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+ unsigned int ram_tlb_address = (unsigned int)CFG_SYS_DDR_SDRAM_BASE;
u64 memsize = (u64)memsize_in_meg << 20;
u64 size;
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
return
- setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+ setup_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}
/* Invalidate the DDR TLBs for the requested size */
void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
- u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
unsigned long epn;
u32 tsize, valid, ptr;
phys_addr_t rpn = 0;
void clear_ddr_tlbs(unsigned int memsize_in_meg)
{
- clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+ clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}
_end = .;
#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
-#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS)
mmc_u_boot_offs = .;
#endif
#endif
.resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
-#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS)
mmc_u_boot_offs = .;
#endif
#endif
mtspr DER, r2
/* set up the stack on top of internal DPRAM */
- lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
- ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
+ lis r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h
+ ori r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l
stw r0, -4(r3)
stw r0, -8(r3)
addi r1, r3, -8
int pamu_init(void)
{
- u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+ u32 base_addr = CFG_SYS_PAMU_ADDR;
struct ccsr_pamu *regs;
u32 i = 0;
u64 ppaact_phys, ppaact_lim, ppaact_size;
void pamu_enable(void)
{
u32 i = 0;
- u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+ u32 base_addr = CFG_SYS_PAMU_ADDR;
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
PAMU_PCR_PE);
void pamu_reset(void)
{
u32 i = 0;
- u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+ u32 base_addr = CFG_SYS_PAMU_ADDR;
struct ccsr_pamu *regs;
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
void pamu_disable(void)
{
u32 i = 0;
- u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+ u32 base_addr = CFG_SYS_PAMU_ADDR;
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++;
-#ifdef CONFIG_SYS_FLASH_BASE_PHYS
+#ifdef CFG_SYS_FLASH_BASE_PHYS
tbl->start_addr[i] =
- (uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS);
+ (uint64_t)virt_to_phys((void *)CFG_SYS_FLASH_BASE_PHYS);
tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++;
#endif
-#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR))
+#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR))
tbl->start_addr[i] =
- (uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR);
+ (uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR);
tbl->size[i] = 256 * 1024; /* 256K CPC flash */
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
#elif defined(CONFIG_ARCH_P1023)
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 2
-#define CONFIG_SYS_QMAN_NUM_PORTALS 3
-#define CONFIG_SYS_BMAN_NUM_PORTALS 3
-#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
+#define CFG_SYS_QMAN_NUM_PORTALS 3
+#define CFG_SYS_BMAN_NUM_PORTALS 3
+#define CFG_SYS_FM_MURAM_SIZE 0x10000
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_NUM_FM2_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FM2_DTSEC 5
#define CFG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131)
#define CFG_SYS_FSL_SRDS_3
#define CFG_SYS_FSL_SRDS_4
#define CFG_SYS_NUM_FMAN 2
-#define CONFIG_SYS_PME_CLK 0
+#define CFG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FM1_CLK 3
-#define CONFIG_SYS_FM2_CLK 3
-#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CFG_SYS_FM1_CLK 3
+#define CFG_SYS_FM2_CLK 3
+#define CFG_SYS_FM_MURAM_SIZE 0x60000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_FM1_CLK 0
+#define CFG_SYS_FM1_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
-#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CFG_SYS_FM_MURAM_SIZE 0x60000
#ifdef CONFIG_ARCH_B4860
#define CONFIG_MAX_DSP_CPUS 12
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_PME_PLAT_CLK_DIV 2
-#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
+#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_FM_PLAT_CLK_DIV 1
-#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
-#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
+#define CFG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
+#define CFG_SYS_FM_MURAM_SIZE 0x30000
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define CFG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FM1_CLK 0
+#define CFG_SYS_FM1_CLK 0
#define CONFIG_QBMAN_CLK_DIV 1
-#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
+#define CFG_SYS_FM_MURAM_SIZE 0x30000
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#endif
#define CONFIG_PME_PLAT_CLK_DIV 1
-#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FM1_CLK 0
+#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
+#define CFG_SYS_FM1_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
extern void init_early_memctl_regs(void);
extern void upmconfig(uint upm, uint *table, uint size);
-#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
+#define LBC_BASE_ADDR ((fsl_lbc_t *)CFG_SYS_LBC_ADDR)
#define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
#define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
#define SET_SRIO_LIODN_1(port, idA) \
{ .id = { idA }, .num_ids = 1, .portid = port, \
.reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
- + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
}
#define SET_SRIO_LIODN_2(port, idA, idB) \
{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
.reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
- + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
.reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
- + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
}
#define SET_SRIO_LIODN_BASE(port, id_a) \
{ .compat[0] = name1, \
.compat[1] = name2, \
.id = { idA }, .num_ids = 1, \
- .reg_offset = off + CONFIG_SYS_CCSRBAR, \
- .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ .reg_offset = off + CFG_SYS_CCSRBAR, \
+ .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
}
#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
{ .compat = name, \
.id = { idA }, .num_ids = 1, \
- .reg_offset = off + CONFIG_SYS_CCSRBAR, \
- .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ .reg_offset = off + CFG_SYS_CCSRBAR, \
+ .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
}
#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
{ .compat = name, \
.id = { idA, idB }, .num_ids = 2, \
- .reg_offset = off + CONFIG_SYS_CCSRBAR, \
- .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ .reg_offset = off + CFG_SYS_CCSRBAR, \
+ .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
}
#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
#ifdef CONFIG_NXP_ESBC
#if defined(CONFIG_FSL_CORENET)
-#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
+#define CFG_SYS_PBI_FLASH_BASE 0xc0000000
#else
-#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
+#define CFG_SYS_PBI_FLASH_BASE 0xce000000
#endif
-#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
+#define CFG_SYS_PBI_FLASH_WINDOW 0xcff80000
#if defined(CONFIG_TARGET_T2080QDS) || \
defined(CONFIG_TARGET_T2080RDB) || \
defined(CONFIG_TARGET_T1042D4RDB) || \
defined(CONFIG_TARGET_T1042RDB_PI) || \
defined(CONFIG_ARCH_T1024)
-#undef CONFIG_SYS_INIT_L3_ADDR
-#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
+#undef CFG_SYS_INIT_L3_ADDR
+#define CFG_SYS_INIT_L3_ADDR 0xbff00000
#endif
#if defined(CONFIG_RAMBOOT_PBL)
-#undef CONFIG_SYS_INIT_L3_ADDR
-#ifdef CONFIG_SYS_INIT_L3_VADDR
-#define CONFIG_SYS_INIT_L3_ADDR \
- (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
+#undef CFG_SYS_INIT_L3_ADDR
+#ifdef CFG_SYS_INIT_L3_VADDR
+#define CFG_SYS_INIT_L3_ADDR \
+ (CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
0xbff00000
#else
-#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
+#define CFG_SYS_INIT_L3_ADDR 0xbff00000
#endif
#endif
#define CFG_SYS_MPC83xx_ESDHC_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
-#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
+#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_MDIO1_OFFSET 0x24000
+#define CFG_SYS_TSEC1_OFFSET 0x24000
+#define CFG_SYS_MDIO1_OFFSET 0x24000
-#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#endif /* __IMMAP_83xx__ */
#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
/* In SFPv3, OSPR register is now at offset 0x200.
* * So directly mapping sfp register map to this address */
-#define CONFIG_SYS_OSPR_OFFSET 0x200
-#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#define CFG_SYS_OSPR_OFFSET 0x200
+#define CFG_SYS_SFP_OFFSET (0xE8000 + CFG_SYS_OSPR_OFFSET)
#else
-#define CONFIG_SYS_SFP_OFFSET 0xE8000
+#define CFG_SYS_SFP_OFFSET 0xE8000
#endif
#define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CFG_SYS_FSL_SEC_OFFSET 0x300000
#define CFG_SYS_FSL_JR0_OFFSET 0x301000
-#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
+#define CFG_SYS_SEC_MON_OFFSET 0x314000
#define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CFG_SYS_FSL_QMAN_OFFSET 0x318000
#define CFG_SYS_FSL_BMAN_OFFSET 0x31a000
#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
#ifdef CONFIG_TSECV2
-#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
+#define CFG_SYS_TSEC1_OFFSET 0xB0000
#elif defined(CONFIG_TSECV2_1)
-#define CONFIG_SYS_TSEC1_OFFSET 0x10000
+#define CFG_SYS_TSEC1_OFFSET 0x10000
#else
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CFG_SYS_TSEC1_OFFSET 0x24000
#endif
-#define CONFIG_SYS_MDIO1_OFFSET 0x24000
+#define CFG_SYS_MDIO1_OFFSET 0x24000
#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#if defined(CONFIG_ARCH_C29X)
#define CFG_SYS_FSL_SEC_OFFSET 0x80000
#endif
#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
-#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
-#define CONFIG_SYS_SFP_OFFSET 0xE7000
+#define CFG_SYS_SEC_MON_OFFSET 0xE6000
+#define CFG_SYS_SFP_OFFSET 0xE7000
#define CFG_SYS_FSL_QMAN_OFFSET 0x88000
#define CFG_SYS_FSL_BMAN_OFFSET 0x8a000
#define CFG_SYS_FSL_FM1_OFFSET 0x100000
#define CFG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CFG_SYS_FSL_CPC_ADDR \
- (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
+ (CFG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
#define CFG_SYS_FSL_SCFG_ADDR \
- (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
+ (CFG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
#define CFG_SYS_FSL_QMAN_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET)
#define CFG_SYS_FSL_BMAN_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
#define CFG_SYS_FSL_DDR3_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
-#define CONFIG_SYS_LBC_ADDR \
+#define CFG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
-#define CONFIG_SYS_IFC_ADDR \
+#define CFG_SYS_IFC_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
#define CFG_SYS_MPC85xx_ESPI_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET)
#define CFG_SYS_FSL_SRIO_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET)
-#define CONFIG_SYS_PAMU_ADDR \
+#define CFG_SYS_PAMU_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
#define CFG_SYS_PCIE1_ADDR \
#define CFG_SYS_PCIE2_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
-#define CONFIG_SYS_SFP_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+#define CFG_SYS_SFP_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET)
-#define CONFIG_SYS_SEC_MON_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+#define CFG_SYS_SEC_MON_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET)
-#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
struct ccsr_cluster_l2 {
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
-#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
+#define CFG_SYS_DCSR_DCFG_OFFSET 0X20000
struct dcsr_dcfg_regs {
u8 res_0[0x520];
u32 ecccr1;
image_entry_arg_t image_entry =
(image_entry_arg_t)spl_image->entry_point;
- image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ,
+ image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CFG_SYS_BOOTMAPSZ,
0, 0);
}
#endif /* CONFIG_SPL_OS_BOOT */
#include <asm/processor.h>
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
+#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
+#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
#endif
/* Make sure the window is below U-Boot. */
assert(window + LARGE_PAGE_SIZE <
- gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_STACK_SIZE);
+ gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE);
/* Map the page into the window and then memset the appropriate part. */
x86_phys_map_page(window, map_addr, 1);
memset((void *)(window + offset), c, size);
* The actual location of memory and IO is the board property.
*/
-#define IOADDR(x) (CONFIG_SYS_IO_BASE + (x))
-#define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x))
+#define IOADDR(x) (CFG_SYS_IO_BASE + (x))
+#define MEMADDR(x) (CFG_SYS_MEMORY_BASE + (x))
#define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \
XCHAL_VECBASE_RESET_PADDR)
int checkboard (void)
{
puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n");
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
puts(" Boot from Internal FLASH\n");
#endif
return 0;
size = 0;
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
- MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
+ MCFSDRAMC_DCR_RC((15 * CFG_SYS_CLK / 1000000) >> 4);
asm (" nop");
#ifdef CFG_SYS_SDRAM_BASE0
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)|
return 0;
}
-#if defined(CONFIG_SYS_DRAM_TEST)
+#if defined(CFG_SYS_DRAM_TEST)
int testdram(void)
{
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
#if defined(CONFIG_MISC_INIT_R)
-#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
+#if defined(CONFIG_CMD_I2C) && defined(CFG_SYS_I2C_G762_ADDR)
/*
* Start I2C fan (GMT G762 controller)
*/
/* Enable open-loop and PWM modes */
data = 0x20;
- if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+ if (i2c_write(CFG_SYS_I2C_G762_ADDR,
G762_REG_FAN_CMD1, 1, &data, 1) != 0)
goto err;
data = 0;
- if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+ if (i2c_write(CFG_SYS_I2C_G762_ADDR,
G762_REG_SET_CNT, 1, &data, 1) != 0)
goto err;
/*
* Start fan at low speed (2800 RPM):
*/
data = 0x08;
- if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+ if (i2c_write(CFG_SYS_I2C_G762_ADDR,
G762_REG_SET_OUT, 1, &data, 1) != 0)
goto err;
return;
err:
printf("Error: failed to start I2C fan @%02x\n",
- CONFIG_SYS_I2C_G762_ADDR);
+ CFG_SYS_I2C_G762_ADDR);
}
#else
static void init_fan(void) {}
-#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
+#endif /* CONFIG_CMD_I2C && CFG_SYS_I2C_G762_ADDR */
#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
/*
t = (struct tag_mv_uboot *)¶ms->u;
t->uboot_version = VER_NUM | syno_board_id();
- t->tclk = CONFIG_SYS_TCLK;
- t->sysclk = CONFIG_SYS_TCLK * 2;
+ t->tclk = CFG_SYS_TCLK;
+ t->sysclk = CFG_SYS_TCLK * 2;
t->isusbhost = usb_port_modes();
for (i = 0; i < ETHADDR_MAX; i++) {
static unsigned long long div_timer = 1; /* Divisor to convert timer reading
* change to U-Boot ticks
*/
-/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
+/* CONFIG_SYS_HZ = CFG_SYS_HZ_CLOCK/(div_clock * div_timer) */
static ulong timestamp; /* U-Boot ticks since startup */
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
+#define READ_TIMER (*(volatile ulong *)(CFG_SYS_TIMERBASE+4))
/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
* - unless otherwise stated
int timer_init (void)
{
/* Load timer with initial value */
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
+ *(volatile ulong *)(CFG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
#ifdef CONFIG_ARCH_CINTEGRATOR
/* Set timer to be
* enabled 1
* 32 bit 1
* wrapping 0
*/
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
+ *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x000000C2;
#else
/* Set timer to be
* enabled 1
* divider 256 10
* XX 00
*/
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
+ *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x00000088;
#endif
/* init the timestamp */
/* start "advancing" time stamp from 0 */
timestamp = 0L;
- div_timer = CONFIG_SYS_HZ_CLOCK;
+ div_timer = CFG_SYS_HZ_CLOCK;
do_div(div_timer, CONFIG_SYS_HZ);
do_div(div_timer, div_clock);
*/
ulong get_tbclk(void)
{
- unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
+ unsigned long long tmp = CFG_SYS_HZ_CLOCK;
do_div(tmp, div_clock);
#define JUNO_FLASH_SEC_SIZE (256 * 1024)
static phys_addr_t find_dtb_in_nor_flash(const char *partname)
{
- phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
+ phys_addr_t sector = CFG_SYS_FLASH_BASE;
int i;
for (i = 0;
imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
reg = readl(imginfo + 0x54);
- return CONFIG_SYS_FLASH_BASE +
+ return CFG_SYS_FLASH_BASE +
reg * JUNO_FLASH_SEC_SIZE;
}
}
* else non-zero (hang).
*/
-#ifdef CONFIG_SYS_FPGAREG_FREQ
- return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
+#ifdef CFG_SYS_FPGAREG_FREQ
+ return (*(volatile unsigned long *)CFG_SYS_FPGAREG_FREQ);
#else
/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
return 50000000;
if (s == 0) {
unsigned int x;
char s[] = __stringify(CONFIG_ETHBASE);
- x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
+ x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW)
& FPGAREG_MAC_MASK;
sprintf(&s[15], "%02x", x);
env_set("ethaddr", s);
static struct ethoc_eth_pdata ethoc_pdata = {
.eth_pdata = {
- .iobase = CONFIG_SYS_ETHOC_BASE,
+ .iobase = CFG_SYS_ETHOC_BASE,
},
- .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
+ .packet_base = CFG_SYS_ETHOC_BUFFER_ADDR,
};
U_BOOT_DRVINFO(ethoc) = {
int ret;
char *ptype;
- struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE;
+ struct storage_partition *part = (void *)CFG_SYS_LOWMEM_BASE;
pcount = atf_get_pcount();
#include <dm/platform_data/serial_pl01x.h>
static const struct pl01x_serial_plat serial0 = {
- .base = CONFIG_SYS_SERIAL0,
+ .base = CFG_SYS_SERIAL0,
.type = TYPE_PL011,
.clock = 0,
.skip_init = true,
};
static const struct pl01x_serial_plat serial1 = {
- .base = CONFIG_SYS_SERIAL1,
+ .base = CFG_SYS_SERIAL1,
.type = TYPE_PL011,
.clock = 0,
.skip_init = true,
#include <uuid.h>
#include <linux/delay.h>
-#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+#define PHYS_FLASH_1 CFG_SYS_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
}
flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
+ CFG_SYS_FLASH_BASE,
+ CFG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
return size;
}
#define CMD_PROGRAM 0x00A0
#define CMD_UNLOCK_BYPASS 0x0020
-#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
+#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x000002AA<<1)))
#define BIT_ERASE_DONE 0x0080
#define BIT_RDY_MASK 0x0080
#if defined(CONFIG_SOC_CA8277B)
/* Enable CPU Timer */
- ldr x0, =CONFIG_SYS_TIMER_BASE
+ ldr x0, =CFG_SYS_TIMER_BASE
mov x1, #1
str w1, [x0]
#endif
unsigned int reg_data, jtag_id;
/* Enable timer */
- writel(1, CONFIG_SYS_TIMER_BASE);
+ writel(1, CFG_SYS_TIMER_BASE);
/* Enable snoop in CCI400 slave port#4 */
writel(3, 0xF5595000);
/* Set polarity to non-inverted */
buf[0] = 0x0;
buf[1] = 0x0;
- ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
+ ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
if (ret) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
- CONFIG_SYS_I2C_EXPANDER_ADDR);
+ CFG_SYS_I2C_EXPANDER_ADDR);
return ret;
}
/* Configure P07-P05 as outputs */
buf[0] = 0x1f;
buf[1] = 0xff;
- ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
+ ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
if (ret) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
- CONFIG_SYS_I2C_EXPANDER_ADDR);
+ CFG_SYS_I2C_EXPANDER_ADDR);
}
/* For Ethernet RMII selection
* P06(SelB)=1
* P05(SelC)=1
*/
- if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+ if (i2c_read(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
printf("\nExpander @ 0x%02x read FAILED!!!\n",
- CONFIG_SYS_I2C_EXPANDER_ADDR);
+ CFG_SYS_I2C_EXPANDER_ADDR);
}
buf[0] &= 0x1f;
buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
- if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+ if (i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
- CONFIG_SYS_I2C_EXPANDER_ADDR);
+ CFG_SYS_I2C_EXPANDER_ADDR);
}
/* Set the output as high */
int board_mmc_getcd(struct mmc *mmc)
{
- return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
+ return !at91_get_pio_value(CFG_SYS_MMC_CD_PIN);
}
#endif
if (gd->flags & GD_FLG_RELOC)
return (void *)gd->fdt_blob;
else
- return (void *)CONFIG_SYS_TMPVIRT;
+ return (void *)CFG_SYS_TMPVIRT;
}
static uint64_t get_fdt_phys(void)
* U-Boot is relocated to RAM already, let's delete the temporary FDT
* virtual-physical mapping that was used in the pre-relocation phase.
*/
- disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1));
+ disable_tlb(find_tlb_idx((void *)CFG_SYS_TMPVIRT, 1));
/*
* Detect the presence of the platform bus node, and
init_used_tlb_cams();
/* Create a dynamic AS=0 CCSRBAR mapping */
- assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ assert(!tlb_map_range(CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
1024 * 1024, TLB_MAP_IO));
/* Create a RAM map that spans all accessible RAM */
if (str && (strcmp(str, "4") == 0)) {
writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
AT91SAM9_PMC_MDIV_4, &pmc->mckr);
- at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
serial_setbrg();
/* Notify the user that the clock is not default */
printf("Setting master clock to %s MHz\n",
int fsl_check_boot_mode_secure(void)
{
uint32_t val;
- struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
{
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
- u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
+ u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE);
u32 flash_addr, addr;
int found = 0;
int i = 0;
*/
#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
sg_tbl = (struct fsl_secboot_sg_table *)
- (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ (((u32)hdr->psgtable & ~(CFG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
/* IE Key Table is the first entry in the SG Table */
#if defined(CONFIG_MPC85xx)
*ie_addr = (uintptr_t)((sg_tbl->src_addr &
- ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+ ~(CFG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
*ie_addr = (uintptr_t)sg_tbl->src_addr;
/* This function returns ospr's key_revoc values.*/
static u32 get_key_revoc(void)
{
- struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
OSPR_KEY_REVOC_SHIFT;
}
*/
static void fsl_secboot_header_verification_failure(void)
{
- struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
/* 29th bit of OSPR is ITS */
u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
*/
static void fsl_secboot_image_verification_failure(void)
{
- struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
uintptr_t *img_addr_ptr)
{
- struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
ulong hash[SHA256_BYTES/sizeof(ulong)];
char hash_str[NUM_HEX_CHARS + 1];
struct fsl_secboot_img_priv *img;
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+ SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
#endif
#ifdef PIXIS_BASE_PHYS
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
#ifdef CPLD_BASE_PHYS
SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+ SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+ CFG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
#ifdef CPLD_BASE
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
#if !defined(CONFIG_NXP_ESBC)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
- * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
+ * the physical address of the SRAM is at CFG_SYS_INIT_L3_ADDR,
* and virtual address is CONFIG_SYS_MONITOR_BASE
*/
SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000,
- CONFIG_SYS_INIT_L3_ADDR & 0xfff00000,
+ CFG_SYS_INIT_L3_ADDR & 0xfff00000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#endif
#endif
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
0, 6, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x00100000,
+ CFG_SYS_BMAN_MEM_PHYS + 0x00100000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_1M, 1),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
MAS3_SW|MAS3_SR, 0,
0, 11, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x00100000,
+ CFG_SYS_QMAN_MEM_PHYS + 0x00100000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_1M, 1),
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_4M, 1),
#endif
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#endif
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#ifdef CFG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg)
{
#if !CONFIG_IS_ENABLED(DM_I2C)
- return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+ return i2c_reg_read(CFG_SYS_I2C_FPGA_ADDR, reg);
#else
struct udevice *dev;
- if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+ if (i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev))
return 0xff;
return dm_i2c_reg_read(dev, reg);
{
u8 val = value;
#if !CONFIG_IS_ENABLED(DM_I2C)
- i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+ i2c_reg_write(CFG_SYS_I2C_FPGA_ADDR, reg, val);
#else
struct udevice *dev;
- if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+ if (!i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev))
dm_i2c_reg_write(dev, reg, val);
#endif
char *qixis_read_time(char *result);
char *qixis_read_tag(char *buf);
const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#ifdef CFG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg);
void qixis_write_i2c(unsigned int reg, u8 value);
#endif
-#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CFG_SYS_I2C_FPGA_ADDR)
#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
#define QIXIS_WRITE(reg, value) \
qixis_write_i2c(offsetof(struct qixis, reg), value)
#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
#endif
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#ifdef CFG_SYS_I2C_FPGA_ADDR
#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
#define QIXIS_WRITE_I2C(reg, value) \
qixis_write_i2c(offsetof(struct qixis, reg), value)
struct udevice *dev;
int ret;
- ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
+ ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
#else
i2c_set_bus_num(bus_num);
- i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+ i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
#endif
return 0;
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
DCFG_CCSR_PORSR1_RCW_SRC_I2C);
- out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+ out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
pinctl);
#endif
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
static void cpld_show(void)
{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
in_8(&cpld_data->cpld_ver) & VERSION_MASK,
static void convert_serdes_mux(int type, int need_reset)
{
char current_serdes;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
current_serdes = cpld_data->serdes_mux;
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
int config_board_mux(void)
{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
int conflict_flag;
conflict_flag = 0;
&& !defined(CONFIG_SPL_BUILD)
static void convert_flash_bank(char bank)
{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
printf("Now switch to boot from flash bank %d.\n", bank);
cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
if (argc > 2)
return CMD_RET_USAGE;
static void print_serdes_mux(void)
{
char current_serdes;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
current_serdes = cpld_data->serdes_mux;
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nor0",
- CONFIG_SYS_NOR0_CSPR,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR0_CSPR,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"nor1",
- CONFIG_SYS_NOR1_CSPR,
- CONFIG_SYS_NOR1_CSPR_EXT,
+ CFG_SYS_NOR1_CSPR,
+ CFG_SYS_NOR1_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
- CONFIG_SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_AMASK,
+ CFG_SYS_FPGA_CSOR,
{
- CONFIG_SYS_FPGA_FTIM0,
- CONFIG_SYS_FPGA_FTIM1,
- CONFIG_SYS_FPGA_FTIM2,
- CONFIG_SYS_FPGA_FTIM3
+ CFG_SYS_FPGA_FTIM0,
+ CFG_SYS_FPGA_FTIM1,
+ CFG_SYS_FPGA_FTIM2,
+ CFG_SYS_FPGA_FTIM3
},
}
};
},
{
"nor0",
- CONFIG_SYS_NOR0_CSPR,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR0_CSPR,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"nor1",
- CONFIG_SYS_NOR1_CSPR,
- CONFIG_SYS_NOR1_CSPR_EXT,
+ CFG_SYS_NOR1_CSPR,
+ CFG_SYS_NOR1_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
- CONFIG_SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_AMASK,
+ CFG_SYS_FPGA_CSOR,
{
- CONFIG_SYS_FPGA_FTIM0,
- CONFIG_SYS_FPGA_FTIM1,
- CONFIG_SYS_FPGA_FTIM2,
- CONFIG_SYS_FPGA_FTIM3
+ CFG_SYS_FPGA_FTIM0,
+ CFG_SYS_FPGA_FTIM1,
+ CFG_SYS_FPGA_FTIM2,
+ CFG_SYS_FPGA_FTIM3
},
}
};
u8 cpld_read(unsigned int reg)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg);
}
void cpld_write(unsigned int reg, u8 value)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
},
{
"cpld",
- CONFIG_SYS_CPLD_CSPR,
- CONFIG_SYS_CPLD_CSPR_EXT,
- CONFIG_SYS_CPLD_AMASK,
- CONFIG_SYS_CPLD_CSOR,
+ CFG_SYS_CPLD_CSPR,
+ CFG_SYS_CPLD_CSPR_EXT,
+ CFG_SYS_CPLD_AMASK,
+ CFG_SYS_CPLD_CSOR,
{
- CONFIG_SYS_CPLD_FTIM0,
- CONFIG_SYS_CPLD_FTIM1,
- CONFIG_SYS_CPLD_FTIM2,
- CONFIG_SYS_CPLD_FTIM3
+ CFG_SYS_CPLD_FTIM0,
+ CFG_SYS_CPLD_FTIM1,
+ CFG_SYS_CPLD_FTIM2,
+ CFG_SYS_CPLD_FTIM3
},
}
};
},
{
"cpld",
- CONFIG_SYS_CPLD_CSPR,
- CONFIG_SYS_CPLD_CSPR_EXT,
- CONFIG_SYS_CPLD_AMASK,
- CONFIG_SYS_CPLD_CSOR,
+ CFG_SYS_CPLD_CSPR,
+ CFG_SYS_CPLD_CSPR_EXT,
+ CFG_SYS_CPLD_AMASK,
+ CFG_SYS_CPLD_CSOR,
{
- CONFIG_SYS_CPLD_FTIM0,
- CONFIG_SYS_CPLD_FTIM1,
- CONFIG_SYS_CPLD_FTIM2,
- CONFIG_SYS_CPLD_FTIM3
+ CFG_SYS_CPLD_FTIM0,
+ CFG_SYS_CPLD_FTIM1,
+ CFG_SYS_CPLD_FTIM2,
+ CFG_SYS_CPLD_FTIM3
},
}
};
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nor0",
- CONFIG_SYS_NOR0_CSPR,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR0_CSPR,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"nor1",
- CONFIG_SYS_NOR1_CSPR,
- CONFIG_SYS_NOR1_CSPR_EXT,
+ CFG_SYS_NOR1_CSPR,
+ CFG_SYS_NOR1_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
- CONFIG_SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_AMASK,
+ CFG_SYS_FPGA_CSOR,
{
- CONFIG_SYS_FPGA_FTIM0,
- CONFIG_SYS_FPGA_FTIM1,
- CONFIG_SYS_FPGA_FTIM2,
- CONFIG_SYS_FPGA_FTIM3
+ CFG_SYS_FPGA_FTIM0,
+ CFG_SYS_FPGA_FTIM1,
+ CFG_SYS_FPGA_FTIM2,
+ CFG_SYS_FPGA_FTIM3
},
}
};
},
{
"nor0",
- CONFIG_SYS_NOR0_CSPR,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR0_CSPR,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"nor1",
- CONFIG_SYS_NOR1_CSPR,
- CONFIG_SYS_NOR1_CSPR_EXT,
+ CFG_SYS_NOR1_CSPR,
+ CFG_SYS_NOR1_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
- CONFIG_SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_AMASK,
+ CFG_SYS_FPGA_CSOR,
{
- CONFIG_SYS_FPGA_FTIM0,
- CONFIG_SYS_FPGA_FTIM1,
- CONFIG_SYS_FPGA_FTIM2,
- CONFIG_SYS_FPGA_FTIM3
+ CFG_SYS_FPGA_FTIM0,
+ CFG_SYS_FPGA_FTIM1,
+ CFG_SYS_FPGA_FTIM2,
+ CFG_SYS_FPGA_FTIM3
},
}
};
u8 cpld_read(unsigned int reg)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg);
}
void cpld_write(unsigned int reg, u8 value)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nor0",
- CONFIG_SYS_NOR0_CSPR_EARLY,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR0_CSPR_EARLY,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK,
CFG_SYS_NOR_CSOR,
{
CFG_SYS_NOR_FTIM3
},
0,
- CONFIG_SYS_NOR0_CSPR,
+ CFG_SYS_NOR0_CSPR,
0,
},
{
"nor1",
- CONFIG_SYS_NOR1_CSPR_EARLY,
- CONFIG_SYS_NOR0_CSPR_EXT,
+ CFG_SYS_NOR1_CSPR_EARLY,
+ CFG_SYS_NOR0_CSPR_EXT,
CFG_SYS_NOR_AMASK_EARLY,
CFG_SYS_NOR_CSOR,
{
CFG_SYS_NOR_FTIM3
},
0,
- CONFIG_SYS_NOR1_CSPR,
+ CFG_SYS_NOR1_CSPR,
CFG_SYS_NOR_AMASK,
},
{
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSOR,
{
SYS_FPGA_CS_FTIM0,
SYS_FPGA_CS_FTIM1,
},
{
"fpga",
- CONFIG_SYS_FPGA_CSPR,
- CONFIG_SYS_FPGA_CSPR_EXT,
+ CFG_SYS_FPGA_CSPR,
+ CFG_SYS_FPGA_CSPR_EXT,
SYS_FPGA_AMASK,
- CONFIG_SYS_FPGA_CSOR,
+ CFG_SYS_FPGA_CSOR,
{
SYS_FPGA_CS_FTIM0,
SYS_FPGA_CS_FTIM1,
/* Read the BRDCFG54 via CLPD */
#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
+ ret = i2c_read(CFG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
struct udevice *dev;
- ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
+ ret = i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
(void *)&brdcfg4, 1);
/* Write to the BRDCFG4 */
#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
+ ret = i2c_write(CFG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
Environment Variables
---------------------
- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
- the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+ the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
- mcmemsize: MC DRAM block size. If this variable is not defined
- the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+ the value CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
-------------------------------------------------------------------
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#if CONFIG_IS_ENABLED(DM_I2C)
- rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
+ rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR);
#else
rtc_enable_32khz_output();
#endif
static struct pl01x_serial_plat serial0 = {
#if CONFIG_CONS_INDEX == 0
- .base = CONFIG_SYS_SERIAL0,
+ .base = CFG_SYS_SERIAL0,
#elif CONFIG_CONS_INDEX == 1
- .base = CONFIG_SYS_SERIAL1,
+ .base = CFG_SYS_SERIAL1,
#else
#error "Unsupported console index value."
#endif
};
static struct pl01x_serial_plat serial1 = {
- .base = CONFIG_SYS_SERIAL1,
+ .base = CFG_SYS_SERIAL1,
.type = TYPE_PL011,
};
/*
* Set LED on
*/
- val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
+ val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED;
mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
return 0;
* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
*/
-#ifdef CONFIG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
/*
* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
*/
mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CONFIG_SYS_PLL_BYPASS
+#elif CFG_SYS_PLL_BYPASS
/*
* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
ulong size = 0;
ulong fbase = 0;
- fbase = (ulong) CONFIG_SYS_FLASH_BASE;
+ fbase = (ulong) CFG_SYS_FLASH_BASE;
flash_get_size((FPWV *) fbase, &flash_info[0]);
flash_get_offsets((ulong) fbase, &flash_info[0]);
fbase += flash_info[0].size;
info->start[0] = base;
info->protect[0] = 0;
- for (i = 1; i < CONFIG_SYS_SST_SECT; i++) {
+ for (i = 1; i < CFG_SYS_SST_SECT; i++) {
info->start[i] = info->start[i - 1]
- + CONFIG_SYS_SST_SECTSZ;
+ + CFG_SYS_SST_SECTSZ;
info->protect[i] = 0;
}
}
info->sector_count = 0;
info->size = 0;
- info->sector_count = CONFIG_SYS_SST_SECT;
- info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ;
+ info->sector_count = CFG_SYS_SST_SECT;
+ info->size = CFG_SYS_SST_SECT * CFG_SYS_SST_SECTSZ;
/* reset ID mode */
*addr = (FPWV) 0x00F000F0;
start = get_timer(0);
- if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
+ if ((s_last - s_first) == (CFG_SYS_SST_SECT - 1)) {
if (prot == 0) {
addr = (FPWV *) info->start[0];
enable_interrupts();
return 0;
- } else if (prot == CONFIG_SYS_SST_SECT) {
+ } else if (prot == CFG_SYS_SST_SECT) {
return 1;
}
}
flag = disable_interrupts();
- base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* First sector */
+ base = (FPWV *) (CFG_SYS_FLASH_BASE); /* First sector */
base[FLASH_CYCLE1] = 0x00AA; /* unlock */
base[FLASH_CYCLE2] = 0x0055; /* unlock */
return (2);
}
- base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+ base = (FPWV *) (CFG_SYS_FLASH_BASE);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
u32 RC, temp;
- RC = (CONFIG_SYS_CLK / 1000000) >> 1;
+ RC = (CFG_SYS_CLK / 1000000) >> 1;
RC = (RC * 15) >> 4;
/* Initialize DRAM Control Register: DCR */
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
#define CALC_TIMING(t) (t + period - 1) / period
- period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
+ period = 1000000000 / (CFG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
CONFIG_M53017EVB -- define for M53017EVB board
CONFIG_MCFUART -- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
CONFIG_BAUDRATE -- define UART baudrate
CONFIG_MCFRTC -- define to use common CF RTC driver
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
CONFIG_SYS_IMMR -- define for MBAR offset
-CONFIG_SYS_MBAR -- define MBAR offset
+CFG_SYS_MBAR -- define MBAR offset
CONFIG_MONITOR_IS_IN_RAM -- Not support
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
+CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd_to_nand(mtdinfo);
- volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+ volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
CONFIG_M5373EVB -- define for M5373EVB board
CONFIG_MCFUART -- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
CONFIG_BAUDRATE -- define UART baudrate
CONFIG_MCFRTC -- define to use common CF RTC driver
CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
CONFIG_SYS_IMMR -- define for MBAR offset
-CONFIG_SYS_MBAR -- define MBAR offset
+CFG_SYS_MBAR -- define MBAR offset
CONFIG_MONITOR_IS_IN_RAM -- Not support
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM
+CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM
CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd_to_nand(mtdinfo);
- volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+ volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SYS_DRAM_TEST)
+#if defined(CFG_SYS_DRAM_TEST)
int
testdram(void)
{
im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+ im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
udelay(50000);
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+ im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
udelay(1000);
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG;
udelay(1000);
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CFG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL;
sync();
udelay(1000);
struct law_entry law_table[] = {
/* LBC window - maps 256M */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CFG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
uint idx;
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+ uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
puts("LBC SDRAM: ");
- print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+ print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
"\n");
/*
*/
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->lbcr = CFG_SYS_LBC_LBCR;
asm("msync");
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ lbc->lsrt = CFG_SYS_LBC_LSRT;
+ lbc->mrtpr = CFG_SYS_LBC_MRTPR;
asm("msync");
/*
* MPC8548 uses "new" 15-16 style addressing.
*/
- lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+ lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON;
lsdmr_common |= LSDMR_BSMA1516;
/*
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
* Entry 0:
* FLASH(cover boot page) 16M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
* Entry 1:
* CCSRBAR 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
* Entry 2:
* LBC SDRAM 64M Cacheable, non-guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
- CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE,
+ CFG_SYS_LBC_SDRAM_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 2, BOOKE_PAGESZ_64M, 1),
int rev = readl(&fuse->gp[6]);
- if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
+ if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR))
rev = 0;
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
int ret;
struct pmic *p;
- if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+ if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) {
ret = pmic_dialog_init(I2C_PMIC);
if (ret)
return ret;
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
};
int board_early_init_f(void)
{
ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
/* Clock configuration to access CPLD using IFC(GPCM) */
setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
/*
int board_early_init_r(void)
{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const unsigned int flashbase = CFG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
disable_tlb(flash_esel);
}
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_16M, 1);
set_tlb(1, flashbase + 0x1000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ CFG_SYS_FLASH_BASE_PHYS + 0x1000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
return 0;
struct udevice *dev;
int ret;
#if defined(CONFIG_TARGET_P1010RDB_PA)
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
I2C_PCA9557_ADDR1, 1, &dev);
#endif
#else
#if defined(CONFIG_TARGET_P1010RDB_PA)
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
switch (ctrl_type) {
case MUX_TYPE_IFC:
int checkboard(void)
{
struct cpu_type *cpu;
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
u8 val;
cpu = gd->arch.cpu;
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
console_init_f();
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
#endif
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE + 0x1000000,
+ CFG_SYS_FLASH_BASE_PHYS + 0x1000000,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 3, BOOKE_PAGESZ_16M, 1),
#endif
/* *I*G - Board CPLD */
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
0, 7, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
/* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1)
#endif
}
#endif /* CONFIG_SYS_DDR_RAW_TIMING */
-#ifdef CONFIG_SYS_DDR_CS0_BNDS
+#ifdef CFG_SYS_DDR_CS0_BNDS
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
char buf[32];
size_t ddr_size;
fsl_ddr_cfg_regs_t ddr_cfg_regs = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[0].bnds = CFG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CFG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2,
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+ .cs[1].bnds = CFG_SYS_DDR_CS1_BNDS,
+ .cs[1].config = CFG_SYS_DDR_CS1_CONFIG,
+ .cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2,
#endif
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+ .timing_cfg_3 = CFG_SYS_DDR_TIMING_3,
+ .timing_cfg_0 = CFG_SYS_DDR_TIMING_0,
+ .timing_cfg_1 = CFG_SYS_DDR_TIMING_1,
+ .timing_cfg_2 = CFG_SYS_DDR_TIMING_2,
+ .ddr_sdram_cfg = CFG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CFG_SYS_DDR_MODE_1,
+ .ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2,
+ .ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CFG_SYS_DDR_INTERVAL,
.ddr_data_init = 0xdeadbeef, /* Poison value */
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+ .ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL,
+ .ddr_init_addr = CFG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CFG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CFG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2
};
get_sys_info(&sysinfo);
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE,
ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_VSC7385_ENET
- SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CFG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+ SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
* This ensures that external watchdog does not trigger
* another reset or possible infinite reset loop.
*/
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
in_8(&cpld_data->wd_cfg); /* Read back to sync write */
}
void board_reset_last(void)
{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
out_8(&cpld_data->system_rst, 1);
}
void board_cpld_init(void)
{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg);
out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
int checkboard(void)
{
- struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u8 in, out, invert, io_config, val;
int bus_num = CONFIG_SYS_SPD_BUS_NUM;
struct udevice *dev;
int ret;
- ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
+ ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_PCA9557_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
#else /* Non DM I2C support - will be removed */
i2c_set_bus_num(bus_num);
- if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
- i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
- i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
- i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
+ if (i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
+ i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
+ i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
+ i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
}
int board_early_init_r(void)
{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const unsigned int flashbase = CFG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
#ifdef CONFIG_VSC7385_ENET
unsigned int vscfw_addr;
disable_tlb(flash_esel);
}
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+ set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+ CFG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
#ifdef CONFIG_VSC7385_ENET
/* *I*G - VSC7385 Switch */
- SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_VSC7385_BASE, CFG_SYS_VSC7385_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_1M, 1),
#endif
#endif /* not SPL */
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020RDB_PD)
/* **M** - 2G DDR on P1020MBG, map the second 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#endif /* RAMBOOT/SPL */
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
/* ***G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#if CONFIG_SYS_L2_SIZE >= (256 << 10)
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + 0x40000,
+ CFG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 12, BOOKE_PAGESZ_256K, 1)
#endif
};
static int riser_phy_addr[] = {
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
+ CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
+ CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
+ CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
+ CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
};
/*
slot = lane_to_slot[lane];
if (slot) {
sprintf(phy, "phy_sgmii_%x",
- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ (port - FM1_DTSEC1));
fdt_set_phy_handle(fdt, compat, addr, phy);
} else {
sprintf(phy, "phy_sgmii_%x",
- CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
+ CFG_SYS_FM1_DTSEC1_PHY_ADDR
+ (port - FM1_DTSEC1));
fdt_set_phy_handle(fdt, compat, addr, phy);
}
* is RGMII, we'll also override its PHY address later. We assume that
* DTSEC4 and DTSEC5 are used for RGMII.
*/
- fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
case PHY_INTERFACE_MODE_RGMII_ID:
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
- CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+ CFG_SYS_FM1_DTSEC5_PHY_ADDR :
+ CFG_SYS_FM1_DTSEC4_PHY_ADDR);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
slot = lane_to_slot[lane];
if (slot)
fm_info_set_phy_address(FM1_10GEC1,
- CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+ CFG_SYS_FM1_10GEC1_PHY_ADDR);
}
fm_info_set_mdio(FM1_10GEC1,
int board_early_init_r(void)
{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const unsigned int flashbase = CFG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
disable_tlb(flash_esel);
}
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
u8 cpld_read(unsigned int reg)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg);
}
void cpld_write(unsigned int reg, u8 value)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
- void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+ void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
/* does not provide HW signals for power management */
clrbits_8(cpld_base + 0x17, 0x40);
struct law_entry law_table[] = {
#ifdef CONFIG_MTD_NOR_FLASH
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#ifdef CFG_SYS_DCSRBAR_PHYS
+ SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
int board_early_init_r(void)
{
-#ifdef CONFIG_SYS_FLASH_BASE
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+#ifdef CFG_SYS_FLASH_BASE
+ const unsigned int flashbase = CFG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
disable_tlb(flash_esel);
}
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+ CFG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
* SRAM is at 0xfffc0000, it covered the 0xfffff000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256K, 1),
#else
#endif
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_16M, 1),
#endif
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif
-#ifdef CONFIG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
*
* The following macros need to be defined:
*
- * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
+ * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
*/
#include <common.h>
u8 cpld_read(unsigned int reg)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg);
}
void cpld_write(unsigned int reg, u8 value)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
- void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+ void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
/* does not provide HW signals for power management */
clrbits_8(cpld_base + 0x17, 0x40);
* DTSEC3
*/
fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_SGMII1_PHY_ADDR);
+ CFG_SYS_SGMII1_PHY_ADDR);
break;
#endif
#ifdef CONFIG_TARGET_T1042RDB
fm_info_set_phy_address(i, 0);
/* T1042RDB only supports SGMII on DTSEC3 */
fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_SGMII1_PHY_ADDR);
+ CFG_SYS_SGMII1_PHY_ADDR);
break;
#endif
#ifdef CONFIG_TARGET_T1042D4RDB
* & DTSEC3
*/
if (FM1_DTSEC1 == i)
- phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
+ phy_addr = CFG_SYS_SGMII1_PHY_ADDR;
if (FM1_DTSEC2 == i)
- phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
+ phy_addr = CFG_SYS_SGMII2_PHY_ADDR;
if (FM1_DTSEC3 == i)
- phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
+ phy_addr = CFG_SYS_SGMII3_PHY_ADDR;
fm_info_set_phy_address(i, phy_addr);
break;
#endif
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
if (FM1_DTSEC4 == i)
- phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+ phy_addr = CFG_SYS_RGMII1_PHY_ADDR;
if (FM1_DTSEC5 == i)
- phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+ phy_addr = CFG_SYS_RGMII2_PHY_ADDR;
fm_info_set_phy_address(i, phy_addr);
break;
case PHY_INTERFACE_MODE_QSGMII:
if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
for (i = 0; i < 4; i++) {
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+ phy_addr = CFG_SYS_FM1_QSGMII11_PHY_ADDR + i;
phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus);
if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
for (i = 4; i < 8; i++) {
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+ phy_addr = CFG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus);
struct law_entry law_table[] = {
#ifdef CONFIG_MTD_NOR_FLASH
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#ifdef CFG_SYS_DCSRBAR_PHYS
+ SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
| 0x24800000);
- out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
+ out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000),
pinctl);
}
#endif
int board_early_init_r(void)
{
-#ifdef CONFIG_SYS_FLASH_BASE
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+#ifdef CFG_SYS_FLASH_BASE
+ const unsigned int flashbase = CFG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
disable_tlb(flash_esel);
}
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+ CFG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) && \
!defined(CONFIG_NXP_ESBC)
/*
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
* SRAM is at 0xfffc0000, it covered the 0xfffff000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256K, 1),
* and virtual address is 0xfffc0000
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
- CONFIG_SYS_INIT_L3_ADDR,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_VADDR,
+ CFG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256K, 1),
#else
#endif
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_16M, 1),
#endif
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif
-#ifdef CONFIG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+ SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
#ifdef QIXIS_BASE_PHYS
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+ SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
int board_early_init_r(void)
{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const unsigned int flashbase = CFG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
disable_tlb(flash_esel);
}
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+ CFG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#endif
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
0, 7, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_16M, 1),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 11, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
u8 cpld_read(unsigned int reg)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg);
}
void cpld_write(unsigned int reg, u8 value)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+ SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+ SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
int board_early_init_r(void)
{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const unsigned int flashbase = CFG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
disable_tlb(flash_esel);
}
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+ CFG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#endif
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
0, 7, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_16M, 1),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 11, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
-#ifdef CONFIG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
#endif
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
*
* The following macros need to be defined:
*
- * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CFG_SYS_CPLD_BASE - The virtual address of the base of the
* CPLD register map
*
*/
u8 cpld_read(unsigned int reg)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
return in_8(p + reg);
}
void cpld_write(unsigned int reg, u8 value)
{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
+ void *p = (void *)CFG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+ SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+ SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CFG_SYS_NAND_BASE_PHYS
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
int board_early_init_r(void)
{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const unsigned int flashbase = CFG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
disable_tlb(flash_esel);
}
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+ CFG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 512K SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_512K, 1),
#else
#endif
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
0, 6, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_16M, 1),
#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 11, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
-#ifdef CONFIG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 18, BOOKE_PAGESZ_2G, 1)
#endif
out_be32(&im->sysconf.ddrlaw[0].bar,
CFG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
- out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+ out_be32(&im->sysconf.ddrcdr, CFG_SYS_DDRCDR_VALUE);
out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
- out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+ out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
/* Currently we use only one CS, so disable the other bank. */
out_be32(&im->ddr.cs_config[1], 0);
- out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
- out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
- out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
- out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
- out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+ out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_SDRAM_CLK_CNTL);
+ out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
- out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
- out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
- out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
- out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+ out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
+ out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
- out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
sync();
/* enable DDR controller */
{
if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
struct onenand_chip *this = mtd->priv;
- this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+ this->base = (void *)CFG_SYS_ONENAND_BASE;
return 0;
}
return 1;
void show_qrio(void)
{
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
printf("QRIO: id = %u, revision = %u\n",
{
u8 slftest;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
slftest = in_8(qrio_base + SLFTEST_OFF);
{
u8 pgy_pres;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
pgy_pres = in_8(qrio_base + BPRTH_OFF);
{
u32 gprt;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
gprt = in_be32(qrio_base + port_off + GPRT_OFF);
{
u32 gprt, mask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
{
u32 direct, mask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
{
u32 direct, mask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
{
u32 direct, mask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
void qrio_wdmask(u8 bit, bool wden)
{
u16 wdmask;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
wdmask = in_be16(qrio_base + WDMASK_OFF);
void qrio_prst(u8 bit, bool en, bool wden)
{
u16 prst;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
qrio_wdmask(bit, wden);
{
unsigned long prstcfg;
u8 i;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
void qrio_set_leds(void)
{
u8 ctrlh;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
/* set UNIT LED to RED and BOOT LED to ON */
ctrlh = in_8(qrio_base + CTRLH_OFF);
void qrio_enable_app_buffer(void)
{
u8 ctrll;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
/* enable application buffer */
ctrll = in_8(qrio_base + CTRLL_OFF);
void qrio_cpuwd_flag(bool flag)
{
u8 reason1;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
reason1 = in_8(qrio_base + REASON1_OFF);
if (flag)
bool qrio_reason_unitrst(void)
{
u16 reason;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
reason = in_be16(qrio_base + REASON1_OFF);
void qrio_uprstreq(u8 mode)
{
u32 rstcfg;
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
rstcfg = in_8(qrio_base + RSTCFG_OFF);
ulong early_bootcount_load(void)
{
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
u8 id = (id_rev >> 8) & 0xff;
u8 rev = id_rev & 0xff;
void early_bootcount_store(ulong ebootcount)
{
- void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
u8 id = (id_rev >> 8) & 0xff;
u8 rev = id_rev & 0xff;
static int piggy_present(void)
{
struct km_bec_fpga __iomem *base =
- (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+ (struct km_bec_fpga __iomem *)CFG_SYS_KMBEC_FPGA_BASE;
return in_8(&base->bprth) & PIGGY_PRESENT;
}
int board_early_init_r(void)
{
struct km_bec_fpga *base =
- (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+ (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
#if defined(CONFIG_ARCH_MPC8360)
unsigned short svid;
u32 ddr_size_log2;
out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
- out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
- out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
- out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
- out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
- out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
- out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
- out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
- out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
- out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
- out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
- out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
- out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+ out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f);
+ out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
+ out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
+ out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
+ out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
+ out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
+ out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL);
udelay(200);
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
{
int testpin = 0;
struct km_bec_fpga *base =
- (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+ (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
debug("post_hotkeys_pressed: %d\n", !testpin);
int board_early_init_f(void)
{
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
bool cpuwd_flag = false;
{
int ret = 0;
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const unsigned int flashbase = CFG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
disable_tlb(flash_esel);
}
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#include <asm/fsl_law.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+ SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+ SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
/* other application LAW are not used in u-boot */
};
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+ CFG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
0, 2, BOOKE_PAGESZ_128M, 1),
0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
/* QRIO */
- SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_QRIO_BASE, CFG_SYS_QRIO_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 11, BOOKE_PAGESZ_64K, 1),
/* MRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 12, BOOKE_PAGESZ_128M, 1),
/* BFTIC */
* in cpu_init_f, so do not use them here!!.
*/
/* PAXE */
- SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 16, BOOKE_PAGESZ_128M, 1)
};
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
- struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
/* Disable unused MCK1 */
setbits_be32(&gur->ddrclkdr, 2);
gpmc_init();
#if defined(CONFIG_CMD_ONENAND)
enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0],
- CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M);
+ CFG_SYS_ONENAND_BASE, GPMC_SIZE_256M);
#endif
/* Enable the clks & power */
per_clocks_enable();
{
struct onenand_chip *this = mtd->priv;
- this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+ this->base = (void *)CFG_SYS_ONENAND_BASE;
this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
this->chip_probe = s5pc110_chip_probe;
{
struct onenand_chip *this = mtd->priv;
- this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+ this->base = (void *)CFG_SYS_ONENAND_BASE;
this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
this->chip_probe = s5pc210_chip_probe;
setting.cr = SDRAM_BASE_CONF;
setting.mdr = AT91_SDRAMC_MD_SDRAM;
- setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+ setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
/*
* I write here directly in this register, because this
at91_sdram_hw_init();
setting.cr = SDRAM_BASE_CONF | mask;
setting.mdr = AT91_SDRAMC_MD_SDRAM;
- setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+ setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
*/
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
- SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#if defined(CONFIG_SYS_FPGA_BASE)
- SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CFG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+ SET_LAW(CFG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#if defined(CFG_SYS_FPGA_BASE)
+ SET_LAW(CFG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
- SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+ SET_LAW(CFG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
ddr->cs0_config = 0;
ddr->sdram_cfg = 0;
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
+ ddr->cs0_bnds = CFG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_SYS_DDR_MODE;
+ ddr->sdram_interval = CFG_SYS_DDR_INTERVAL;
+ ddr->sdram_cfg_2 = CFG_SYS_DDR_CONFIG_2;
+ ddr->sdram_clk_cntl = CFG_SYS_DDR_CLK_CONTROL;
asm ("sync;isync;msync");
udelay(1000);
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
+ ddr->sdram_cfg = CFG_SYS_DDR_CONFIG;
asm ("sync; isync; msync");
udelay(1000);
}
#endif
-#if defined(CONFIG_SYS_DRAM_TEST)
+#if defined(CFG_SYS_DRAM_TEST)
int testdram(void)
{
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
/*
* Check if boot FLASH isn't max size
*/
- if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
+ if (gd->bd->bi_flashsize < (0 - CFG_SYS_FLASH0)) {
set_lbc_or(0, gd->bd->bi_flashstart |
(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
set_lbc_br(0, gd->bd->bi_flashstart |
/*
* Check if only one FLASH bank is available
*/
- if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
+ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CFG_SYS_FLASH0)) {
set_lbc_or(1, 0);
set_lbc_br(1, 0);
sys_info_t sysinfo;
uint clkdiv;
uint lbc_mhz;
- uint lcrr = CONFIG_SYS_LBC_LCRR;
+ uint lcrr = CFG_SYS_LBC_LCRR;
get_sys_info (&sysinfo);
clkdiv = lbc->lcrr & LCRR_CLKDIV;
/* Fixup FPGA mapping */
val[i++] = 3; /* chip select number */
val[i++] = 0; /* always 0 */
- val[i++] = CONFIG_SYS_FPGA_BASE;
- val[i++] = CONFIG_SYS_FPGA_SIZE;
+ val[i++] = CFG_SYS_FPGA_BASE;
+ val[i++] = CFG_SYS_FPGA_SIZE;
rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
val, i * sizeof(u32), 1);
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
* 0xfc000000 64M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
-#if defined(CONFIG_SYS_FPGA_BASE)
+#if defined(CFG_SYS_FPGA_BASE)
/*
* TLB 4: 1M Non-cacheable, guarded
* 0xc0000000 1M FPGA and NAND
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_FPGA_BASE, CFG_SYS_FPGA_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_1M, 1),
#endif
* (0xcbfc0000 256K LIME GDC MMIO)
* MMIO is relocatable and could be at 0xcbfc0000
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_LIME_BASE, CFG_SYS_LIME_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, CFG_SYS_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
#endif
* DCR
* set proper RC as per specification
*/
- RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
+ RC = (CFG_SYS_CPU_CLK / 1000000) >> 1;
RC = (RC * 15) >> 4;
/* 0x8000 is the faster option */
/* adjust memory start address for LPAE */
if (lpae) {
start[0] -= CFG_SYS_SDRAM_BASE;
- start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
+ start[0] += CFG_SYS_LPAE_SDRAM_BASE;
}
if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
if (prop1 && prop2) {
initrd_start = __be64_to_cpu(*prop1);
initrd_start -= CFG_SYS_SDRAM_BASE;
- initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_start += CFG_SYS_LPAE_SDRAM_BASE;
initrd_start = __cpu_to_be64(initrd_start);
initrd_end = __be64_to_cpu(*prop2);
initrd_end -= CFG_SYS_SDRAM_BASE;
- initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_end += CFG_SYS_LPAE_SDRAM_BASE;
initrd_end = __cpu_to_be64(initrd_end);
err = fdt_delprop(blob, nodeoffset,
if (size) {
*reserve_start -= CFG_SYS_SDRAM_BASE;
*reserve_start +=
- CONFIG_SYS_LPAE_SDRAM_BASE;
+ CFG_SYS_LPAE_SDRAM_BASE;
*reserve_start =
__cpu_to_be64(*reserve_start);
} else {
gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
- tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
+ tca642x_set_inital_state(CFG_SYS_I2C_TCA642X_ADDR, tca642x_init);
return 0;
}
*/
int board_flash_wp_on(void)
{
- if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ if (pca953x_get_val(CFG_SYS_I2C_PCA953X_ADDR0) &
CONFIG_SYS_PCA953X_NVM_WP)
return 1;
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#elif defined(CONFIG_MPC86xx)
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+ volatile immap_t *immap = (immap_t *)CFG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
#endif
default TEXT_BASE
help
The physical start address of boot monitor code (which is the same as
- CONFIG_TEXT_BASE when linking) and the same as CONFIG_SYS_FLASH_BASE
+ CONFIG_TEXT_BASE when linking) and the same as CFG_SYS_FLASH_BASE
when booting from flash.
config SPL_SYS_MONITOR_BASE
return tmp;
}
-#if defined(CONFIG_SYS_BOOTMAPSZ)
- return CONFIG_SYS_BOOTMAPSZ;
+#if defined(CFG_SYS_BOOTMAPSZ)
+ return CFG_SYS_BOOTMAPSZ;
#else
return env_get_bootm_size();
#endif
}
#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
old_bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
+ i2c_set_bus_num(CFG_SYS_RTC_BUS_NUM);
#else
old_bus = I2C_GET_BUS();
- I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM);
+ I2C_SET_BUS(CFG_SYS_RTC_BUS_NUM);
#endif
switch (argc) {
* When multiple buses are present, the list is an array of bus-address
* pairs. The following macros take care of this */
-#if defined(CONFIG_SYS_I2C_NOPROBES)
+#if defined(CFG_SYS_I2C_NOPROBES)
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
static struct
{
uchar bus;
uchar addr;
-} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
+} i2c_no_probes[] = CFG_SYS_I2C_NOPROBES;
#define GET_BUS_NUM i2c_get_bus_num()
#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
#else /* single bus */
-static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
+static uchar i2c_no_probes[] = CFG_SYS_I2C_NOPROBES;
#define GET_BUS_NUM 0
#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
int j;
int addr = -1;
int found = 0;
-#if defined(CONFIG_SYS_I2C_NOPROBES)
+#if defined(CFG_SYS_I2C_NOPROBES)
int k, skip;
unsigned int bus = GET_BUS_NUM;
#endif /* NOPROBES */
if ((0 <= addr) && (j != addr))
continue;
-#if defined(CONFIG_SYS_I2C_NOPROBES)
+#if defined(CFG_SYS_I2C_NOPROBES)
skip = 0;
for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
}
putc ('\n');
-#if defined(CONFIG_SYS_I2C_NOPROBES)
+#if defined(CFG_SYS_I2C_NOPROBES)
puts ("Excluded chip addresses:");
for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
if (COMPARE_BUS(bus,k))
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
int j;
- for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
+ for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
if (i2c_bus[i].next_hop[j].chip == 0)
break;
printf("->%s@0x%2x:%d",
printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
int j;
- for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
+ for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
if (i2c_bus[i].next_hop[j].chip == 0)
break;
printf("->%s@0x%2x:%d",
post_init_f,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_SYS_DRAM_TEST)
+#if defined(CFG_SYS_DRAM_TEST)
testdram,
-#endif /* CONFIG_SYS_DRAM_TEST */
+#endif /* CFG_SYS_DRAM_TEST */
INIT_FUNC_WATCHDOG_RESET
#ifdef CONFIG_POST
* NOTE: Maybe we should add some schedule()? XXX
*/
if (env_get_yesno("flashchecksum") == 1) {
- const uchar *flash_base = (const uchar *)CONFIG_SYS_FLASH_BASE;
+ const uchar *flash_base = (const uchar *)CFG_SYS_FLASH_BASE;
printf(" CRC: %08X", crc32(0,
flash_base,
putc('\n');
/* update start of FLASH memory */
-#ifdef CONFIG_SYS_FLASH_BASE
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#ifdef CFG_SYS_FLASH_BASE
+ bd->bi_flashstart = CFG_SYS_FLASH_BASE;
#endif
/* size of FLASH memory (final value) */
bd->bi_flashsize = flash_size;
#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
/* flash mapped at end of memory map */
bd->bi_flashoffset = CONFIG_TEXT_BASE + flash_size;
-#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
+#elif CONFIG_SYS_MONITOR_BASE == CFG_SYS_FLASH_BASE
bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */
#endif
return 0;
bool "Ensures that CCSR is not relocated"
depends on PPC
help
- If this is defined, then CONFIG_SYS_CCSRBAR_PHYS will be forced to a
+ If this is defined, then CFG_SYS_CCSRBAR_PHYS will be forced to a
value that ensures that CCSR is not relocated.
config TPL_SYS_CCSR_DO_NOT_RELOCATE
config SPL_RELOC_STACK
hex "Address of the start of the stack SPL will use after relocation."
help
- If unspecified, this is equal to CONFIG_SYS_SPL_MALLOC_START. Starting
+ If unspecified, this is equal to CFG_SYS_SPL_MALLOC_START. Starting
address of the malloc pool used in SPL. When this option is set the full
malloc is used in SPL and it is set up by spl_init() and before that, the
simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined.
DECLARE_GLOBAL_DATA_PTR;
DECLARE_BINMAN_MAGIC_SYM;
-#ifndef CONFIG_SYS_UBOOT_START
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#ifndef CFG_SYS_UBOOT_START
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
#endif
u32 *boot_params_ptr = NULL;
spl_image->entry_point = u_boot_pos;
spl_image->load_addr = u_boot_pos;
} else {
- spl_image->entry_point = CONFIG_SYS_UBOOT_START;
+ spl_image->entry_point = CFG_SYS_UBOOT_START;
spl_image->load_addr = CONFIG_TEXT_BASE;
}
spl_image->os = IH_OS_U_BOOT;
}
/*
- * If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's
+ * If a platform does not provide CFG_SYS_UBOOT_START, U-Boot's
* Makefile will set it to 0 and it will end up as the entry point
* here. What it actually means is: use the load address.
*/
unsigned long __weak spl_nor_get_uboot_base(void)
{
- return CONFIG_SYS_UBOOT_BASE;
+ return CFG_SYS_UBOOT_BASE;
}
static int spl_nor_load_image(struct spl_image_info *spl_image,
int err;
/* Read for a header, parse or error out. */
- spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(*header),
+ spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, sizeof(*header),
(void *)header);
if (image_get_magic(header) != IH_MAGIC)
if (err)
return err;
- spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS,
+ spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS,
spl_image->size, (void *)spl_image->load_addr);
/* Read device tree. */
- spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS,
- CONFIG_SYS_SPI_ARGS_SIZE,
+ spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
+ CFG_SYS_SPI_ARGS_SIZE,
(void *)CONFIG_SYS_SPL_ARGS_ADDR);
return 0;
#ifdef CONFIG_SPL_ONENAND_SUPPORT
case BOOT_DEVICE_ONENAND:
info.read = onenand_spl_read_block;
- info.peb_size = CONFIG_SYS_ONENAND_BLOCK_SIZE;
+ info.peb_size = CFG_SYS_ONENAND_BLOCK_SIZE;
break;
#endif
default:
}
#endif
return(spl_parse_image_header(spl_image, bootdev,
- (const struct legacy_img_hdr *)CONFIG_SYS_UBOOT_BASE));
+ (const struct legacy_img_hdr *)CFG_SYS_UBOOT_BASE));
}
SPL_LOAD_IMAGE_METHOD("XIP", 0, BOOT_DEVICE_XIP, spl_xip);
/* this is a weak define that we are overriding */
int board_mmc_getcd(struct mmc *mmc)
{
- return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN);
+ return !at91_get_gpio_value(CFG_SYS_MMC_CD_PIN);
}
#endif
/* SD/MMC card */
#define CONFIG_GENERIC_ATMEL_MCI 1
#define CONFIG_ATMEL_MCI_PORTB 1 /* Atmel XE-EK uses port B */
-#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9
+#define CFG_SYS_MMC_CD_PIN AT91_PIN_PC9
#define CONFIG_CMD_MMC 1
void flash_cmd_reset(flash_info_t *info)
{
/*
- * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
+ * FLASH at address CFG_SYS_FLASH_BASE is a Spansion chip and
* needs the Spansion type reset commands. The other flash chip
* is located behind a FPGA (Xilinx DS617) and needs the Intel type
* reset command.
*/
- if (info->start[0] == CONFIG_SYS_FLASH_BASE)
+ if (info->start[0] == CFG_SYS_FLASH_BASE)
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
else
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
Davinci special defines
=======================
-CONFIG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode
+CFG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode
need a "NOR Boot Configuration Word" stored
in the NOR Flash. This define adds this.
More Info about this, see:
CONFIG_USB_OHCI_NEW: enable the new OHCI driver
- CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI
+ CFG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI
registers
CONFIG_SYS_USB_OHCI_SLOT_NAME: slot name
3) TLB entry for the stack during AS1
Location : Lable "create_init_ram_area"
TLB Entry : 14
- EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+ EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution
Location : cpu_init_early_f
TLB Entry : 13
- EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+ EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
Properties : 1M, AS1, I, G
5) Invalidate unproctected TLB Entries
8) Update Flash's TLB entry
Location : Board_init_r
TLB entry : Search from TLB entries
- EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+ EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
Properties : Board specific size, AS0, I, G, IPROT
Location : Label "_start"
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
#if defined(CONFIG_NXP_ESBC)
- EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+ EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
Properties : 1M, AS1, I, G, IPROT
#else
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
Location : Label "create_init_ram_area"
TLB Entry : 15
#if defined(CONFIG_NXP_ESBC)
- EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+ EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
Properties : 1M, AS1, I, G, IPROT
#else
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
3) TLB entry for the stack during AS1
Location : Lable "create_init_ram_area"
TLB Entry : 14
- EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+ EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution
Location : cpu_init_early_f
TLB Entry : 13
- EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+ EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
Properties : 1M, AS1, I, G
5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
12) Update Flash's TLB entry
Location : Board_init_r
TLB entry : Search from TLB entries
- EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+ EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
Properties : Board specific size, AS0, I, G, IPROT
chip.IO_ADDR_R = ...;
chip.IO_ADDR_W = ...;
- if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
+ if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL))
error out
/*
setenv sout serial_scc; setenv baudrate 38400
After that press 'enter' at the SCC console. Note that baudrates <38400
-are not allowed on LWMON with watchdog enabled (see CONFIG_SYS_BAUDRATE_TABLE in
+are not allowed on LWMON with watchdog enabled (see CFG_SYS_BAUDRATE_TABLE in
include/configs/lwmon.h).
Other options, generally set inside include/configs/<boardname>.h, they may
apply to one or more cpu for the ColdFire family:
-CONFIG_SYS_MBAR:
+CFG_SYS_MBAR:
defines the base address of the MCF5272 configuration registers
-CONFIG_SYS_SCR:
+CFG_SYS_SCR:
defines the contents of the System Configuration Register
-CONFIG_SYS_SPR:
+CFG_SYS_SPR:
defines the contents of the System Protection Register
-CONFIG_SYS_MFD:
+CFG_SYS_MFD:
defines the PLL Multiplication Factor Divider
(see table 9-4 of MCF user manual)
-CONFIG_SYS_RFD:
+CFG_SYS_RFD:
defines the PLL Reduce Frequency Devider
(see table 9-4 of MCF user manual)
CONFIG_SYS_CSx_BASE:
if set to 0 chip select x is read/write else chip select is read only
CONFIG_SYS_CSx_WS:
defines the number of wait states of chip select x
-CONFIG_SYS_CACHE_ICACR:
+CFG_SYS_CACHE_ICACR:
cache-related registers config
-CONFIG_SYS_CACHE_DCACR:
+CFG_SYS_CACHE_DCACR:
cache-related registers config
CONFIG_SYS_CACHE_ACRX:
cache-related registers config
these options are used.
CONFIG_MCFUART:
defines enabling of ColdFire UART driver
-CONFIG_SYS_UART_PORT:
+CFG_SYS_UART_PORT:
defines the UART port to be used (only a single UART can be actually enabled)
-CONFIG_SYS_SBFHDR_SIZE:
+CFG_SYS_SBFHDR_SIZE:
size of the prepended SBF header, if any
Maintainers should submit patches switching over to using CONFIG_DM_I2C and
other base driver model options in time for inclusion in the 2021.10 release.
-CONFIG_SYS_TIMER_RATE and CONFIG_SYS_TIMER_COUNTER
+CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER
--------------------------------------------------
Deadline: 2023.01
8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32),
10(MOBILE_WHITEBAR_64)
samsung,h-sync-polarity: Horizontal Sync polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,v-sync-polarity: Vertical Sync polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,interlaced: Progressive if 0, else Interlaced
samsung,color-space: input video data format
COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
samsung,vl-height: Height of display area in mm
samsung,vl-clkp: Clock polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-oep: Output Enable polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-hsp: Horizontal Sync polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-vsp: Vertical Sync polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-dp: Data polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-cmd-allow-len: Wait end of frame
samsung,winid: Window number on which data is to be displayed
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.
-1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+1.2 CFG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
This option should be enabled for boards having a SYS_ON_OFF_CTL signal
connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
reference designs.
for use by the bootm command. See also "bootm_size"
environment variable. Address defined by "bootm_low" is
also the base of the initial memory mapping for the Linux
- kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
+ kernel -- see the description of CFG_SYS_BOOTMAPSZ and
bootm_mapsize.
bootm_mapsize
This variable is given as a hexadecimal number and it
defines the size of the memory region starting at base
address bootm_low that is accessible by the Linux kernel
- during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used
+ during early boot. If unset, CFG_SYS_BOOTMAPSZ is used
as the default value if it is defined, and bootm_size is
used otherwise.
is usually what you want since it allows for
maximum initrd size. If for some reason you want to
make sure that the initrd image is loaded below the
- CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
+ CFG_SYS_BOOTMAPSZ limit, you can set this environment
variable to a value of "no" or "off" or "0".
Alternatively, you can set it to a maximum upper
address to use (U-Boot will still check that it
bool "Boot counter on I2C device"
help
Enable support for the bootcounter on an i2c (like RTC) device.
- CONFIG_SYS_I2C_RTC_ADDR = i2c chip address
+ CFG_SYS_I2C_RTC_ADDR = i2c chip address
CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
the bootcounter.
buf[0] = BC_MAGIC;
buf[1] = (a & 0xff);
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+ ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
CONFIG_BOOTCOUNT_ALEN, buf, 2);
if (ret != 0)
puts("Error writing bootcount\n");
unsigned char buf[3];
int ret;
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+ ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
CONFIG_BOOTCOUNT_ALEN, buf, 2);
if (ret != 0) {
puts("Error loading bootcount\n");
static ulong at91_slow_clk_get_rate(struct clk *clk)
{
- return CONFIG_SYS_AT91_SLOW_CLOCK;
+ return CFG_SYS_AT91_SLOW_CLOCK;
}
static struct clk_ops at91_slow_clk_ops = {
help
Enable driver model in SPL. You will need to provide a
suitable malloc() implementation. If you are not using the
- full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+ full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. In that case you
must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
help
Enable driver model in TPL. You will need to provide a
suitable malloc() implementation. If you are not using the
- full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+ full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
consider using CONFIG_TPL_SYS_MALLOC_SIMPLE. In that case you
must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
help
Enable driver model in VPL. You will need to provide a
suitable malloc() implementation. If you are not using the
- full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+ full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
consider using CONFIG_SPL_SYS_MALLOC_SIMPLE.
config DM_WARN
/*
* CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
- * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
+ * of DDR controllers. It is the same as CFG_SYS_DDR_SDRAM_BASE for
* all Power SoCs. But it could be different for ARM SoCs. For example,
* fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
* 0x00_8000_0000 ~ 0x00_ffff_ffff
#ifdef CONFIG_MPC83xx
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE
#else
-#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE
#endif
#endif
#define CONFIG_FPGA_DELAY()
#endif
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
#endif
static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
#define CONFIG_FPGA_DELAY()
#endif
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */
#endif
static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
ts = get_timer(0); /* get current time */
do {
CONFIG_FPGA_DELAY();
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
/* check the time */
puts("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
#define CONFIG_FPGA_DELAY()
#endif
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
/* Now wait for INIT and BUSY to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
CONFIG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for BUSY to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
CONFIG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
ret_val = FPGA_FAIL;
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
return FPGA_FAIL;
}
/* Now wait for INIT to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
return FPGA_FAIL;
}
putc ('*');
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
ret_val = FPGA_FAIL;
break;
#define CONFIG_FPGA_DELAY()
#endif
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
/* Now wait for INIT and BUSY to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
CONFIG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for BUSY to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
CONFIG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
ret_val = FPGA_FAIL;
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
if (*fn->abort)
(*fn->abort) (cookie);
/* Now wait for INIT to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
if (*fn->abort)
(*fn->abort) (cookie);
putc ('*');
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
ret_val = FPGA_FAIL;
break;
* which yields 11.44 mS. So let's make it bigger in order to handle
* an XC2V1000, if anyone can ever get ahold of one.
*/
-#ifndef CONFIG_SYS_FPGA_WAIT_INIT
-#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
+#ifndef CFG_SYS_FPGA_WAIT_INIT
+#define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
#endif
/*
* This is normally not necessary since for most reasonable configuration
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/
-#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
-#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
+#ifndef CFG_SYS_FPGA_WAIT_BUSY
+#define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
#endif
/* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written.
*/
-#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
-#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
+#ifndef CFG_SYS_FPGA_WAIT_CONFIG
+#define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
#endif
static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
udelay(10);
ts = get_timer(0);
do {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
- __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
ts = get_timer(0);
do {
CONFIG_FPGA_DELAY();
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
- __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
break;
}
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) {
printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
- __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
+ __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG);
(*fn->abort)(cookie);
ret_val = FPGA_FAIL;
break;
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer(0);
while ((*fn->busy)(cookie)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) {
printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
__func__, __LINE__,
- CONFIG_SYS_FPGA_WAIT_BUSY);
+ CFG_SYS_FPGA_WAIT_BUSY);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
#ifndef CONFIG_SYS_FPGA_PROG_TIME
/* Polling the PCAP_INIT status for Reset */
ts = get_timer(0);
while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for INIT to clear\n",
__func__);
return FPGA_FAIL;
ts = get_timer(0);
while (!(readl(&devcfg_base->status) &
DEVCFG_STATUS_PCFG_INIT)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for INIT to set\n",
__func__);
return FPGA_FAIL;
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
#include <pca953x.h>
/* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_PCA953X_ADDR
-#define CONFIG_SYS_I2C_PCA953X_ADDR (~0)
+#ifndef CFG_SYS_I2C_PCA953X_ADDR
+#define CFG_SYS_I2C_PCA953X_ADDR (~0)
#endif
enum {
PCA953X_CMD_INVERT,
};
-#ifdef CONFIG_SYS_I2C_PCA953X_WIDTH
+#ifdef CFG_SYS_I2C_PCA953X_WIDTH
struct pca953x_chip_ngpio {
uint8_t chip;
uint8_t ngpio;
};
static struct pca953x_chip_ngpio pca953x_chip_ngpios[] =
- CONFIG_SYS_I2C_PCA953X_WIDTH;
+ CFG_SYS_I2C_PCA953X_WIDTH;
/*
* Determine the number of GPIO pins supported. If we don't know we assume
static int do_pca953x(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
+ static uint8_t chip = CFG_SYS_I2C_PCA953X_ADDR;
int ret = CMD_RET_USAGE, val;
ulong ul_arg2 = 0;
ulong ul_arg3 = 0;
int ret;
org_bus_num = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+ i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM);
if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) {
printf("Could not read before writing\n");
int ret = 0;
org_bus_num = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+ i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM);
if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) {
ret = -1;
goto error;
static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR;
+ static uchar chip = CFG_SYS_I2C_TCA642X_ADDR;
int ret = CMD_RET_USAGE, val;
int gpio_bank = 0;
uint8_t bank_shift;
psc = 2;
/* SCLL + SCLH */
- div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
+ div = (CFG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_M68K
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
+#define CONFIG_SYS_IMMR CFG_SYS_MBAR
#endif
#if !CONFIG_IS_ENABLED(DM_I2C)
#if !defined(CONFIG_SYS_I2C_DIRECT_BUS)
struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] =
- CONFIG_SYS_I2C_BUSES;
+ CFG_SYS_I2C_BUSES;
#endif
DECLARE_GLOBAL_DATA_PTR;
/* Connect requested bus if behind muxes */
if (i2c_bus_tmp->next_hop[0].chip != 0) {
/* Set all muxes along the path to that bus */
- for (i = 0; i < CONFIG_SYS_I2C_MAX_HOPS; i++) {
+ for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) {
int ret;
if (i2c_bus_tmp->next_hop[i].chip == 0)
/* Disconnect current bus (turn off muxes if any) */
if ((i2c_bus_tmp->next_hop[0].chip != 0) &&
(I2C_ADAP->init_done != 0)) {
- i = CONFIG_SYS_I2C_MAX_HOPS;
+ i = CFG_SYS_I2C_MAX_HOPS;
do {
uint8_t chip;
int ret;
#define DEF_DEVICE(num) \
{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
-static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
+static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = {
#ifdef CONFIG_SYS_I2C_BASE0
DEF_DEVICE(0),
#endif
#endif /* CONFIG_DM_I2C */
/*
- * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
+ * On SUNXI, we get CFG_SYS_TCLK from this include, so we want to
* always have it.
*/
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_ARCH_SUNXI)
static uint twsi_calc_freq(const int n, const int m)
{
#ifdef CONFIG_ARCH_SUNXI
- return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
+ return CFG_SYS_TCLK / (10 * (m + 1) * (1 << n));
#else
- return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
+ return CFG_SYS_TCLK / (10 * (m + 1) * (2 << n));
#endif
}
#define VF610_I2C_REGSHIFT 0
#define I2C_EARLY_INIT_INDEX 0
-#ifdef CONFIG_SYS_I2C_IFDR_DIV
-#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
+#ifdef CFG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE CFG_SYS_I2C_IFDR_DIV
#else
#define I2C_IFDR_DIV_CONSERVATIVE 0x7e
#endif
struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"cs0",
-#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
- CONFIG_SYS_CSPR0,
-#ifdef CONFIG_SYS_CSPR0_EXT
- CONFIG_SYS_CSPR0_EXT,
+#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0)
+ CFG_SYS_CSPR0,
+#ifdef CFG_SYS_CSPR0_EXT
+ CFG_SYS_CSPR0_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK0
- CONFIG_SYS_AMASK0,
+#ifdef CFG_SYS_AMASK0
+ CFG_SYS_AMASK0,
#else
0,
#endif
- CONFIG_SYS_CSOR0,
+ CFG_SYS_CSOR0,
{
- CONFIG_SYS_CS0_FTIM0,
- CONFIG_SYS_CS0_FTIM1,
- CONFIG_SYS_CS0_FTIM2,
- CONFIG_SYS_CS0_FTIM3,
+ CFG_SYS_CS0_FTIM0,
+ CFG_SYS_CS0_FTIM1,
+ CFG_SYS_CS0_FTIM2,
+ CFG_SYS_CS0_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR0_EXT
- CONFIG_SYS_CSOR0_EXT,
+#ifdef CFG_SYS_CSOR0_EXT
+ CFG_SYS_CSOR0_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR0_FINAL
- CONFIG_SYS_CSPR0_FINAL,
+#ifdef CFG_SYS_CSPR0_FINAL
+ CFG_SYS_CSPR0_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK0_FINAL
- CONFIG_SYS_AMASK0_FINAL,
+#ifdef CFG_SYS_AMASK0_FINAL
+ CFG_SYS_AMASK0_FINAL,
#else
0,
#endif
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2
{
"cs1",
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
- CONFIG_SYS_CSPR1,
-#ifdef CONFIG_SYS_CSPR1_EXT
- CONFIG_SYS_CSPR1_EXT,
+#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1)
+ CFG_SYS_CSPR1,
+#ifdef CFG_SYS_CSPR1_EXT
+ CFG_SYS_CSPR1_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK1
- CONFIG_SYS_AMASK1,
+#ifdef CFG_SYS_AMASK1
+ CFG_SYS_AMASK1,
#else
0,
#endif
- CONFIG_SYS_CSOR1,
+ CFG_SYS_CSOR1,
{
- CONFIG_SYS_CS1_FTIM0,
- CONFIG_SYS_CS1_FTIM1,
- CONFIG_SYS_CS1_FTIM2,
- CONFIG_SYS_CS1_FTIM3,
+ CFG_SYS_CS1_FTIM0,
+ CFG_SYS_CS1_FTIM1,
+ CFG_SYS_CS1_FTIM2,
+ CFG_SYS_CS1_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR1_EXT
- CONFIG_SYS_CSOR1_EXT,
+#ifdef CFG_SYS_CSOR1_EXT
+ CFG_SYS_CSOR1_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR1_FINAL
- CONFIG_SYS_CSPR1_FINAL,
+#ifdef CFG_SYS_CSPR1_FINAL
+ CFG_SYS_CSPR1_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK1_FINAL
- CONFIG_SYS_AMASK1_FINAL,
+#ifdef CFG_SYS_AMASK1_FINAL
+ CFG_SYS_AMASK1_FINAL,
#else
0,
#endif
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3
{
"cs2",
-#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
- CONFIG_SYS_CSPR2,
-#ifdef CONFIG_SYS_CSPR2_EXT
- CONFIG_SYS_CSPR2_EXT,
+#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2)
+ CFG_SYS_CSPR2,
+#ifdef CFG_SYS_CSPR2_EXT
+ CFG_SYS_CSPR2_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK2
- CONFIG_SYS_AMASK2,
+#ifdef CFG_SYS_AMASK2
+ CFG_SYS_AMASK2,
#else
0,
#endif
- CONFIG_SYS_CSOR2,
+ CFG_SYS_CSOR2,
{
- CONFIG_SYS_CS2_FTIM0,
- CONFIG_SYS_CS2_FTIM1,
- CONFIG_SYS_CS2_FTIM2,
- CONFIG_SYS_CS2_FTIM3,
+ CFG_SYS_CS2_FTIM0,
+ CFG_SYS_CS2_FTIM1,
+ CFG_SYS_CS2_FTIM2,
+ CFG_SYS_CS2_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR2_EXT
- CONFIG_SYS_CSOR2_EXT,
+#ifdef CFG_SYS_CSOR2_EXT
+ CFG_SYS_CSOR2_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR2_FINAL
- CONFIG_SYS_CSPR2_FINAL,
+#ifdef CFG_SYS_CSPR2_FINAL
+ CFG_SYS_CSPR2_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK2_FINAL
- CONFIG_SYS_AMASK2_FINAL,
+#ifdef CFG_SYS_AMASK2_FINAL
+ CFG_SYS_AMASK2_FINAL,
#else
0,
#endif
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4
{
"cs3",
-#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
- CONFIG_SYS_CSPR3,
-#ifdef CONFIG_SYS_CSPR3_EXT
- CONFIG_SYS_CSPR3_EXT,
+#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3)
+ CFG_SYS_CSPR3,
+#ifdef CFG_SYS_CSPR3_EXT
+ CFG_SYS_CSPR3_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK3
- CONFIG_SYS_AMASK3,
+#ifdef CFG_SYS_AMASK3
+ CFG_SYS_AMASK3,
#else
0,
#endif
- CONFIG_SYS_CSOR3,
+ CFG_SYS_CSOR3,
{
- CONFIG_SYS_CS3_FTIM0,
- CONFIG_SYS_CS3_FTIM1,
- CONFIG_SYS_CS3_FTIM2,
- CONFIG_SYS_CS3_FTIM3,
+ CFG_SYS_CS3_FTIM0,
+ CFG_SYS_CS3_FTIM1,
+ CFG_SYS_CS3_FTIM2,
+ CFG_SYS_CS3_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR3_EXT
- CONFIG_SYS_CSOR3_EXT,
+#ifdef CFG_SYS_CSOR3_EXT
+ CFG_SYS_CSOR3_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR3_FINAL
- CONFIG_SYS_CSPR3_FINAL,
+#ifdef CFG_SYS_CSPR3_FINAL
+ CFG_SYS_CSPR3_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK3_FINAL
- CONFIG_SYS_AMASK3_FINAL,
+#ifdef CFG_SYS_AMASK3_FINAL
+ CFG_SYS_AMASK3_FINAL,
#else
0,
#endif
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5
{
"cs4",
-#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
- CONFIG_SYS_CSPR4,
-#ifdef CONFIG_SYS_CSPR4_EXT
- CONFIG_SYS_CSPR4_EXT,
+#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4)
+ CFG_SYS_CSPR4,
+#ifdef CFG_SYS_CSPR4_EXT
+ CFG_SYS_CSPR4_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK4
- CONFIG_SYS_AMASK4,
+#ifdef CFG_SYS_AMASK4
+ CFG_SYS_AMASK4,
#else
0,
#endif
- CONFIG_SYS_CSOR4,
+ CFG_SYS_CSOR4,
{
- CONFIG_SYS_CS4_FTIM0,
- CONFIG_SYS_CS4_FTIM1,
- CONFIG_SYS_CS4_FTIM2,
- CONFIG_SYS_CS4_FTIM3,
+ CFG_SYS_CS4_FTIM0,
+ CFG_SYS_CS4_FTIM1,
+ CFG_SYS_CS4_FTIM2,
+ CFG_SYS_CS4_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR4_EXT
- CONFIG_SYS_CSOR4_EXT,
+#ifdef CFG_SYS_CSOR4_EXT
+ CFG_SYS_CSOR4_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR4_FINAL
- CONFIG_SYS_CSPR4_FINAL,
+#ifdef CFG_SYS_CSPR4_FINAL
+ CFG_SYS_CSPR4_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK4_FINAL
- CONFIG_SYS_AMASK4_FINAL,
+#ifdef CFG_SYS_AMASK4_FINAL
+ CFG_SYS_AMASK4_FINAL,
#else
0,
#endif
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7
{
"cs6",
-#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
- CONFIG_SYS_CSPR6,
-#ifdef CONFIG_SYS_CSPR6_EXT
- CONFIG_SYS_CSPR6_EXT,
+#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6)
+ CFG_SYS_CSPR6,
+#ifdef CFG_SYS_CSPR6_EXT
+ CFG_SYS_CSPR6_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK6
- CONFIG_SYS_AMASK6,
+#ifdef CFG_SYS_AMASK6
+ CFG_SYS_AMASK6,
#else
0,
#endif
- CONFIG_SYS_CSOR6,
+ CFG_SYS_CSOR6,
{
- CONFIG_SYS_CS6_FTIM0,
- CONFIG_SYS_CS6_FTIM1,
- CONFIG_SYS_CS6_FTIM2,
- CONFIG_SYS_CS6_FTIM3,
+ CFG_SYS_CS6_FTIM0,
+ CFG_SYS_CS6_FTIM1,
+ CFG_SYS_CS6_FTIM2,
+ CFG_SYS_CS6_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR6_EXT
- CONFIG_SYS_CSOR6_EXT,
+#ifdef CFG_SYS_CSOR6_EXT
+ CFG_SYS_CSOR6_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR6_FINAL
- CONFIG_SYS_CSPR6_FINAL,
+#ifdef CFG_SYS_CSPR6_FINAL
+ CFG_SYS_CSPR6_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK6_FINAL
- CONFIG_SYS_AMASK6_FINAL,
+#ifdef CFG_SYS_AMASK6_FINAL
+ CFG_SYS_AMASK6_FINAL,
#else
0,
#endif
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8
{
"cs7",
-#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
- CONFIG_SYS_CSPR7,
-#ifdef CONFIG_SYS_CSPR7_EXT
- CONFIG_SYS_CSPR7_EXT,
+#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7)
+ CFG_SYS_CSPR7,
+#ifdef CFG_SYS_CSPR7_EXT
+ CFG_SYS_CSPR7_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK7
- CONFIG_SYS_AMASK7,
+#ifdef CFG_SYS_AMASK7
+ CFG_SYS_AMASK7,
#else
0,
#endif
- CONFIG_SYS_CSOR7,
-#ifdef CONFIG_SYS_CSOR7_EXT
- CONFIG_SYS_CSOR7_EXT,
+ CFG_SYS_CSOR7,
+#ifdef CFG_SYS_CSOR7_EXT
+ CFG_SYS_CSOR7_EXT,
#else
0,
#endif
{
- CONFIG_SYS_CS7_FTIM0,
- CONFIG_SYS_CS7_FTIM1,
- CONFIG_SYS_CS7_FTIM2,
- CONFIG_SYS_CS7_FTIM3,
+ CFG_SYS_CS7_FTIM0,
+ CFG_SYS_CS7_FTIM1,
+ CFG_SYS_CS7_FTIM2,
+ CFG_SYS_CS7_FTIM3,
},
-#ifdef CONFIG_SYS_CSPR7_FINAL
- CONFIG_SYS_CSPR7_FINAL,
+#ifdef CFG_SYS_CSPR7_FINAL
+ CFG_SYS_CSPR7_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK7_FINAL
- CONFIG_SYS_AMASK7_FINAL,
+#ifdef CFG_SYS_AMASK7_FINAL
+ CFG_SYS_AMASK7_FINAL,
#else
0,
#endif
#else
void init_early_memctl_regs(void)
{
-#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
- set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
- set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
- set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
- set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
+#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0)
+ set_ifc_ftim(IFC_CS0, IFC_FTIM0, CFG_SYS_CS0_FTIM0);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM1, CFG_SYS_CS0_FTIM1);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM2, CFG_SYS_CS0_FTIM2);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM3, CFG_SYS_CS0_FTIM3);
#ifndef CONFIG_A003399_NOR_WORKAROUND
-#ifdef CONFIG_SYS_CSPR0_EXT
- set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
+#ifdef CFG_SYS_CSPR0_EXT
+ set_ifc_cspr_ext(IFC_CS0, CFG_SYS_CSPR0_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR0_EXT
- set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+#ifdef CFG_SYS_CSOR0_EXT
+ set_ifc_csor_ext(IFC_CS0, CFG_SYS_CSOR0_EXT);
#endif
- set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
- set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
- set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+ set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0);
+ set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0);
+ set_ifc_csor(IFC_CS0, CFG_SYS_CSOR0);
#endif
#endif
-#ifdef CONFIG_SYS_CSPR1_EXT
- set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
+#ifdef CFG_SYS_CSPR1_EXT
+ set_ifc_cspr_ext(IFC_CS1, CFG_SYS_CSPR1_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR1_EXT
- set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+#ifdef CFG_SYS_CSOR1_EXT
+ set_ifc_csor_ext(IFC_CS1, CFG_SYS_CSOR1_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
- set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
- set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
- set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
- set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
+#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1)
+ set_ifc_ftim(IFC_CS1, IFC_FTIM0, CFG_SYS_CS1_FTIM0);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM1, CFG_SYS_CS1_FTIM1);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM2, CFG_SYS_CS1_FTIM2);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM3, CFG_SYS_CS1_FTIM3);
- set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
- set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
- set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+ set_ifc_csor(IFC_CS1, CFG_SYS_CSOR1);
+ set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1);
+ set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1);
#endif
-#ifdef CONFIG_SYS_CSPR2_EXT
- set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
+#ifdef CFG_SYS_CSPR2_EXT
+ set_ifc_cspr_ext(IFC_CS2, CFG_SYS_CSPR2_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR2_EXT
- set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
+#ifdef CFG_SYS_CSOR2_EXT
+ set_ifc_csor_ext(IFC_CS2, CFG_SYS_CSOR2_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
- set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
- set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
- set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
- set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
+#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2)
+ set_ifc_ftim(IFC_CS2, IFC_FTIM0, CFG_SYS_CS2_FTIM0);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM1, CFG_SYS_CS2_FTIM1);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM2, CFG_SYS_CS2_FTIM2);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM3, CFG_SYS_CS2_FTIM3);
- set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
- set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
- set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
+ set_ifc_csor(IFC_CS2, CFG_SYS_CSOR2);
+ set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2);
+ set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2);
#endif
-#ifdef CONFIG_SYS_CSPR3_EXT
- set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
+#ifdef CFG_SYS_CSPR3_EXT
+ set_ifc_cspr_ext(IFC_CS3, CFG_SYS_CSPR3_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR3_EXT
- set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
+#ifdef CFG_SYS_CSOR3_EXT
+ set_ifc_csor_ext(IFC_CS3, CFG_SYS_CSOR3_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
- set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
- set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
- set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
- set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
+#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3)
+ set_ifc_ftim(IFC_CS3, IFC_FTIM0, CFG_SYS_CS3_FTIM0);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM1, CFG_SYS_CS3_FTIM1);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM2, CFG_SYS_CS3_FTIM2);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM3, CFG_SYS_CS3_FTIM3);
- set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
- set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
- set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
+ set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3);
+ set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3);
+ set_ifc_csor(IFC_CS3, CFG_SYS_CSOR3);
#endif
-#ifdef CONFIG_SYS_CSPR4_EXT
- set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#ifdef CFG_SYS_CSPR4_EXT
+ set_ifc_cspr_ext(IFC_CS4, CFG_SYS_CSPR4_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR4_EXT
- set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
+#ifdef CFG_SYS_CSOR4_EXT
+ set_ifc_csor_ext(IFC_CS4, CFG_SYS_CSOR4_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
- set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
- set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
- set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
- set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4)
+ set_ifc_ftim(IFC_CS4, IFC_FTIM0, CFG_SYS_CS4_FTIM0);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM1, CFG_SYS_CS4_FTIM1);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM2, CFG_SYS_CS4_FTIM2);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM3, CFG_SYS_CS4_FTIM3);
- set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
- set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
- set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+ set_ifc_cspr(IFC_CS4, CFG_SYS_CSPR4);
+ set_ifc_amask(IFC_CS4, CFG_SYS_AMASK4);
+ set_ifc_csor(IFC_CS4, CFG_SYS_CSOR4);
#endif
#ifdef CONFIG_SYS_CSPR5_EXT
set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
#endif
-#ifdef CONFIG_SYS_CSPR6_EXT
- set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#ifdef CFG_SYS_CSPR6_EXT
+ set_ifc_cspr_ext(IFC_CS6, CFG_SYS_CSPR6_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR6_EXT
- set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
+#ifdef CFG_SYS_CSOR6_EXT
+ set_ifc_csor_ext(IFC_CS6, CFG_SYS_CSOR6_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
- set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
- set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
- set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
- set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6)
+ set_ifc_ftim(IFC_CS6, IFC_FTIM0, CFG_SYS_CS6_FTIM0);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM1, CFG_SYS_CS6_FTIM1);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM2, CFG_SYS_CS6_FTIM2);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM3, CFG_SYS_CS6_FTIM3);
- set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
- set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
- set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+ set_ifc_cspr(IFC_CS6, CFG_SYS_CSPR6);
+ set_ifc_amask(IFC_CS6, CFG_SYS_AMASK6);
+ set_ifc_csor(IFC_CS6, CFG_SYS_CSOR6);
#endif
-#ifdef CONFIG_SYS_CSPR7_EXT
- set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#ifdef CFG_SYS_CSPR7_EXT
+ set_ifc_cspr_ext(IFC_CS7, CFG_SYS_CSPR7_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR7_EXT
- set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
+#ifdef CFG_SYS_CSOR7_EXT
+ set_ifc_csor_ext(IFC_CS7, CFG_SYS_CSOR7_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
- set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
- set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
- set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
- set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7)
+ set_ifc_ftim(IFC_CS7, IFC_FTIM0, CFG_SYS_CS7_FTIM0);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM1, CFG_SYS_CS7_FTIM1);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM2, CFG_SYS_CS7_FTIM2);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM3, CFG_SYS_CS7_FTIM3);
- set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
- set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
- set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+ set_ifc_cspr(IFC_CS7, CFG_SYS_CSPR7);
+ set_ifc_amask(IFC_CS7, CFG_SYS_AMASK7);
+ set_ifc_csor(IFC_CS7, CFG_SYS_CSOR7);
#endif
}
void init_final_memctl_regs(void)
{
-#ifdef CONFIG_SYS_CSPR0_FINAL
- set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
+#ifdef CFG_SYS_CSPR0_FINAL
+ set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0_FINAL);
#endif
-#ifdef CONFIG_SYS_AMASK0_FINAL
- set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+#ifdef CFG_SYS_AMASK0_FINAL
+ set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0);
#endif
-#ifdef CONFIG_SYS_CSPR1_FINAL
- set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
+#ifdef CFG_SYS_CSPR1_FINAL
+ set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1_FINAL);
#endif
-#ifdef CONFIG_SYS_AMASK1_FINAL
- set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
+#ifdef CFG_SYS_AMASK1_FINAL
+ set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1_FINAL);
#endif
-#ifdef CONFIG_SYS_CSPR2_FINAL
- set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
+#ifdef CFG_SYS_CSPR2_FINAL
+ set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2_FINAL);
#endif
-#ifdef CONFIG_SYS_AMASK2_FINAL
- set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+#ifdef CFG_SYS_AMASK2_FINAL
+ set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2);
#endif
-#ifdef CONFIG_SYS_CSPR3_FINAL
- set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
+#ifdef CFG_SYS_CSPR3_FINAL
+ set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3_FINAL);
#endif
-#ifdef CONFIG_SYS_AMASK3_FINAL
- set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+#ifdef CFG_SYS_AMASK3_FINAL
+ set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3);
#endif
}
#endif
#endif
#include <fsl_qbman.h>
-#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
-#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
+#define MAX_BPORTALS (CFG_SYS_BMAN_CINH_SIZE / CFG_SYS_BMAN_SP_CINH_SIZE)
+#define MAX_QPORTALS (CFG_SYS_QMAN_CINH_SIZE / CFG_SYS_QMAN_SP_CINH_SIZE)
void setup_qbman_portals(void)
{
- void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
- CONFIG_SYS_BMAN_SWP_ISDR_REG;
- void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
- CONFIG_SYS_QMAN_SWP_ISDR_REG;
+ void __iomem *bpaddr = (void *)CFG_SYS_BMAN_CINH_BASE +
+ CFG_SYS_BMAN_SWP_ISDR_REG;
+ void __iomem *qpaddr = (void *)CFG_SYS_QMAN_CINH_BASE +
+ CFG_SYS_QMAN_SWP_ISDR_REG;
struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
#ifdef CONFIG_PHYS_64BIT
- out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+ out_be32(&qman->qcsp_bare, (u32)(CFG_SYS_QMAN_MEM_PHYS >> 32));
#endif
- out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+ out_be32(&qman->qcsp_bar, (u32)CFG_SYS_QMAN_MEM_PHYS);
#ifdef CONFIG_FSL_CORENET
int i;
- for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+ for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
u8 sdest = qp_info[i].sdest;
u16 fliodn = qp_info[i].fliodn;
u16 dliodn = qp_info[i].dliodn;
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
int i;
- for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+ for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
u8 sdest = qp_info[i].sdest;
u16 ficid = qp_info[i].ficid;
u16 dicid = qp_info[i].dicid;
#endif
/* Change default state of BMan ISDR portals to all 1s */
- inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
- CONFIG_SYS_BMAN_SP_CINH_SIZE);
- inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
- CONFIG_SYS_QMAN_SP_CINH_SIZE);
+ inhibit_portals(bpaddr, CFG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
+ CFG_SYS_BMAN_SP_CINH_SIZE);
+ inhibit_portals(qpaddr, CFG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
+ CFG_SYS_QMAN_SP_CINH_SIZE);
}
void inhibit_portals(void __iomem *addr, int max_portals,
static u32 get_sec_mon_state(void)
{
struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
+ (CFG_SYS_SEC_MON_ADDR);
return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK;
}
u32 sts;
int timeout = 10;
struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
+ (CFG_SYS_SEC_MON_ADDR);
sts = get_sec_mon_state();
u32 sts;
int timeout = 10;
struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
+ (CFG_SYS_SEC_MON_ADDR);
printf("SEC_MON state transitioning to Soft Fail.\n");
sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
#include <mmc.h>
#include <malloc.h>
-#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS
+#ifndef CFG_SYS_MMC_U_BOOT_OFFS
extern uchar mmc_u_boot_offs[];
#endif
}
#ifdef CONFIG_FSL_CORENET
- offset = CONFIG_SYS_MMC_U_BOOT_OFFS;
+ offset = CFG_SYS_MMC_U_BOOT_OFFS;
#else
sector = 0;
again:
val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i);
offset = (offset << 8) + val;
}
-#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS
+#ifndef CFG_SYS_MMC_U_BOOT_OFFS
offset += (ulong)&mmc_u_boot_offs - CONFIG_SPL_TEXT_BASE;
#else
- offset += CONFIG_SYS_MMC_U_BOOT_OFFS;
+ offset += CFG_SYS_MMC_U_BOOT_OFFS;
#endif
#endif
/*
* Load U-Boot image from mmc into RAM
*/
- code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
+ code_len = CFG_SYS_MMC_U_BOOT_SIZE;
blk_start = offset / mmc->read_bl_len;
blk_off = offset % mmc->read_bl_len;
blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1;
blk_start++;
}
err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
- (uchar *)CONFIG_SYS_MMC_U_BOOT_DST +
+ (uchar *)CFG_SYS_MMC_U_BOOT_DST +
(blk_off ? (mmc->read_bl_len - blk_off) : 0));
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
* after SDHC DMA transfer.
*/
if (blk_off)
- memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST,
+ memcpy((uchar *)CFG_SYS_MMC_U_BOOT_DST,
tmp_buf + blk_off, mmc->read_bl_len - blk_off);
/*
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
- flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE);
+ flush_cache(CFG_SYS_MMC_U_BOOT_DST, CFG_SYS_MMC_U_BOOT_SIZE);
/*
* Jump to U-Boot image
*/
- uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START;
+ uboot = (void *)CFG_SYS_MMC_U_BOOT_START;
(*uboot)();
}
#include <asm/arch/hardware.h>
#include "atmel_mci.h"
-#ifndef CONFIG_SYS_MMC_CLK_OD
-# define CONFIG_SYS_MMC_CLK_OD 150000
+#ifndef CFG_SYS_MMC_CLK_OD
+# define CFG_SYS_MMC_CLK_OD 150000
#endif
#define MMC_DEFAULT_BLKLEN 512
/* Set default clocks and blocklen */
#ifdef CONFIG_DM_MMC
- mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+ mci_set_mode(dev, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
#else
- mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+ mci_set_mode(mmc, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
#endif
return 0;
struct mmc *mmc;
struct sh_sdhi_host *host = NULL;
- if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL)
+ if (ch >= CFG_SYS_SH_SDHI_NR_CHANNEL)
return -ENODEV;
host = malloc(sizeof(struct sh_sdhi_host));
* AMD/Spansion Application Note: Migration from Single-byte to Three-byte
* Device IDs, Publication Number 25538 Revision A, November 8, 2001
*
- * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
+ * Define CFG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
* reading and writing ... (yes there is such a Hardware).
*/
#else
__weak phys_addr_t cfi_flash_bank_addr(int i)
{
- return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
+ return ((phys_addr_t [])CFG_SYS_FLASH_BANKS_LIST)[i];
}
#endif
__weak unsigned long cfi_flash_bank_size(int i)
{
-#ifdef CONFIG_SYS_FLASH_BANKS_SIZES
- return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
+#ifdef CFG_SYS_FLASH_BANKS_SIZES
+ return ((unsigned long [])CFG_SYS_FLASH_BANKS_SIZES)[i];
#else
return 0;
#endif
*/
#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \
(defined(CONFIG_SYS_MONITOR_BASE) && \
- (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE))
+ (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE))
static flash_info_t *flash_get_info(ulong base)
{
int i;
int i;
int cword_offset;
int cp_offset;
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
u32 cmd_le = cpu_to_le32(cmd);
#endif
uchar val;
for (i = info->portwidth; i > 0; i--) {
cword_offset = (info->portwidth - i) % info->chipwidth;
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
cp_offset = info->portwidth - i;
val = *((uchar *)&cmd_le + cword_offset);
#else
uchar retval;
cp = flash_map(info, 0, offset);
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
retval = flash_read8(cp);
#else
retval = flash_read8(cp + info->portwidth - 1);
for (x = 0; x < 4 * info->portwidth; x++)
debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
#endif
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
retval = ((flash_read8(addr) << 16) |
(flash_read8(addr + info->portwidth) << 24) |
(flash_read8(addr + 2 * info->portwidth)) |
#endif
/* Wait for command completion */
-#ifdef CONFIG_SYS_LOW_RES_TIMER
+#ifdef CFG_SYS_LOW_RES_TIMER
reset_timer();
#endif
start = get_timer(0);
#endif
/* Wait for command completion */
-#ifdef CONFIG_SYS_LOW_RES_TIMER
+#ifdef CFG_SYS_LOW_RES_TIMER
reset_timer();
#endif
start = get_timer(0);
*/
static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
{
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
unsigned short w;
unsigned int l;
unsigned long long ll;
cword->w8 = c;
break;
case FLASH_CFI_16BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
w = c;
w <<= 8;
cword->w16 = (cword->w16 >> 8) | w;
#endif
break;
case FLASH_CFI_32BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
l = c;
l <<= 24;
cword->w32 = (cword->w32 >> 8) | l;
#endif
break;
case FLASH_CFI_64BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
ll = c;
ll <<= 56;
cword->w64 = (cword->w64 >> 8) | ll;
/* Monitor protection ON by default */
#if defined(CONFIG_SYS_MONITOR_BASE) && \
- (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \
+ (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE) && \
(!defined(CONFIG_MONITOR_IS_IN_RAM))
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
if (ver >= FSL_IFC_V2_0_0)
ifc_ctrl->regs.rregs =
- (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+ (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
else
ifc_ctrl->regs.rregs =
- (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
+ (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
/* clear event registers */
ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
static inline struct fsl_ifc_runtime *runtime_regs_address(void)
{
- struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
+ struct fsl_ifc regs = {(void *)CFG_SYS_IFC_ADDR, NULL};
int ver = 0;
ver = ifc_in32(®s.gregs->ifc_rev);
if (ver >= FSL_IFC_V2_0_0)
- regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+ regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
else
- regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
+ regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
return regs.rregs;
}
int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
{
- struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR;
struct fsl_ifc_runtime *ifc = NULL;
uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
int page_size;
static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
= (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
-#if !defined(CONFIG_SYS_MAX_NAND_CHIPS)
-#define CONFIG_SYS_MAX_NAND_CHIPS 1
+#if !defined(CFG_SYS_MAX_NAND_CHIPS)
+#define CFG_SYS_MAX_NAND_CHIPS 1
#endif
#define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
lpc32xx_nand_init();
/* identify chip */
- ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
+ ret = nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL);
if (ret) {
pr_err("nand_scan_ident returned %i", ret);
return;
static inline uint16_t onenand_readw(uint32_t addr)
{
- return readw(CONFIG_SYS_ONENAND_BASE + addr);
+ return readw(CFG_SYS_ONENAND_BASE + addr);
}
static inline void onenand_writew(uint16_t value, uint32_t addr)
{
- writew(value, CONFIG_SYS_ONENAND_BASE + addr);
+ writew(value, CFG_SYS_ONENAND_BASE + addr);
}
static enum onenand_spl_pagesize onenand_spl_get_geometry(void)
static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf,
enum onenand_spl_pagesize pagesize)
{
- const uint32_t addr = CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM;
+ const uint32_t addr = CFG_SYS_ONENAND_BASE + ONENAND_DATARAM;
uint32_t offset;
onenand_writew(onenand_block_address(block),
/* It's used for some board init required */
err = onenand_board_init(&onenand_mtd);
#else
- onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE;
+ onenand_chip.base = (void *) CFG_SYS_ONENAND_BASE;
#endif
if (!err && !(onenand_scan(&onenand_mtd, 1))) {
}
#ifdef CONFIG_FSL_CORENET
- offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
- code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE;
+ offset = CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ code_len = CFG_SYS_SPI_FLASH_U_BOOT_SIZE;
#else
/*
* Load U-Boot image from SPI flash into RAM
flash->page_size, (void *)buf);
offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
/* Skip spl code */
- offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ offset += CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
/* Get the code size from offset 0x48 */
code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
/* Skip spl code */
printf("Loading second stage boot loader ");
while (copy_len <= code_len) {
spi_flash_read(flash, offset + copy_len, 0x2000,
- (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST
+ (void *)(CFG_SYS_SPI_FLASH_U_BOOT_DST
+ copy_len));
copy_len = copy_len + 0x2000;
putc('.');
/*
* Jump to U-Boot image
*/
- flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
- uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START;
+ flush_cache(CFG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
+ uboot = (void *)CFG_SYS_SPI_FLASH_U_BOOT_START;
(*uboot)();
}
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
flash_info[i].flash_id = FLASH_STM32;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
+ flash_info[i].start[0] = CFG_SYS_FLASH_BASE + (i << 20);
flash_info[i].size = sect_sz_kb[0];
for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
flash_info[i].start[j] = flash_info[i].start[j - 1]
struct dtsec *regs = (struct dtsec *)CFG_SYS_FSL_FM1_DTSEC1_ADDR;
/* Assign a Physical address to the TBI */
- out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
+ out_be32(®s->tbipa, CFG_SYS_TBIPA_VALUE);
#endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
void *base = reg;
muram[fm_idx].base = base;
- muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
+ muram[fm_idx].size = CFG_SYS_FM_MURAM_SIZE;
muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
- muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
+ muram[fm_idx].top = base + CFG_SYS_FM_MURAM_SIZE;
}
/*
{
int off;
uint32_t ph;
- phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
+ phys_addr_t paddr = CFG_SYS_CCSRBAR_PHYS + info->compat_offset;
#ifndef CONFIG_SYS_FMAN_V3
- u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
+ u64 dtsec1_addr = (u64)CFG_SYS_CCSRBAR_PHYS +
CFG_SYS_FSL_FM1_DTSEC1_OFFSET;
#endif
s->addr_cena = d->cena_bar;
s->addr_cinh = d->cinh_bar;
- s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
+ s->cena = (void *)valloc(CFG_SYS_PAGE_SIZE);
if (!s->cena) {
printf("Could not allocate page for cena shadow\n");
return -1;
}
- memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
+ memset((void *)s->cena, 0x00, CFG_SYS_PAGE_SIZE);
#ifdef QBMAN_CHECKING
/* We should never be asked to initialise for a portal that isn't in
static struct mc_version mc_ver_info;
static int mc_boot_status = -1;
static int mc_dpl_applied = -1;
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
static int mc_aiop_applied = -1;
#endif
struct fsl_mc_io *root_mc_io = NULL;
int dpc_size;
#endif
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
- BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
- CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
+#ifdef CFG_SYS_LS_MC_DRAM_DPC_OFFSET
+ BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
+ CFG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
- mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
+ mc_dpc_offset = CFG_SYS_LS_MC_DRAM_DPC_OFFSET;
#else
-#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
+#error "CFG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
#endif
/*
}
dpc_size = fdt_totalsize(dpc_fdt_hdr);
- if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
+ if (dpc_size > CFG_SYS_LS_MC_DPC_MAX_LENGTH) {
printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
dpc_size);
return -EINVAL;
int dpl_size;
#endif
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
- BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
- CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
+#ifdef CFG_SYS_LS_MC_DRAM_DPL_OFFSET
+ BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
+ CFG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
- mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
+ mc_dpl_offset = CFG_SYS_LS_MC_DRAM_DPL_OFFSET;
#else
-#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
+#error "CFG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
#endif
/*
}
dpl_size = fdt_totalsize(dpl_fdt_hdr);
- if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
+ if (dpl_size > CFG_SYS_LS_MC_DPL_MAX_LENGTH) {
printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
dpl_size);
return -EINVAL;
*/
static unsigned long get_mc_boot_timeout_ms(void)
{
- unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+ unsigned long timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS;
char *timeout_ms_env_var = env_get(MC_BOOT_TIMEOUT_ENV_VAR);
"\' environment variable: %lu\n",
timeout_ms);
- timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+ timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS;
}
}
return timeout_ms;
}
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
__weak bool soc_has_aiop(void)
{
#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
- CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+ CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
#else
aiop_img = (void *)aiop_fw_addr;
mc_copy_image("MC AIOP image",
- (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
- mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+ (u64)aiop_img, CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
+ mc_ram_addr + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
#endif
mc_aiop_applied = 0;
return mc_boot_status;
}
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void)
{
return mc_aiop_applied;
*/
unsigned long mc_get_dram_block_size(void)
{
- unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+ unsigned long dram_block_size = CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
char *dram_block_size_env_var = env_get(MC_MEM_SIZE_ENV_VAR);
if (dram_block_size_env_var) {
dram_block_size = hextoul(dram_block_size_env_var, NULL);
- if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
+ if (dram_block_size < CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
printf("fsl-mc: WARNING: Invalid value for \'"
MC_MEM_SIZE_ENV_VAR
"\' environment variable: %lu\n",
case 's': {
char sub_cmd;
u64 mc_fw_addr, mc_dpc_addr;
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
u64 aiop_fw_addr;
#endif
if (argc < 3)
err = mc_init_object();
break;
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
case 'a':
if (argc < 4)
goto usage;
static void init_eth_info(struct fec_info_dma *info)
{
/* setup Receive and Transmit buffer descriptor */
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+#ifdef CFG_SYS_FEC_BUF_USE_SRAM
static u32 tmp;
if (info->index == 0)
- tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+ tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
else
info->rxbd = (cbd_t *)DBUF_LENGTH;
tmp = (u32)info->txbd;
info->txbuf =
(char *)((u32)info->txbuf + tmp +
- (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
tmp = (u32)info->txbuf;
#else
info->rxbd =
(PKTBUFSRX * sizeof(cbd_t)));
info->txbd =
(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
- (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
info->txbuf =
(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif
/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Settings: Last, Tx CRC */
- for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
+ for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) {
info->txbd[i].cbd_sc = 0;
info->txbd[i].cbd_datlen = 0;
info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
}
- info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
+ info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
info->used_tbd_idx = 0;
- info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
+ info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER;
/* Set Rx FIFO alarm and granularity value */
fecp->rfcr = 0x0c000000;
miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
/* process all the consumed TBDs */
- while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
+ while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) {
p_used_tbd = &info->txbd[info->used_tbd_idx];
if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
#ifdef ET_DEBUG
}
/* clean this buffer descriptor */
- if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
+ if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1))
p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
else
p_used_tbd->cbd_sc = 0;
/* update some indeces for a correct handling of TBD ring */
info->clean_tbd_num++;
info->used_tbd_idx = (info->used_tbd_idx + 1)
- % CONFIG_SYS_TX_ETH_BUFFER;
+ % CFG_SYS_TX_ETH_BUFFER;
}
/* Check for valid length of data. */
p_tbd->cbd_datlen = length;
p_tbd->cbd_bufaddr = (u32)packet;
p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
- info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
+ info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER;
/* Enable DMA transmit task */
MCD_continDma(info->tx_task);
if (val)
info->tx_init = fdt32_to_cpu(*val);
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
- u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+#ifdef CFG_SYS_FEC_BUF_USE_SRAM
+ u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
#endif
init_eth_info(info);
static void init_eth_info(struct fec_info_s *info)
{
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+#ifdef CFG_SYS_FEC_BUF_USE_SRAM
static u32 tmp;
if (info->index == 0)
- tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+ tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
else
info->rxbd = (cbd_t *)DBUF_LENGTH;
tmp = (u32)info->txbd;
info->txbuf =
(char *)((u32)info->txbuf + tmp +
- (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
tmp = (u32)info->txbuf;
#else
info->rxbd =
/* Activate transmit Buffer Descriptor polling */
fecp->tdar = 0x01000000; /* Descriptor polling active */
-#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
+#ifndef CFG_SYS_FEC_BUF_USE_SRAM
/*
* FEC unable to initial transmit data packet.
* A nop will ensure the descriptor polling active completed.
#define STD_UEC_INFO(num) \
{ \
.uf_info = { \
- .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
- .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
- .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
- .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
+ .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\
+ .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \
+ .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \
+ .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\
}, \
.num_threads_tx = UEC_NUM_OF_THREADS_1, \
.num_threads_rx = UEC_NUM_OF_THREADS_1, \
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
.tx_bd_ring_len = 16, \
.rx_bd_ring_len = 16, \
- .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
- .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
- .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
+ .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \
+ .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \
+ .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \
}
struct uec_inf {
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
- priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ priv->tbiaddr = CFG_SYS_TBIPA_VALUE;
priv->flags = tsec_info->flags;
strcpy(dev->name, tsec_info->devname);
struct eth_pdata *pdata = dev_get_plat(dev);
struct tsec_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
- u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ u32 tbiaddr = CFG_SYS_TBIPA_VALUE;
struct tsec_data *data;
ofnode parent, child;
fdt_addr_t reg;
u8 *fw = firmware;
unsigned int i;
- u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050);
- u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040);
- u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044);
- u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048);
- u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070);
+ u32 *gloreset = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c050);
+ u32 *icpu_ctrl = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c040);
+ u32 *icpu_addr = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c044);
+ u32 *icpu_data = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c048);
+ u32 *icpu_rom_map = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c070);
#ifdef DEBUG
- u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060);
+ u32 *chipid = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c060);
#endif
out_be32(gloreset, 3);
p->number_of_regs = DIALOG_NUM_OF_REGS;
p->interface = PMIC_I2C;
- p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR;
+ p->hw.i2c.addr = CFG_SYS_DIALOG_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = bus;
#define STD_UEC_INFO(num) \
{ \
.uf_info = { \
- .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
- .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
- .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
- .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
+ .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\
+ .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \
+ .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \
+ .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\
}, \
.num_threads_tx = UEC_NUM_OF_THREADS_1, \
.num_threads_rx = UEC_NUM_OF_THREADS_1, \
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
.tx_bd_ring_len = 16, \
.rx_bd_ring_len = 16, \
- .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
- .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
- .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
+ .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \
+ .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \
+ .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \
}
struct uec_inf {
*
* Some boards do not have a PHY for each ethernet port. These ports are known
* as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
- * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
+ * CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
* When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
* and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
* speed and duplex should be for the port.
* #define CONFIG_FIXED_PHY 0xFFFFFFFF
* #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
*
- * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
- * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
- * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
- * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
+ * #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ * #define CFG_SYS_UEC2_PHY_ADDR 0x02
+ * #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ * #define CFG_SYS_UEC4_PHY_ADDR 0x04
*
* #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
* {name, speed, duplex},
#endif
/*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#ifndef CFG_SYS_I2C_RTC_ADDR
+# define CFG_SYS_I2C_RTC_ADDR 0x68
#endif
#if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
static
uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
#endif /* !CONFIG_DM_RTC */
static
uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
#else
static uchar rtc_read(struct udevice *dev, uchar reg)
#endif
/*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#ifndef CFG_SYS_I2C_RTC_ADDR
+# define CFG_SYS_I2C_RTC_ADDR 0x68
#endif
#if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
*/
static uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write(uchar reg, uchar val, bool set)
{
if (set == true) {
- val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ val |= i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
} else {
- val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val;
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ val = i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg) & ~val;
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
}
static void rtc_write_raw (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
static
uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
#else
static int ds3231_rtc_get(struct udevice *dev, struct rtc_time *tmp)
{
u8 buf[M41T62_DATETIME_REG_SIZE];
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
+ i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
m41t62_update_rtc_time(tm, buf);
return 0;
{
u8 buf[M41T62_DATETIME_REG_SIZE];
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
+ i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
m41t62_set_rtc_buf(tm, buf);
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf,
+ if (i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf,
M41T62_DATETIME_REG_SIZE)) {
printf("I2C write failed in %s()\n", __func__);
return -1;
* M41T82: Make sure HT (Halt Update) bit is cleared.
* This bit is 0 in M41T62 so its save to clear it always.
*/
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
+ i2c_read(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
val &= ~M41T80_ALHOUR_HT;
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
+ i2c_write(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
}
#endif /* CONFIG_DM_RTC */
#include <i2c.h>
#include <linux/delay.h>
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-#define CONFIG_SYS_I2C_RTC_ADDR 0x50
+#ifndef CFG_SYS_I2C_RTC_ADDR
+#define CFG_SYS_I2C_RTC_ADDR 0x50
#endif
/* ------------------------------------------------------------------------- */
static uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
udelay(2500);
}
static uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
#else
static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp)
/****** Helper functions ****************************************/
static u8 rtc_read(u8 reg)
{
- return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg);
+ return i2c_reg_read(CFG_SYS_I2C_RTC_ADDR, reg);
}
static void rtc_write(u8 reg, u8 val)
{
- i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write(CFG_SYS_I2C_RTC_ADDR, reg, val);
}
/****************************************************************/
#define rtc_debug 0 /* gcc will remove all the debug code for us */
#endif
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#ifndef CFG_SYS_I2C_RTC_ADDR
+#define CFG_SYS_I2C_RTC_ADDR 0x32
#endif
#define RS5C372_RAM_SIZE 0x10
{
int ret;
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len);
+ ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len);
if (ret != 0) {
printf("%s: failed to read\n", __FUNCTION__);
return ret;
buf[14] = 0; /* reg. 13 */
buf[15] = 0; /* reg. 14 */
buf[16] = USE_24HOUR_MODE; /* reg. 15 */
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1);
+ ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1);
if (ret != 0) {
printf("%s: failed\n", __FUNCTION__);
return;
memset(buf, 0, sizeof(buf));
/* only read register 15 */
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1);
+ ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1);
if (ret == 0) {
/* need to save register 15 */
printf("WARNING: year should be between 1970 and 2069!\n");
buf[7] = bin2bcd(tmp->tm_year % 100);
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8);
+ ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8);
if (ret != 0) {
printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret);
return -1;
#endif
/*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#ifndef CFG_SYS_I2C_RTC_ADDR
+# define CFG_SYS_I2C_RTC_ADDR 0x32
#endif
/*
int rtc_get(struct rtc_time *tm)
{
struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ .chip = CFG_SYS_I2C_RTC_ADDR,
};
return rx8010sj_rtc_get(&dev, tm);
int rtc_set(struct rtc_time *tm)
{
struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ .chip = CFG_SYS_I2C_RTC_ADDR,
};
return rx8010sj_rtc_set(&dev, tm);
void rtc_reset(void)
{
struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ .chip = CFG_SYS_I2C_RTC_ADDR,
};
rx8010sj_rtc_reset(&dev);
void rtc_init(void)
{
struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ .chip = CFG_SYS_I2C_RTC_ADDR,
};
rx8010sj_rtc_init(&dev);
static void rtc_write(int reg, u8 val)
{
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
+ i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
}
/*
{
u8 buf[8];
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
+ i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
/*
* Table with supported baudrates (defined in config_xyz.h)
*/
-static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
static int serial_check_stdout(const void *blob, struct udevice **devp)
/*
* Table with supported baudrates (defined in config_xyz.h)
*/
-static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
/**
* serial_null() - Void registration routine of a serial driver
}
#if CONFIG_POST & CONFIG_SYS_POST_UART
-static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE;
+static const int bauds[] = CFG_SYS_BAUDRATE_TABLE;
/**
* uart_post_test() - Test the currently selected serial port using POST
SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
/* setup format */
- scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
+ scalar = ((CFG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
/*
* Use following format:
struct davinci_spi_slave *ds = dev_get_priv(bus);
debug("%s speed %u\n", __func__, max_hz);
- if (max_hz > CONFIG_SYS_SPI_CLK / 2)
+ if (max_hz > CFG_SYS_SPI_CLK / 2)
return -EINVAL;
ds->freq = max_hz;
* follows:
* SPI actual frequency = core_clk / (SPR * (2 ^ SPPR))
*/
- divider = DIV_ROUND_UP(CONFIG_SYS_TCLK, hz);
+ divider = DIV_ROUND_UP(CFG_SYS_TCLK, hz);
if (divider < 16) {
/* This is the easy case, divider is less than 16 */
spr = divider;
data = readl(®->timing1);
data &= ~KW_SPI_TMISO_SAMPLE_MASK;
- if (CONFIG_SYS_TCLK == 250000000 &&
+ if (CFG_SYS_TCLK == 250000000 &&
mode & SPI_CPOL &&
mode & SPI_CPHA)
data |= KW_SPI_TMISO_SAMPLE_2;
{
switch (type) {
case SYSRESET_COLD:
- writel(CONFIG_SYS_FPGAREG_RESET_CODE,
- CONFIG_SYS_FPGAREG_RESET);
+ writel(CFG_SYS_FPGAREG_RESET_CODE,
+ CFG_SYS_FPGAREG_RESET);
break;
default:
return -EPROTONOSUPPORT;
return ret;
uc_priv->clock_rate = ret;
} else {
- uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+ uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
}
/* init timer */
#define GPT_CLKSRC_IPG_CLK (1 << 6)
#define GPT_CLKSRC_IPG_CLK_24M (5 << 6)
-/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
-#ifndef CONFIG_SYS_HZ_CLOCK
-#define CONFIG_SYS_HZ_CLOCK 3000000
+/* If CFG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
+#ifndef CFG_SYS_HZ_CLOCK
+#define CFG_SYS_HZ_CLOCK 3000000
#endif
struct imx_gpt_timer_regs {
static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
{
- u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+ u32 prescaler = (rate / CFG_SYS_HZ_CLOCK) - 1;
/* Reset the timer */
setbits_le32(®s->cr, GPT_CR_SWR);
return ret;
}
- uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+ uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
return 0;
}
if (IS_ENABLED(CONFIG_ARCH_MVEBU))
return MVEBU_TIMER_FIXED_RATE_25MHZ;
else
- return CONFIG_SYS_TCLK;
+ return CFG_SYS_TCLK;
}
/**
if (type == INPUT_CLOCK_25MHZ)
uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ;
else
- uc_priv->clock_rate = CONFIG_SYS_TCLK;
+ uc_priv->clock_rate = CFG_SYS_TCLK;
orion_timer_init(priv->base, type);
return 0;
rate = clk_get_rate(&clk);
/* we set timer prescaler to obtain a 1MHz timer counter frequency */
- psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+ psc = (rate / CFG_SYS_HZ_CLOCK) - 1;
writel(psc, ®s->psc);
/* Set timer frequency to 1MHz */
- uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+ uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
/* Configure timer for auto-reload */
setbits_le32(®s->cr1, CR1_ARPE);
gohci.disabled = 1;
gohci.sleeping = 0;
gohci.irq = -1;
- gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
+ gohci.regs = (struct ohci_regs *)CFG_SYS_USB_OHCI_REGS_BASE;
gohci.flags = 0;
gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
.usecount = 0,
};
-#if !defined CONFIG_SYS_LDB_CLOCK
-#define CONFIG_SYS_LDB_CLOCK 65000000
+#if !defined CFG_SYS_LDB_CLOCK
+#define CFG_SYS_LDB_CLOCK 65000000
#endif
static struct clk ldb_clk = {
.name = "ldb_clk",
- .rate = CONFIG_SYS_LDB_CLOCK,
+ .rate = CFG_SYS_LDB_CLOCK,
.usecount = 0,
};
type flash chips the second sector can be used: the offset
for this sector is given here.
- CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
+ CONFIG_ENV_OFFSET is used relative to CFG_SYS_FLASH_BASE.
CONFIG_ENV_ADDR:
/*
* Add in absolutes.
*/
-GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE));
+GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE));
#endif /* ENV_IS_EMBEDDED */
#endif
#endif
-#ifndef CONFIG_SYS_BAUDRATE_TABLE
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#ifndef CFG_SYS_BAUDRATE_TABLE
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
#endif /* __CONFIG_FALLBACKS_H */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
-#define CONFIG_SYS_PLL_ODR 0x36
-#define CONFIG_SYS_PLL_FDR 0x7D
+#define CFG_SYS_CLK 166666666 /* CPU Core Clock */
+#define CFG_SYS_PLL_ODR 0x36
+#define CFG_SYS_PLL_FDR 0x7D
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
* You should know what you are doing if you make changes here.
*/
/* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/*
* Configuration for environment
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
* CS4 - Available
* CS5 - Available
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x007F0001
-#define CONFIG_SYS_CS0_CTRL 0x00001FA0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x007F0001
+#define CFG_SYS_CS0_CTRL 0x00001FA0
#endif /* _M5208EVBE_H */
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* I2C */
-#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
-#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
-#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
+#define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
+#define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
/* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
#ifdef CONFIG_MCFFEC
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 75000000
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
+#define CFG_SYS_CLK 75000000
+#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2
-#define CONFIG_SYS_MBAR 0x40000000
+#define CFG_SYS_MBAR 0x40000000
/*
* Low Level Configuration Settings
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x21
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x21
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
+#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
* CS7 - Available
*/
#ifdef CONFIG_NORFLASH_PS32BIT
-# define CONFIG_SYS_CS0_BASE 0xFFC00000
-# define CONFIG_SYS_CS0_MASK 0x003f0001
-# define CONFIG_SYS_CS0_CTRL 0x00001D00
+# define CFG_SYS_CS0_BASE 0xFFC00000
+# define CFG_SYS_CS0_MASK 0x003f0001
+# define CFG_SYS_CS0_CTRL 0x00001D00
#else
-# define CONFIG_SYS_CS0_BASE 0xFFE00000
-# define CONFIG_SYS_CS0_MASK 0x001f0001
-# define CONFIG_SYS_CS0_CTRL 0x00001D80
+# define CFG_SYS_CS0_BASE 0xFFE00000
+# define CFG_SYS_CS0_MASK 0x001f0001
+# define CFG_SYS_CS0_CTRL 0x00001D80
#endif
#endif /* _M5329EVB_H */
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
* Clock configuration: enable only one of the following options
*/
-#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
-#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
-#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
+#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
+#define CFG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
/*
* Low Level Configuration Settings
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
-#define CONFIG_SYS_MBAR2 0x80000000
+#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_SYS_MBAR2 0x80000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
+#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
+#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
/*-----------------------------------------------------------------------
*/
/* CS0 - AMD Flash, address 0xffc00000 */
-#define CONFIG_SYS_CS0_BASE 0xffe00000
-#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
+#define CFG_SYS_CS0_BASE 0xffe00000
+#define CFG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
+#define CFG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
-#define CONFIG_SYS_CS1_BASE 0xe0000000
-#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
-#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define CFG_SYS_CS1_BASE 0xe0000000
+#define CFG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
+#define CFG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
-#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
-#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
+#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
+#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* M5249 */
#include <linux/stringify.h>
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
/* Configuration for environment
env/embedded.o(.text*);
#ifdef CONFIG_DRIVER_DM9000
-# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
+# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300)
# define DM9000_IO CONFIG_DM9000_BASE
# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
# undef CONFIG_DM9000_DEBUG
#define CONFIG_HOSTNAME "M5253DEMO"
/* I2C */
-#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
-#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
-#define CONFIG_SYS_I2C_PINMUX_SET (0)
-
-#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
-#define CONFIG_SYS_FAST_CLK
-#ifdef CONFIG_SYS_FAST_CLK
-# define CONFIG_SYS_PLLCR 0x1243E054
-# define CONFIG_SYS_CLK 140000000
+#define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C))
+#define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
+#define CFG_SYS_I2C_PINMUX_SET (0)
+
+#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
+#define CFG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
+# define CFG_SYS_PLLCR 0x1243E054
+# define CFG_SYS_CLK 140000000
#else
-# define CONFIG_SYS_PLLCR 0x135a4140
-# define CONFIG_SYS_CLK 70000000
+# define CFG_SYS_PLLCR 0x135a4140
+# define CFG_SYS_CLK 70000000
#endif
/*
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
-#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
+#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*
* Start addresses for the final memory configuration
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
+#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
#define FLASH_SST6401B 0x200
#define SST_ID_xF6401B 0x236D236D
* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
* 0x30 is block erase in SST
*/
-# define CONFIG_SYS_FLASH_SIZE 0x800000
+# define CFG_SYS_FLASH_SIZE 0x800000
#else
-# define CONFIG_SYS_SST_SECT 2048
-# define CONFIG_SYS_SST_SECTSZ 0x1000
+# define CFG_SYS_SST_SECT 2048
+# define CFG_SYS_SST_SECTSZ 0x1000
#endif
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \
CF_ADDRMASK(8) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
+#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
-#define CONFIG_SYS_CS0_BASE 0xFF800000
-#define CONFIG_SYS_CS0_MASK 0x007F0021
-#define CONFIG_SYS_CS0_CTRL 0x00001D80
+#define CFG_SYS_CS0_BASE 0xFF800000
+#define CFG_SYS_CS0_MASK 0x007F0021
+#define CFG_SYS_CS0_CTRL 0x00001D80
-#define CONFIG_SYS_CS1_BASE 0xE0000000
-#define CONFIG_SYS_CS1_MASK 0x00000001
-#define CONFIG_SYS_CS1_CTRL 0x00003DD8
+#define CFG_SYS_CS1_BASE 0xE0000000
+#define CFG_SYS_CS1_MASK 0x00000001
+#define CFG_SYS_CS1_CTRL 0x00003DD8
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
-#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
-#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
+#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
+#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
+#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
+#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
+#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
+#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* _M5253DEMO_H */
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
"save\0" \
""
-#define CONFIG_SYS_CLK 66000000
+#define CFG_SYS_CLK 66000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
-#define CONFIG_SYS_SCR 0x0003
-#define CONFIG_SYS_SPR 0xffff
+#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_SYS_SCR 0x0003
+#define CFG_SYS_SPR 0xffff
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE 0xffe00000
+#define CFG_SYS_FLASH_BASE 0xffe00000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_PACNT 0x00000000
-#define CONFIG_SYS_PADDR 0x0000
-#define CONFIG_SYS_PADAT 0x0000
-#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
-#define CONFIG_SYS_PBDDR 0x0000
-#define CONFIG_SYS_PBDAT 0x0000
-#define CONFIG_SYS_PDCNT 0x00000000
+#define CFG_SYS_PACNT 0x00000000
+#define CFG_SYS_PADDR 0x0000
+#define CFG_SYS_PADAT 0x0000
+#define CFG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
+#define CFG_SYS_PBDDR 0x0000
+#define CFG_SYS_PBDAT 0x0000
+#define CFG_SYS_PDCNT 0x00000000
#endif /* _M5272C3_H */
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
/* Available command configuration */
/* I2C */
-#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
-#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
-#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
+#define CFG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
+#define CFG_SYS_I2C_PINMUX_CLR (0xFFF0)
+#define CFG_SYS_I2C_PINMUX_SET (0x000F)
#ifdef CONFIG_MCFFEC
# define CONFIG_OVERWRITE_ETHADDR_ONCE
"save\0" \
""
-#define CONFIG_SYS_CLK 150000000
+#define CFG_SYS_CLK 150000000
/*
* Low Level Configuration Settings
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x40000000
+#define CFG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CONFIG_SYS_FLASH_SIZE 0x200000
+#define CFG_SYS_FLASH_SIZE 0x200000
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
-#define CONFIG_SYS_CS0_BASE 0xffe00000
-#define CONFIG_SYS_CS0_CTRL 0x00001980
-#define CONFIG_SYS_CS0_MASK 0x001F0001
+#define CFG_SYS_CS0_BASE 0xffe00000
+#define CFG_SYS_CS0_CTRL 0x00001980
+#define CFG_SYS_CS0_MASK 0x001F0001
-#define CONFIG_SYS_CS1_BASE 0x30000000
-#define CONFIG_SYS_CS1_CTRL 0x00001900
-#define CONFIG_SYS_CS1_MASK 0x00070001
+#define CFG_SYS_CS1_BASE 0x30000000
+#define CFG_SYS_CS1_CTRL 0x00001900
+#define CFG_SYS_CS1_MASK 0x00070001
#endif /* _M5275EVB_H */
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
"save\0" \
""
-#define CONFIG_SYS_CLK 64000000
+#define CFG_SYS_CLK 64000000
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
-#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
+#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
+#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
-#define CONFIG_SYS_MBAR 0x40000000
+#define CFG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
+#define CFG_SYS_INT_FLASH_BASE 0xf0000000
+#define CFG_SYS_INT_FLASH_ENABLE 0x21
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
-#define CONFIG_SYS_CS0_BASE 0xFFE00000
-#define CONFIG_SYS_CS0_CTRL 0x00001980
-#define CONFIG_SYS_CS0_MASK 0x001F0001
+#define CFG_SYS_CS0_BASE 0xFFE00000
+#define CFG_SYS_CS0_CTRL 0x00001980
+#define CFG_SYS_CS0_MASK 0x001F0001
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
-#define CONFIG_SYS_PADDR 0x0000000
-#define CONFIG_SYS_PADAT 0x0000000
+#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
+#define CFG_SYS_PADDR 0x0000000
+#define CFG_SYS_PADAT 0x0000000
-#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
-#define CONFIG_SYS_PBDDR 0x0000000
-#define CONFIG_SYS_PBDAT 0x0000000
+#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
+#define CFG_SYS_PBDDR 0x0000000
+#define CFG_SYS_PBDAT 0x0000000
-#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
+#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
-#define CONFIG_SYS_PEHLPAR 0xC0
-#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
-#define CONFIG_SYS_DDRUA 0x05
-#define CONFIG_SYS_PJPAR 0xFF
+#define CFG_SYS_PEHLPAR 0xC0
+#define CFG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
+#define CFG_SYS_DDRUA 0x05
+#define CFG_SYS_PJPAR 0xFF
#endif /* _CONFIG_M5282EVB_H */
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000
#ifdef CONFIG_MCFFEC
-# define CONFIG_SYS_TX_ETH_BUFFER 8
-# define CONFIG_SYS_FEC_BUF_USE_SRAM
+# define CFG_SYS_TX_ETH_BUFFER 8
+# define CFG_SYS_FEC_BUF_USE_SRAM
#endif
-#define CONFIG_SYS_RTC_CNT (0x8000)
-#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
+#define CFG_SYS_RTC_CNT (0x8000)
+#define CFG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
/* I2C */
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 80000000
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK 80000000
+#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_SPANSION_S29WS_N 1
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
#endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
* CS4 - Available
* CS5 - Available
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00001FA0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x00FF0001
+#define CFG_SYS_CS0_CTRL 0x00001FA0
-#define CONFIG_SYS_CS1_BASE 0xC0000000
-#define CONFIG_SYS_CS1_MASK 0x00070001
-#define CONFIG_SYS_CS1_CTRL 0x00001FA0
+#define CFG_SYS_CS1_BASE 0xC0000000
+#define CFG_SYS_CS1_MASK 0x00070001
+#define CFG_SYS_CS1_CTRL 0x00001FA0
#endif /* _M53017EVB_H */
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 80000000
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK 80000000
+#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
-#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
+#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
#ifdef CONFIG_CMD_NAND
-# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
+# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE
# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#endif
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
* CS4 - Available
* CS5 - Available
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x007f0001
-#define CONFIG_SYS_CS0_CTRL 0x00001fa0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x007f0001
+#define CFG_SYS_CS0_CTRL 0x00001fa0
-#define CONFIG_SYS_CS1_BASE 0x10000000
-#define CONFIG_SYS_CS1_MASK 0x001f0001
-#define CONFIG_SYS_CS1_CTRL 0x002A3780
+#define CFG_SYS_CS1_BASE 0x10000000
+#define CFG_SYS_CS1_MASK 0x001f0001
+#define CFG_SYS_CS1_CTRL 0x002A3780
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_CS2_BASE 0x20000000
-#define CONFIG_SYS_CS2_MASK (16 << 20)
-#define CONFIG_SYS_CS2_CTRL 0x00001f60
+#define CFG_SYS_CS2_BASE 0x20000000
+#define CFG_SYS_CS2_MASK (16 << 20)
+#define CFG_SYS_CS2_CTRL 0x00001f60
#endif
#endif /* _M5329EVB_H */
* (easy to change)
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_CLK 80000000
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK 80000000
+#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
-#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
+#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
+# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE
# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
* CS4 - Available
* CS5 - Available
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x007f0001
-#define CONFIG_SYS_CS0_CTRL 0x00001fa0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x007f0001
+#define CFG_SYS_CS0_CTRL 0x00001fa0
-#define CONFIG_SYS_CS1_BASE 0x10000000
-#define CONFIG_SYS_CS1_MASK 0x001f0001
-#define CONFIG_SYS_CS1_CTRL 0x002A3780
+#define CFG_SYS_CS1_BASE 0x10000000
+#define CFG_SYS_CS1_MASK 0x001f0001
+#define CFG_SYS_CS1_CTRL 0x002A3780
-#define CONFIG_SYS_CS2_BASE 0x20000000
-#define CONFIG_SYS_CS2_MASK (16 << 20)
-#define CONFIG_SYS_CS2_CTRL 0x00001f60
+#define CFG_SYS_CS2_BASE 0x20000000
+#define CFG_SYS_CS2_MASK (16 << 20)
+#define CFG_SYS_CS2_CTRL 0x00001f60
#endif /* _M5373EVB_H */
/* Miscellaneous configurable options */
/* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
-#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
+#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
+#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
#define CFG_SYS_SDRAM_BASE 0x00000000
/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CFG_SYS_BOOTMAPSZ (8 << 20)
/* Environment Configuration */
*/
/* System Clock Configuration Register */
-#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
+#define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
+#define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
+#define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
/*
* System IO Config
*/
-#define CONFIG_SYS_SICRH 0x08200000
-#define CONFIG_SYS_SICRL 0x00000000
+#define CFG_SYS_SICRH 0x08200000
+#define CFG_SYS_SICRL 0x00000000
/*
* Output Buffer Impedance
*/
-#define CONFIG_SYS_OBIR 0x30100000
+#define CFG_SYS_OBIR 0x30100000
/*
* Device configurations
* DDR Setup
*/
#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
+#define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
+#define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
* Manually set up DDR parameters
*/
#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+#define CFG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+#define CFG_SYS_DDR_TIMING_3 0x00000000
+#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
| (0 << TIMING_CFG0_RRT_SHIFT) \
| (0 << TIMING_CFG0_WWT_SHIFT) \
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00260802 */ /* DDR400 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+#define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
| (7 << TIMING_CFG1_CASLAT_SHIFT) \
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3937d322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
| (5 << TIMING_CFG2_CPO_SHIFT) \
| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x02984cc8 */
-#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
+#define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x06090100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
+#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2)
/* 0x43000000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
+#define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
+#define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
| (0x0442 << SDRAM_MODE_SD_SHIFT))
/* 0x04400442 */ /* DDR400 */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
+#define CFG_SYS_DDR_MODE2 0x00000000
/*
* Memory test
*/
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
/*
* The reserved memory
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
+#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
/*
* NAND Flash on the Local Bus
/* Vitesse 7385 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
+#define CFG_SYS_VSC7385_BASE 0xF0000000
/*
* Serial Port
*/
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_FSL_SERDES2 0xe3100
/* I2C */
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
+#define CFG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
* Config on-board RTC
*/
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+#define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* General PCI
#ifdef CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CFG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 2
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration
* Only possible on E500 Version 2 or newer cores.
*/
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xe0000000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+#define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
+#define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST \
+ {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
#define CONFIG_HWCONFIG /* enable hwconfig */
/*
* SDRAM on the Local Bus
*/
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
#else
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE
#endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+#define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR2, need:
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: the top 17 bits of BR2.
*/
/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR2, need:
* 64MB mask for AM, OR2[0:7] = 1111 1100
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* Common settings for all Local Bus SDRAM commands.
* or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
+#define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| LSDMR_PRETOACT7 \
| LSDMR_ACTTORW7 \
| LSDMR_BL8 \
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/*
* I2C
*/
#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+#define CFG_SYS_I2C_NOPROBES { {0, 0x69} }
#endif
/*
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
/*
* Environment Configuration
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CFG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#endif
#endif
extern unsigned long get_sdram_size(void);
#endif
#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xffe00000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/*
* Memory map
*/
/* NOR Flash on IFC */
-#define CONFIG_SYS_FLASH_BASE 0xee000000
+#define CFG_SYS_FLASH_BASE 0xee000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
FTIM2_NOR_TWP(0x1c)
#define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* CFI for NOR Flash */
/* Set up IFC registers for boot location NOR/NAND */
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffb00000
+#define CFG_SYS_CPLD_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
+#define CFG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
#else
-#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
#endif
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 0x0
+#define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Config the L2 Cache as L2 SRAM
*/
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#endif
#endif
#endif
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/* I2C */
#define I2C_PCA9557_ADDR1 0x18
/* RTC */
#define CONFIG_RTC_PT7C4338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/*
* SPI interface will not be available in case of NAND boot SPI CS0 will be
*/
#if defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10))
#endif
#endif
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#define CONFIG_POST CFG_SYS_POST_MEMORY /* test POST memory test */
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
+#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
CONFIG_RAMBOOT_TEXT_BASE)
#else
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
+#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR
#endif
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x52
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
*/
/* Set the local bus clock 1/8 of platform clock */
-#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
+#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8
/*
* This board doesn't have a promjet connector.
* However, it uses commone corenet board LAW and TLB.
* It is necessary to use the same start address with proper offset.
*/
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#define CFG_SYS_FLASH_BASE 0xe0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
+#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
#define CONFIG_FSL_CPLD
| OR_FCM_EHTR)
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
+#define CFG_SYS_BMAN_MEM_SIZE 0x00200000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf4200000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
+#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull
#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_MEM_SIZE 0x00200000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
-#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
-#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
-#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
+#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
+#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
+#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
+#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
+#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
+#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
+#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
+#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
+#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
+#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0
-#define CONFIG_SYS_TBIPA_VALUE 8
+#define CFG_SYS_TBIPA_VALUE 8
#endif
#ifdef CONFIG_MMC
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
/*
* Environment Configuration
/*
* NS16550 Configuration
*/
-#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/*
* U-Boot bootcode configuration
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
/*
* NS16550 Configuration
*/
-#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/*
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
+#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#define SPD_EEPROM_ADDRESS 0x51
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE 0xe8000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0xf)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
#ifdef CONFIG_TARGET_T1024RDB
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+#define CFG_SYS_CPLD_BASE 0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT (0xf)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
+#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
+#define CFG_SYS_CS2_FTIM3 0x0
#endif
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
*/
#define RTC
#define CONFIG_RTC_DS1337 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/*
* eSPI - Enhanced SPI
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
+
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
+#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
/*
- * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
- * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
- * (CONFIG_SYS_INIT_L3_VADDR) will be different.
+ * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence
+ * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address
+ * (CFG_SYS_INIT_L3_VADDR) will be different.
*/
-#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_VADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#define CFG_SYS_NOR_CSPR_EXT (0xf)
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* CPLD on IFC */
#define CPLD_LBMAP_MASK 0x3F
#define CPLD_INT_MASK_TDMR2 0x01
#endif
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CPLD_BASE 0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT (0xf)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
+#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
+#define CFG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
*/
#define RTC
#define CONFIG_RTC_DS1337 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/*DVI encoder*/
#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#define CFG_SYS_SGMII1_PHY_ADDR 0x03
#elif defined(CONFIG_TARGET_T1040D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
+#define CFG_SYS_SGMII1_PHY_ADDR 0x01
#elif defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
-#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
-#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
+#define CFG_SYS_SGMII1_PHY_ADDR 0x02
+#define CFG_SYS_SGMII2_PHY_ADDR 0x03
+#define CFG_SYS_SGMII3_PHY_ADDR 0x01
#endif
#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
+#define CFG_SYS_RGMII1_PHY_ADDR 0x04
+#define CFG_SYS_RGMII2_PHY_ADDR 0x05
#else
-#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
+#define CFG_SYS_RGMII1_PHY_ADDR 0x01
+#define CFG_SYS_RGMII2_PHY_ADDR 0x02
#endif
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_VSC9953
#ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
+#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
+#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
#else
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
+#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
+#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
#endif
#endif
#endif
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Dynamic MTD Partition support with mtdparts
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_FLASH_BASE 0xe0000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
+#define CFG_SYS_NOR0_CSPR_EXT (0xf)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR_EXT (0xf)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
#define QIXIS_BASE 0xffdf0000
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_EXT (0xf)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
+#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3 0x0
/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/*
* I2C
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 18
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 18
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 18
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 18
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
+#define CFG_SYS_NOR0_CSPR_EXT (0xf)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS }
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT (0xf)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+#define CFG_SYS_CPLD_BASE 0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT (0xf)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2 0x0
+#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3 0x0
+#define CFG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/*
* I2C
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 18
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 18
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 18
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 18
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST 0x00200000
+#define CFG_SYS_MMC_U_BOOT_START 0x00200000
+#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE 0xe0000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
*/
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
/*
* IFC Definitions
*/
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR0_CSPR_EXT (0xf)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR_EXT (0xf)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CPLD_BASE 0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR3_EXT (0xf)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
+#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
/* I2C */
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 50
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 50
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 50
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 50
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
* 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
*/
#if defined(CONFIG_NOR)
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CFG_SYS_FLASH_BASE (0x08000000)
+#define CFG_SYS_FLASH_SIZE 0x01000000
#endif /* NOR support */
#endif /* ! __CONFIG_AM335X_EVM_H */
/* on one chip */
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#define CFG_SYS_FLASH_BASE NAND_BASE
#endif
#endif /* __CONFIG_H */
#define __CONFIG_AM43XX_EVM_H
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
/* SPL defines. */
/* Enabling L2 Cache */
-#define CONFIG_SYS_PL310_BASE 0x48242000
+#define CFG_SYS_PL310_BASE 0x48242000
/*
* When building U-Boot such that there is no previous loader
* 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
* 0x9E0000 - 0x2000000 : USERLAND
*/
-#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
+#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000
+#define CFG_SYS_SPI_ARGS_OFFS 0x140000
+#define CFG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */
#define CONFIG_HOSTNAME "AMCORE"
-#define CONFIG_SYS_UART_PORT 0
+#define CFG_SYS_UART_PORT 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"upgrade_uboot=loady; " \
"erase 0xfff00000 0xffffffff; " \
"cp.b 0x20000 0xfff00000 ${filesize}\0"
-#define CONFIG_SYS_CLK 45000000
-#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
+#define CFG_SYS_CLK 45000000
+#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 2)
/* Register Base Addrs */
-#define CONFIG_SYS_MBAR 0x10000000
+#define CFG_SYS_MBAR 0x10000000
/* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
/* size of internal SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 0x1000000
-#define CONFIG_SYS_FLASH_BASE 0xffc00000
+#define CFG_SYS_FLASH_BASE 0xffc00000
/* amcore design has flash data bytes wired swapped */
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
/* reserve 128-4KB */
#define LDS_BOARD_TEXT \
env/embedded.o(.text*);
/* memory map space for linux boot data */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CFG_SYS_BOOTMAPSZ (8 << 20)
/*
* Cache Configuration
* sdram - single region - no masks
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
CF_ACR_EN)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
CF_CACR_EC)
/* CS0 - AMD Flash, address 0xffc00000 */
-#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
+#define CFG_SYS_CS0_BASE (CFG_SYS_FLASH_BASE>>16)
/* 4MB, AA=0,V=1 C/I BIT for errata */
-#define CONFIG_SYS_CS0_MASK 0x003f0001
+#define CFG_SYS_CS0_MASK 0x003f0001
/* WS=10, AA=1, PS=16bit (10) */
-#define CONFIG_SYS_CS0_CTRL 0x1980
+#define CFG_SYS_CS0_CTRL 0x1980
/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
-#define CONFIG_SYS_CS1_BASE 0x3000
-#define CONFIG_SYS_CS1_MASK 0x00070001
-#define CONFIG_SYS_CS1_CTRL 0x0100
+#define CFG_SYS_CS1_BASE 0x3000
+#define CFG_SYS_CS1_MASK 0x00070001
+#define CFG_SYS_CS1_CTRL 0x0100
#endif /* __AMCORE_CONFIG_H */
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* Miscellaneous configurable options */
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE 0x2000
/*
* Serial Port
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE 0x2000
/*
* Serial Port
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */
#define __CONFIG_ARBEL_H
#define CFG_SYS_SDRAM_BASE 0x0
-#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
-#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_BOOTMAPSZ (20 << 20)
+#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */
#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
#endif
/* Framebuffer */
-#define CONFIG_SYS_LDB_CLOCK 28341000
+#define CFG_SYS_LDB_CLOCK 28341000
#include "mx6_common.h"
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#ifdef CONFIG_PRE_CON_BUF_SZ
-#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
-#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
+#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
+#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
#else
-#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
-#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
+#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
#endif
/*
* interface etc.
*/
-#define CONFIG_SYS_CLK 80000000
-#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
+#define CFG_SYS_CLK 80000000
+#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3)
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
/*
* Define baudrate for UART1 (console output, tftp, ...)
* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
- * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
+ * CFG_SYS_BAUDRATE_TABLE defines values that can be selected
* in u-boot command interface
*/
-#define CONFIG_SYS_UART_PORT (2)
-#define CONFIG_SYS_UART2_ALT3_GPIO
+#define CFG_SYS_UART_PORT (2)
+#define CFG_SYS_UART2_ALT3_GPIO
/*
* Watchdog configuration; Watchdog is disabled for running from RAM
* it needs non-blocking CFI routines.
*/
-#define CONFIG_SYS_FPGA_WAIT 1000
+#define CFG_SYS_FPGA_WAIT 1000
/* End of user parameters to be customized */
/* Base register address */
-#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
+#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
/* System Conf. Reg. & System Protection Reg. */
-#define CONFIG_SYS_SCR 0x0003;
-#define CONFIG_SYS_SPR 0xffff;
+#define CFG_SYS_SCR 0x0003;
+#define CFG_SYS_SPR 0xffff;
/*
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
* CS4 - unused
* CS5 - unused
*/
-#define CONFIG_SYS_CS0_BASE 0
-#define CONFIG_SYS_CS0_MASK 0x00ff0001
-#define CONFIG_SYS_CS0_CTRL 0x00001fc0
+#define CFG_SYS_CS0_BASE 0
+#define CFG_SYS_CS0_MASK 0x00ff0001
+#define CFG_SYS_CS0_CTRL 0x00001fc0
-#define CONFIG_SYS_CS1_BASE 0x01000000
-#define CONFIG_SYS_CS1_MASK 0x00ff0001
-#define CONFIG_SYS_CS1_CTRL 0x00001fc0
+#define CFG_SYS_CS1_BASE 0x01000000
+#define CFG_SYS_CS1_MASK 0x00ff0001
+#define CFG_SYS_CS1_CTRL 0x00001fc0
-#define CONFIG_SYS_CS2_BASE 0x20000000
-#define CONFIG_SYS_CS2_MASK 0x00ff0001
-#define CONFIG_SYS_CS2_CTRL 0x0000fec0
+#define CFG_SYS_CS2_BASE 0x20000000
+#define CFG_SYS_CS2_MASK 0x00ff0001
+#define CFG_SYS_CS2_CTRL 0x0000fec0
-#define CONFIG_SYS_CS3_BASE 0x21000000
-#define CONFIG_SYS_CS3_MASK 0x00ff0001
-#define CONFIG_SYS_CS3_CTRL 0x0000fec0
+#define CFG_SYS_CS3_BASE 0x21000000
+#define CFG_SYS_CS3_MASK 0x00ff0001
+#define CFG_SYS_CS3_CTRL 0x0000fec0
-#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CFG_SYS_FLASH_BASE 0x00000000
/* Reserve 256 kB for Monitor */
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
(CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CONFIG_SYS_FLASH_SIZE 0x2000000
+#define CFG_SYS_FLASH_SIZE 0x2000000
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
#endif /* _CONFIG_ASTRO_MCF5373L_H */
#include <linux/kconfig.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#endif
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/*
* SDRAM: 1 bank, min 32, max 128 MB
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
#ifdef CONFIG_AT91SAM9XE
-# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
+# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
#else
-# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
#endif
/* NAND flash */
#endif
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
#endif
#define __CONFIG_H
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#include <asm/hardware.h>
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_DM9000_NO_SROM
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
#endif
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
/* SDRAM */
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NOR flash, if populated */
#ifdef CONFIG_SYS_USE_NORFLASH
#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* Address and size of Primary Environment Sector */
#define MASTER_PLL_OUT 3
/* clocks */
-#define CONFIG_SYS_MOR_VAL \
+#define CFG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
-#define CONFIG_SYS_PLLAR_VAL \
+#define CFG_SYS_PLLAR_VAL \
(AT91_PMC_PLLAR_29 | \
AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
AT91_PMC_PLLXR_PLLCOUNT(63) | \
AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
+#define CFG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
+#define CFG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
+#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
+#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
+#define CFG_SYS_MATRIX_EBICSA_VAL \
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1 0
+#define CFG_SYS_SDRC_MR_VAL1 0
/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
+#define CFG_SYS_SDRC_TR_VAL1 0x13C
/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
+#define CFG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
(1 << 28)) /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
+#define CFG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
+#define CFG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+#define CFG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
+#define CFG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_MODE_DBW_16 | \
AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
+#define CFG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_MR_URSTEN | \
AT91_RSTC_MR_ERSTL(15))
/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
+#define CFG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_MR_WDV(0xfff) | \
AT91_WDT_MR_WDDIS | \
#endif
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#endif
#define __CONFIG_H
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x70000000
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
#define __AT91SAM9N12_CONFIG_H_
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */
#define CFG_SYS_SDRAM_BASE 0x20000000
/* SPL */
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20953f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20953f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define __CONFIG_H__
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* general purpose I/O */
/* SPL */
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
/* support JEDEC */
#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
/* max number of memory banks */
/*
* There are 4 banks supported for this Controller,
* but we have only 1 bank connected to flash on board
*/
-#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
+#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
*/
/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
+#define CFG_SYS_BOOTMAPSZ (64 << 20)
/* Increase max gunzip size */
/* Support autoboot from RAM (kernel image is loaded via debug port) */
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_512M
/*
#define CFG_SYS_NS16550_COM1 0xf040c000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000
+#define CFG_SYS_INIT_RAM_ADDR 0x10200000
#include "bcmstb.h"
#define CFG_SYS_NS16550_COM1 0xf040ab00
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000
+#define CFG_SYS_INIT_RAM_ADDR 0x80200000
#include "bcmstb.h"
#define __BCM963138_H
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_HZ_CLOCK 500000000
+#define CFG_SYS_HZ_CLOCK 500000000
#endif
* initramfs images, in which case this limitation is eliminated.
*/
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
+#define CFG_SYS_INIT_RAM_SIZE 0x100000
/*
* CONFIG_SYS_LOAD_ADDR - 1 MiB.
/*
* Serial console configuration.
*/
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/*
#define PHYS_SDRAM_SIZE (SZ_512M)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */
#define CONFIG_SH_QSPI_BASE 0xE6B10000
#else
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
+#define CFG_SYS_FLASH_BASE 0x00000000
+#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
+#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) }
+#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) }
#endif
/* Board Clock */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM3380_H */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6318_H */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM63268_H */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6328_H */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
-#define CONFIG_SYS_FLASH_BASE 0xbfc00000
+#define CFG_SYS_FLASH_BASE 0xbfc00000
#endif /* __CONFIG_BMIPS_BCM6338_H */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
-#define CONFIG_SYS_FLASH_BASE 0xbfc00000
+#define CFG_SYS_FLASH_BASE 0xbfc00000
#endif /* __CONFIG_BMIPS_BCM6348_H */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
-#define CONFIG_SYS_FLASH_BASE 0xbe000000
+#define CFG_SYS_FLASH_BASE 0xbe000000
#endif /* __CONFIG_BMIPS_BCM6358_H */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6362_H */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
-#define CONFIG_SYS_FLASH_BASE 0xb8000000
+#define CFG_SYS_FLASH_BASE 0xb8000000
#endif /* __CONFIG_BMIPS_BCM6368_H */
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6838_H */
#include <linux/sizes.h>
/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 500000, 1500000 }
#endif /* __CONFIG_BMIPS_COMMON_H */
# define CFG_SYS_SDRAM_BASE 0x80000000
#endif
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/*
* Console
/* -- i.mx6 specifica -- */
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
+#define CFG_SYS_PL310_BASE L2_PL310_BASE
#endif /* !CONFIG_SYS_L2CACHE_OFF */
#define CONFIG_MXC_GPT_HCLK
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Ethernet */
#define CONFIG_FEC_FIXED_SPEED _1000BASET
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
/* Flat Device Tree Definitions */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
/* Memory configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* NS16550-ish UARTs */
#define CFG_SYS_NS16550_CLK 48000000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
+#define CFG_SYS_I2C_PCA953X_ADDR 0x20
+#define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
#undef CONFIG_EXTRA_ENV_SETTINGS
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* SPI Flash support */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Serial console */
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONFIG_MXC_USB_FLAGS 0
/* Boot */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CFG_SYS_BOOTMAPSZ (8 << 20)
/* misc */
#define __CONFIG_CM_T43_H
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
#define CONFIG_POWER_TPS65218
/* Enabling L2 Cache */
-#define CONFIG_SYS_PL310_BASE 0x48242000
+#define CFG_SYS_PL310_BASE 0x48242000
/*
* Since SPL did pll and ddr initialization for us,
* ---
*/
-#define CONFIG_SYS_CLK 66000000
+#define CFG_SYS_CLK 66000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/* ---
* Define baudrate for UART1 (console output, tftp, ...)
* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
- * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
+ * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
* interface
* ---
*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
/* ---
* set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
* ---
*/
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
/* ---
* System Conf. Reg. & System Protection Reg.
* ---
*/
-#define CONFIG_SYS_SCR 0x0003
-#define CONFIG_SYS_SPR 0xffff
+#define CFG_SYS_SCR 0x0003
+#define CFG_SYS_SPR 0xffff
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
*-----------------------------------------------------------------------
*/
-#define CONFIG_SYS_FLASH_BASE 0xffe00000
+#define CFG_SYS_FLASH_BASE 0xffe00000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Port configuration (GPIO)
*/
-#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
+#define CFG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
GPIO*/
-#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
+#define CFG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
(1^=output, 0^=input) */
-#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
-#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
+#define CFG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
+#define CFG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
configuration */
-#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
-#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
-#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
+#define CFG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
+#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
+#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
#endif /* _CONFIG_COBRA5272_H */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
/* NAND stuff */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
/* NAND stuff */
#define PHYS_SDRAM_SIZE (256 * SZ_1M)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* USB Host Support */
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* serial console */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_MASTER_CLOCK 132096000
#define AT91_PLL_LOCK_TIMEOUT 1000000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
/*
* SoC Configuration
*/
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_OSCIN_FREQ 24000000
+#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
+#define CFG_SYS_DV_NOR_BOOT_CFG (0x11)
#endif
/*
/* memtest will be run on 16MB */
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
+#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
DAVINCI_SYSCFG_SUSPSRC_UART2 | \
* PLL configuration
*/
-#define CONFIG_SYS_DA850_PLL0_PLLM 24
-#define CONFIG_SYS_DA850_PLL1_PLLM 21
+#define CFG_SYS_DA850_PLL0_PLLM 24
+#define CFG_SYS_DA850_PLL1_PLLM 21
/*
* DDR2 memory configuration
*/
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
DV_DDR_PHY_EXT_STRBEN | \
(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
+#define CFG_SYS_DA850_DDR2_SDBCR ( \
(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+#define CFG_SYS_DA850_DDR2_SDBCR2 0
-#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
+#define CFG_SYS_DA850_DDR2_SDTIMR ( \
(14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
(0 << DV_DDR_SDTMR1_WTR_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
+#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \
(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
(0 << DV_DDR_SDTMR2_XP_SHIFT) | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
(0 << DV_DDR_SDTMR2_CKE_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
-#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
+#define CFG_SYS_DA850_DDR2_SDRCR 0x00000494
+#define CFG_SYS_DA850_DDR2_PBBPR 0x30
/*
* Serial Driver info
*/
#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/*
* I2C Configuration
*/
-#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
/*
* Flash & Environment
#endif
#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define CFG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
#endif
#define PHYS_SDRAM_SIZE SZ_512M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
/*
* NOR Flash
*/
-#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
-#define CONFIG_SYS_FLASH_SIZE SZ_4M
+#define CFG_SYS_FLASH_BASE EMC_CS0_BASE
+#define CFG_SYS_FLASH_SIZE SZ_4M
/*
* NAND controller
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment */
*/
/* Below values are "dummy" - only to avoid build break */
-#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000
+#define CFG_SYS_SPI_KERNEL_OFFS 0x150000
+#define CFG_SYS_SPI_ARGS_OFFS 0x140000
+#define CFG_SYS_SPI_ARGS_SIZE 0x10000
#define CONFIG_MXC_UART_BASE UART5_BASE
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* ENV config */
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
* 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
* 0x9E0000 - 0x2000000 : USERLAND
*/
-#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
+#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000
+#define CFG_SYS_SPI_ARGS_OFFS 0x140000
+#define CFG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */
/* Parallel NOR Support */
#if defined(CONFIG_NOR)
/* NOR: device related configs */
-#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CFG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
+#define CFG_SYS_FLASH_BASE (0x08000000)
/* Reduce SPL size by removing unlikey targets */
#endif /* NOR support */
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __DRAAK_H */
#include <linux/sizes.h>
#include <asm/arch/sysmap-sdm845.h>
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x5000000\0" \
* High Level Configuration Options (easy to change) *
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
* Environment is in the second sector of the first 256k of flash *
*----------------------------------------------------------------------*/
-/*#define CONFIG_SYS_DRAM_TEST 1 */
-#undef CONFIG_SYS_DRAM_TEST
+/*#define CFG_SYS_DRAM_TEST 1 */
+#undef CFG_SYS_DRAM_TEST
/*----------------------------------------------------------------------*
* Clock and PLL Configuration *
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
+#define CFG_SYS_CLK 80000000 /* 8MHz * 8 */
/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
-#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
+#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
+#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*----------------------------------------------------------------------*
* Network *
* You should know what you are doing if you make changes here.
*-----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBAR 0x40000000
+#define CFG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*-----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
+#define CFG_SYS_INT_FLASH_BASE 0xF0000000
+#define CFG_SYS_INT_FLASH_ENABLE 0x21
-#define CONFIG_SYS_FLASH_SIZE 16*1024*1024
+#define CFG_SYS_FLASH_SIZE 16*1024*1024
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
CF_CACR_EUSP)
* Memory bank definitions
*/
-#define CONFIG_SYS_CS0_BASE 0xFF000000
-#define CONFIG_SYS_CS0_CTRL 0x00001980
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
+#define CFG_SYS_CS0_BASE 0xFF000000
+#define CFG_SYS_CS0_CTRL 0x00001980
+#define CFG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS2_BASE 0xE0000000
-#define CONFIG_SYS_CS2_CTRL 0x00001980
-#define CONFIG_SYS_CS2_MASK 0x000F0001
+#define CFG_SYS_CS2_BASE 0xE0000000
+#define CFG_SYS_CS2_CTRL 0x00001980
+#define CFG_SYS_CS2_MASK 0x000F0001
-#define CONFIG_SYS_CS3_BASE 0xE0100000
-#define CONFIG_SYS_CS3_CTRL 0x00001980
-#define CONFIG_SYS_CS3_MASK 0x000F0001
+#define CFG_SYS_CS3_BASE 0xE0100000
+#define CFG_SYS_CS3_CTRL 0x00001980
+#define CFG_SYS_CS3_MASK 0x000F0001
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
-#define CONFIG_SYS_PADDR 0x0000000
-#define CONFIG_SYS_PADAT 0x0000000
+#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
+#define CFG_SYS_PADDR 0x0000000
+#define CFG_SYS_PADAT 0x0000000
-#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
-#define CONFIG_SYS_PBDDR 0x0000000
-#define CONFIG_SYS_PBDAT 0x0000000
+#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
+#define CFG_SYS_PBDDR 0x0000000
+#define CFG_SYS_PBDAT 0x0000000
-#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
+#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
-#define CONFIG_SYS_PASPAR 0x0F0F
-#define CONFIG_SYS_PEHLPAR 0xC0
-#define CONFIG_SYS_PUAPAR 0x0F
-#define CONFIG_SYS_DDRUA 0x05
-#define CONFIG_SYS_PJPAR 0xFF
+#define CFG_SYS_PASPAR 0x0F0F
+#define CFG_SYS_PEHLPAR 0xC0
+#define CFG_SYS_PUAPAR 0x0F
+#define CFG_SYS_DDRUA 0x05
+#define CFG_SYS_PJPAR 0xFF
/*-----------------------------------------------------------------------
* I2C
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __EBISU_H */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+#define CFG_SYS_STACK_SIZE (32 * 1024)
#endif
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
/* NAND specific changes for etamin due to different page size */
#undef CFG_SYS_NAND_ECCPOS
-#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */
+#define CFG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
/* CPU information */
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
/* 32kB internal SRAM */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */
-#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10)
+#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */
+#define CFG_SYS_INIT_RAM_SIZE (32 << 10)
/* 128MB SDRAM in 1 bank */
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE (128 << 20)
/* 512kB on-chip NOR flash */
-# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
+# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
+#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
#endif
/* RTC */
#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+#define CFG_SYS_I2C_RTC_ADDR 0x51
#endif
/* I2C */
-#define CONFIG_SYS_MAX_I2C_BUS 1
+#define CFG_SYS_MAX_I2C_BUS 1
#define I2C_SOFT_DECLARATIONS
#include <configs/aspeed-common.h>
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* Misc */
#define CONFIG_EXTRA_ENV_SETTINGS \
#include <configs/aspeed-common.h>
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* Misc */
#define STR_HELPER(s) #s
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define CONFIG_SYS_SPI_BASE 0x12D30000
+#define CFG_SYS_SPI_BASE 0x12D30000
#define FLASH_SIZE (4 << 20)
#define CONFIG_SPI_BOOTING
#define CPU_RELEASE_ADDR secondary_boot_addr
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
#define CFG_SYS_SDRAM_BASE 0x40000000
#endif
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
/* SPL */
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000
#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* RAM */
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#endif
/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* RAM */
*/
#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
/* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */
-#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE
/*
* Memory test
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
+#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CFG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Command definition */
#define CONFIG_EXTRA_ENV_SETTINGS \
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/*
* MTD Command for mtdparts
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
+#define CFG_SYS_BOOTMAPSZ (16 << 20)
#define CONFIG_PL011_CLOCK 150000000
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0xf6801000
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0xe82b1000
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_1G
/*
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_1G
/*
/* CS2 Base address */
#define PHYS_FLASH_1 0xc0000000
/* Flash Base for U-Boot */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* Address and size of Redundant Environment Sector */
/*
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* UART */
#ifdef CONFIG_MXC_UART
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __IMX6DL_MAMOJ_CONFIG_H */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* SPL */
#ifdef CONFIG_SPL
#define PHYS_SDRAM_SIZE SZ_128M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Config*/
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#include <asm/arch/imx-regs.h>
#include <config_distro_bootcmd.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#endif
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define UBOOT_ITB_OFFSET_FSPI \
(UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE)
#ifdef CONFIG_FSPI_CONF_HEADER
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI)
#else
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#endif
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
"splblk=0x42\0" \
BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Initial environment variables */
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define MEM_LAYOUT_ENV_SETTINGS \
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define BOOT_TARGET_DEVICES(func) \
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define BOOT_TARGET_DEVICES(func) \
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Enable Distro Boot */
"splblk=0x40\0" \
BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
#include <asm/arch/imx-regs.h>
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */
#define CFG_SYS_SDRAM_BASE 0x40000000
#include <asm/arch/imx-regs.h>
#include <config_distro_bootcmd.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* GUIDs for capsule updatable firmware images */
#define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \
"fi;\0"
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 6GB or 4G DDR */
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* Enable Distro Boot */
"splblk=0x40\0" \
BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#define CFG_SYS_SDRAM_BASE 0x40000000
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_MALLOC_F_ADDR 0x22040000
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x80000000
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_UBOOT_START 0x800023FD
+#define CFG_SYS_UBOOT_START 0x800023FD
#endif /* __IMXRT1020_EVK_H */
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_UBOOT_START 0x800023FD
+#define CFG_SYS_UBOOT_START 0x800023FD
#endif /* __IMXRT1050_EVK_H */
#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
DMAMEM_SZ_ALL)
/* For SPL */
-#define CONFIG_SYS_UBOOT_START 0x202403FD
+#define CFG_SYS_UBOOT_START 0x202403FD
/* For SPL ends */
#endif /* __IMXRT1170_EVK_H */
* Common ARM Integrator configuration settings
*/
-#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
+#define CFG_SYS_TIMERBASE 0x13000100 /* Timer1 */
/*
* The ARM boot monitor initializes the board.
* - SIB block
* - U-Boot environment
*/
-#define CONFIG_SYS_FLASH_BASE 0x24000000
+#define CFG_SYS_FLASH_BASE 0x24000000
/* Timeout values in ticks */
#include "integrator-common.h"
/* Integrator/AP-specific configuration */
-#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
+#define CFG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
/* Flash settings */
-#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
+#define CFG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
/*-----------------------------------------------------------------------
* PCI definitions
#include "integrator-common.h"
/* Integrator CP-specific configuration */
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
#define CONFIG_SERVERIP 192.168.1.100
#define CONFIG_IPADDR 192.168.1.104
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* FLASH Configuration */
-#define CONFIG_SYS_FLASH_BASE 0x000000000
+#define CFG_SYS_FLASH_BASE 0x000000000
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
-#define CONFIG_SYS_UBOOT_BASE 0x50280000
+#define CFG_SYS_UBOOT_BASE 0x50280000
/* Image load address in RAM for DFU boot*/
#else
-#define CONFIG_SYS_UBOOT_BASE 0x50080000
+#define CFG_SYS_UBOOT_BASE 0x50080000
#endif
/* HyperFlash related configuration */
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
-#define CONFIG_SYS_UBOOT_BASE 0x50280000
+#define CFG_SYS_UBOOT_BASE 0x50280000
/* Image load address in RAM for DFU boot*/
#else
-#define CONFIG_SYS_UBOOT_BASE 0x50080000
+#define CFG_SYS_UBOOT_BASE 0x50080000
#endif
/* U-Boot general configuration */
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
/*
* System IO Config
*/
-#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
+#define CFG_SYS_SICRL SICRL_IRQ_CKS
-#define CONFIG_SYS_DDRCDR (\
+#define CFG_SYS_DDRCDR (\
DDRCDR_EN | \
DDRCDR_PZ_MAXZ | \
DDRCDR_NZ_MAXZ | \
DDRCDR_M_ODR)
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+#define CFG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_32_BE | \
SDRAM_CFG_SREN | \
SDRAM_CFG_HSE)
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ODT_WR_CFG | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_MODE 0x47860242
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
+#define CFG_SYS_DDR_MODE 0x47860242
+#define CFG_SYS_DDR_MODE2 0x8080c000
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
+#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
(3 << TIMING_CFG1_WRREC_SHIFT) | \
(7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(3 << TIMING_CFG1_PRETOACT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
(5 << TIMING_CFG2_CPO_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CFG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CFG_SYS_KMBEC_FPGA_SIZE 128
/* KMBEC FPGA (PRIO) */
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
+#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CFG_SYS_KMBEC_FPGA_SIZE 64
/*
* High Level Configuration Options
/*
* System IO Setup
*/
-#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
+#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
/**
* DDR RAM settings
*/
-#define CONFIG_SYS_DDR_SDRAM_CFG (\
+#define CFG_SYS_DDR_SDRAM_CFG (\
SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_SREN | \
SDRAM_CFG_HSE)
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (\
+#define CFG_SYS_DDR_CLK_CNTL (\
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL (\
+#define CFG_SYS_DDR_INTERVAL (\
(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CFG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDRCDR (\
+#define CFG_SYS_DDRCDR (\
DDRCDR_EN | \
DDRCDR_Q_DRN)
-#define CONFIG_SYS_DDR_MODE 0x47860452
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
+#define CFG_SYS_DDR_MODE 0x47860452
+#define CFG_SYS_DDR_MODE2 0x8080c000
-#define CONFIG_SYS_DDR_TIMING_0 (\
+#define CFG_SYS_DDR_TIMING_0 (\
(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
+#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
(3 << TIMING_CFG1_WRREC_SHIFT) | \
(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(3 << TIMING_CFG1_PRETOACT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_2 (\
+#define CFG_SYS_DDR_TIMING_2 (\
(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(5 << TIMING_CFG2_CPO_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CFG_SYS_DDR_TIMING_3 0x00000000
/* EEprom support */
/*
* PAXE on the local bus CS3
*/
-#define CONFIG_SYS_PAXE_BASE 0xA0000000
+#define CFG_SYS_PAXE_BASE 0xA0000000
*/
#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_83XX_DDR_USES_CS0
/*
* The reserved memory
*/
-#define CONFIG_SYS_FLASH_BASE 0xF0000000
+#define CFG_SYS_FLASH_BASE 0xF0000000
/* Reserve 768 kB for Mon */
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
/*
* Init Local Bus Memory Controller:
*
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
+#define CFG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
/* I2C */
#define CFG_SYS_NUM_I2C_BUSES 4
-#define CONFIG_SYS_I2C_MAX_HOPS 1
-#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
+#define CFG_SYS_I2C_MAX_HOPS 1
+#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
{1, {I2C_NULL_HOP} } }
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
-#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
+#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE
#endif
/*
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CFG_SYS_BOOTMAPSZ (8 << 20)
/*
* Environment
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
CONFIG_KM_PHRAM + \
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
/* POST memory regions test */
-#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST (CFG_SYS_POST_MEM_REGIONS)
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
/*
* IFC Definitions
*/
/* NOR Flash Definitions */
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_TE | \
CSPR_MSEL_NOR | \
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* NAND Flash Definitions */
#define CFG_SYS_NAND_BASE 0x68000000
FTIM2_NAND_TWHRE(0x3c))
#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */
-#define CONFIG_SYS_QRIO_BASE 0x70000000
-#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
+#define CFG_SYS_QRIO_BASE 0x70000000
+#define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE
-#define CONFIG_SYS_CSPR2_EXT (0x00)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+#define CFG_SYS_CSPR2_EXT (0x00)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_TE | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_20 | \
CSOR_GPCM_BCTLD)
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
FTIM0_GPCM_TEADC(0x8) | \
FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x6))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x7))
-#define CONFIG_SYS_CS2_FTIM3 0x04000000
+#define CFG_SYS_CS2_FTIM3 0x04000000
/*
* Serial Port
*/
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CFG_SYS_I2C_MAX_HOPS 1
#define CFG_SYS_NUM_I2C_BUSES 3
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x0
-#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
+#define CFG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
{1, {I2C_NULL_HOP} }, \
}
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize}\0" \
- "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
- "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "erase " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
"cp.b ${load_addr_r} " \
- __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
"set_fdthigh=true\0" \
"ethrotate=no\0" \
""
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
#endif
#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
/* Application IFC CS4 MRAM */
-#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
+#define CFG_SYS_MRAM_BASE SYS_LAWAPP_BASE
#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
#define SYS_MRAM_CSPR_EXT (0x0f)
-#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
+#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \
CSPR_PORT_SIZE_8 | /* 8 bit */ \
CSPR_MSEL_GPCM | /* msel = gpcm */ \
CSPR_V /* bank is valid */)
FTIM2_GPCM_TCH(0x2) | \
FTIM2_GPCM_TWP(0x8))
#define SYS_MRAM_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
-#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
-#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
-#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
-#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
-#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
-#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
-#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
+#define CFG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
+#define CFG_SYS_CSPR4 SYS_MRAM_CSPR
+#define CFG_SYS_AMASK4 SYS_MRAM_AMASK
+#define CFG_SYS_CSOR4 SYS_MRAM_CSOR
+#define CFG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
+#define CFG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
+#define CFG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
+#define CFG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
/* Application IFC CS6: BFTIC */
#define SYS_BFTIC_BASE 0xd0000000
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
#define SYS_BFTIC_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
-#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
-#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
-#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
-#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
-#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
-#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
-#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
+#define CFG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
+#define CFG_SYS_CSPR6 SYS_BFTIC_CSPR
+#define CFG_SYS_AMASK6 SYS_BFTIC_AMASK
+#define CFG_SYS_CSOR6 SYS_BFTIC_CSOR
+#define CFG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
+#define CFG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
+#define CFG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
+#define CFG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
/* Application IFC CS7 PAXE */
-#define CONFIG_SYS_PAXE_BASE 0xd8000000
-#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
+#define CFG_SYS_PAXE_BASE 0xd8000000
+#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CFG_SYS_PAXE_BASE)
#define SYS_PAXE_CSPR_EXT (0x0f)
-#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
+#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \
CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
CSPR_MSEL_GPCM | /* MSEL = GPCM */\
CSPR_V) /* valid */
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
#define SYS_PAXE_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
-#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
-#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
-#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
-#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
-#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
-#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
-#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
+#define CFG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
+#define CFG_SYS_CSPR7 SYS_PAXE_CSPR
+#define CFG_SYS_AMASK7 SYS_PAXE_AMASK
+#define CFG_SYS_CSOR7 SYS_PAXE_CSOR
+#define CFG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
+#define CFG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
+#define CFG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
+#define CFG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
/* PRST */
#define KM_BFTIC4_RST 0
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
/* POST memory regions test */
-#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
+#define CONFIG_POST CFG_SYS_POST_MEM_REGIONS
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#define CFG_SYS_DCSRBAR 0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
* IFC Definitions
*/
/* NOR flash on IFC CS0 */
-#define CONFIG_SYS_FLASH_BASE 0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
- CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE 0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
+ CFG_SYS_FLASH_BASE)
#define CFG_SYS_NOR_CSPR_EXT (0x0f)
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
0x00000010 | /* drive TE high */\
CSPR_MSEL_NOR | /* MSEL = NOR */\
FTIM2_NOR_TWPH(0x6))
#define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* More NOR Flash params */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC CS1*/
#define CFG_SYS_NAND_BASE 0xfa000000
FTIM2_NAND_TWHRE(0x3c))
#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
/* More NAND Flash Params */
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO on IFC CS2 */
-#define CONFIG_SYS_QRIO_BASE 0xfb000000
-#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
+#define CFG_SYS_QRIO_BASE 0xfb000000
+#define CFG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CFG_SYS_QRIO_BASE)
#define SYS_QRIO_CSPR_EXT (0x0f)
-#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
0x00000010 | /* drive TE high */\
CSPR_MSEL_GPCM | /* MSEL = GPCM */\
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x7))
#define SYS_QRIO_FTIM3 0x04000000
-#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
-#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
-#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
-#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
-#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
+#define CFG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
+#define CFG_SYS_CSPR2 SYS_QRIO_CSPR
+#define CFG_SYS_AMASK2 SYS_QRIO_AMASK
+#define CFG_SYS_CSOR2 SYS_QRIO_CSOR
+#define CFG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
+#define CFG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
+#define CFG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
+#define CFG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port - controlled on board with jumper J8
*/
#if !defined(CONFIG_DM_SERIAL)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x11C500)
#endif
#ifndef __ASSEMBLY__
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS 10
+#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
+ CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS 10
+#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
+ CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
/* Qman / Bman */
/* RGMII (FM1@DTESC5) is local managemant interface */
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
+#define CFG_SYS_RGMII2_PHY_ADDR 0x11
/*
* Hardware Watchdog
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize}\0" \
- "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
- "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "erase " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
"cp.b ${load_addr_r} " \
- __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
"set_fdthigh=true\0" \
#define CONFIG_NAND_ECC_BCH
#define CONFIG_NAND_KMETER1
#define NAND_MAX_CHIPS 1
-#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/**
* KMCOGE5NE has 512 MB RAM
*/
-#define CONFIG_SYS_DDR_CS0_CONFIG (\
+#define CFG_SYS_DDR_CS0_CONFIG (\
CSCONFIG_EN | \
CSCONFIG_AP | \
CSCONFIG_ODT_WR_ONLY_CURRENT | \
CSCONFIG_COL_BIT_10)
/* enable POST tests */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS)
#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
#include "km/km-mpc83xx.h"
#include "km/km-mpc8360.h"
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10 | \
CSCONFIG_ODT_WR_ONLY_CURRENT)
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* Board and environment settings */
#define CONFIG_MXC_UART_BASE UART4_BASE
#define PHYS_SDRAM_SIZE (SZ_4G)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
/* Board and environment settings */
#define CONFIG_HOSTNAME "kontron-mx8mm"
BOOTENV
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
/* we don't have secure memory unless we have a BL31 */
#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
-#undef CONFIG_SYS_MEM_RESERVE_SECURE
+#undef CFG_SYS_MEM_RESERVE_SECURE
#endif
/* DDR */
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/* early stack pointer */
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment */
#ifdef CONFIG_CMD_I2C
/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
#if defined(CONFIG_NET2BIG_V2)
-#define CONFIG_SYS_I2C_G762_ADDR 0x3e
+#define CFG_SYS_I2C_G762_ADDR 0x3e
#endif
#endif /* CONFIG_CMD_I2C */
/*
* SoC Configuration
*/
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_OSCIN_FREQ 24000000
+#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/*
* Memory Info
*/
#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
+#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
/*
* U-Boot general configuration
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
/* RAM */
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#endif
/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* RAM */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* FLASH and environment organization */
#include <asm/arch/stream_id_lsch2.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/*SPI device */
#define CFG_SYS_FSL_QSPI_BASE 0x40000000
*/
#ifdef CONFIG_FSL_QIXIS
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_BRDCFG_REG 0x04
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x08
* RTC configuration
*/
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* Voltage monitor on channel 2*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/*
* DDR: 800 MHz ( 1600 MT/s data rate )
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG_BI 0x00000001
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/*
* Serial Port
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#ifdef CONFIG_NAND_BOOT
#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10)
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT (0x0)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
#define CFG_SYS_NOR_FTIM3 0
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
- CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
+ CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
/*
* NAND Flash Definitions
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_PWR_CTL2 0x21
#define QIXIS_PWR_CTL2_PCTL 0x2
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/*
* QIXIS Timing parameters for IFC GPCM
*/
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
FTIM0_GPCM_TEADC(0xe) | \
FTIM0_GPCM_TEAHC(0xe))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
FTIM2_GPCM_TCH(0xe) | \
FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_FPGA_FTIM3 0x0
#endif
#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#endif
/*
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/* XHCI Support - enabled by default */
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* Serial Port */
#define CFG_SYS_NS16550_CLK get_serial_clock()
"bootm $load_addr#$board\0"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif
/* CPLD */
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE 0x7fb00000
+#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
FTIM0_GPCM_TEADC(0xf) | \
FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_FPGA_FTIM3
/*
* Serial Port
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CFG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_LS102XA_STREAM_ID
/* Link Definitions */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/*
* SMP Definitinos
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 1
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 5
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
#endif
/* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM 1
+#define CFG_SYS_RTC_BUS_NUM 1
#define I2C_MUX_CH_RTC 0xB
/* Store environment at top of flash */
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CFG_SYS_RTC_BUS_NUM 0
/* Store environment at top of flash */
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 2
#define QIXIS_LBMAP_MASK 0xe0
#define QIXIS_LBMAP_SHIFT 0x5
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
#endif
/* Link Definitions */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
#if defined(CONFIG_TFABOOT) || \
(!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
/*
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
* CONFIG_TEXT_BASE is linked to 0x60000000 for booting
*/
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* FMan ucode */
#ifndef SPL_NO_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CFG_SYS_FM_MURAM_SIZE 0x60000
#endif
#endif
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT (0x0)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
- CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
+ CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
/*
* NAND Flash Definitions
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/*
* QIXIS Timing parameters for IFC GPCM
*/
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
FTIM0_GPCM_TEADC(0x20) | \
FTIM0_GPCM_TEAHC(0x10))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_FPGA_FTIM3 0x0
#endif
#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#endif
#endif
#define CFG_SYS_NOR_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
FTIM2_NOR_TWPH(0x8) | \
FTIM2_NOR_TWP(0x10))
#define CFG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
/*
* NAND Flash Definitions
/*
* CPLD
*/
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE 0x7fb00000
+#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
-#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_CPLD_CSPR_EXT (0x0)
+#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
+#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
FTIM0_GPCM_TEADC(0xf) | \
FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_CPLD_FTIM3 0x0
+#define CFG_SYS_CPLD_FTIM3 0x0
/* IFC Timing Params */
#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#endif
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3
/*
* Environment
/* Link Definitions */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
/* FMan ucode */
#ifndef SPL_NO_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CFG_SYS_FM_MURAM_SIZE 0x60000
#endif
#endif
#include "ls1046a_common.h"
-#define CONFIG_SYS_UBOOT_BASE 0x40100000
+#define CFG_SYS_UBOOT_BASE 0x40100000
/*
* NAND Flash Definitions
#define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
/* EEPROM */
#define I2C_RETIMER_ADDR 0x18
/* RTC */
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
+#define CFG_SYS_RTC_BUS_NUM 0
/*
* Environment
/* IFC */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
/*
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
* CONFIG_TEXT_BASE is linked to 0x60000000 for booting
*/
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT (0x0)
+#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
- CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
+ CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
/*
* NAND Flash Definitions
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define QIXIS_BASE_PHYS QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)
/*
* QIXIS Timing parameters for IFC GPCM
*/
-#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
+#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
FTIM0_GPCM_TEADC(0x20) | \
FTIM0_GPCM_TEAHC(0x10))
-#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
+#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
+#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3 0x0
+#define CFG_SYS_FPGA_FTIM3 0x0
#endif
#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
#endif
#endif
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_UBOOT_BASE 0x40100000
+#define CFG_SYS_UBOOT_BASE 0x40100000
#endif
#define CFG_SYS_NAND_BASE 0x7e800000
/*
* CPLD
*/
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE 0x7fb00000
+#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
-#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
-#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_CPLD_CSPR_EXT (0x0)
+#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
+#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CPLD_FTIM3 0x0
+#define CFG_SYS_CPLD_FTIM3 0x0
/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3
/* EEPROM */
#define I2C_RETIMER_ADDR 0x18
#define CFG_SYS_FSL_QSPI_BASE 0x20000000
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
* SMP Definitinos
*/
* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
*
* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
* CONFIG_TEXT_BASE is linked to 0x30000000 for booting
*/
-#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
-#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+#define CFG_SYS_FLASH_BASE 0x580000000ULL
+#define CFG_SYS_FLASH_BASE_PHYS 0x80000000
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
+#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000
+#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
-#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
-#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
+#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
/*
* Carve out a DDR region which will not be used by u-boot/Linux
*/
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Miscellaneous configurable options */
* IFC Definitions
*/
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR1_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
FTIM2_NOR_TWPH(0xe) | \
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\
+ CFG_SYS_FLASH_BASE + 0x40000000}
#endif
#endif
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define QIXIS_QMAP_MASK 0xe0
#define QIXIS_QMAP_SHIFT 5
#define QIXIS_SDID_MASK 0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
+#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
#else
-#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
#endif
/* QIXIS Timing parameters*/
#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
#define SYS_FPGA_CS_FTIM3 0x0
#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK3 SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK2 SYS_FPGA_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK3 SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
#endif
#endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
* I2C bus multiplexer
* RTC configuration
*/
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#ifdef CONFIG_FSL_DSPI
#if !defined(CONFIG_TFABOOT) && \
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
FTIM2_NOR_TCH(0x0) | \
FTIM2_NOR_TWP(0x1))
#define CFG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
#endif
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_BRDCFG4_OFFSET 0x54
#define QIXIS_LBMAP_SWITCH 2
#define QIXIS_QMAP_MASK 0xe0
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
-#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_FPGA_CSPR_EXT (0x0)
+#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
+#define CFG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
/* QIXIS Timing parameters*/
#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK2 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define I2C_MUX_CH_VOL_MONITOR 0xA
/* Voltage monitor on channel 2*/
* RTC configuration
*/
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#endif
#ifndef SPL_NO_ENV
/* Link Definitions */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
* SMP Definitinos
* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
*
* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
* CONFIG_TEXT_BASE is linked to 0x30000000 for booting
*/
-#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
-#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+#define CFG_SYS_FLASH_BASE 0x580000000ULL
+#define CFG_SYS_FLASH_BASE_PHYS 0x80000000
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
+#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000
+#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
/* For LS2085A */
-#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
-#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
+#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
+#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
/*
* Carve out a DDR region which will not be used by u-boot/Linux
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Miscellaneous configurable options */
#include "ls2080a_common.h"
#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
+#define CFG_SYS_I2C_IFDR_DIV 0x7e
#endif
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR1_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\
+ CFG_SYS_FLASH_BASE + 0x40000000}
#endif
#define CFG_SYS_NAND_CSPR_EXT (0x0)
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_CSPR3_EXT (0x0)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_CSPR3_EXT (0x0)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_SPL)
#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
#endif
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
* I2C
*/
#define RTC
#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+#define CFG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CFG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
+#define CFG_SYS_IFC_CCR 0x01000000
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\
+ CFG_SYS_FLASH_BASE + 0x40000000}
#endif
#define CFG_SYS_NAND_CSPR_EXT (0x0)
#define QIXIS_RCW_SRC_NAND 0x119
#define QIXIS_RST_FORCE_MEM 0x01
-#define CONFIG_SYS_CSPR3_EXT (0x0)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_CSPR3_EXT (0x0)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
#if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#ifdef CONFIG_TARGET_LS2081ARDB
#define QIXIS_QMAP_MASK 0x07
* I2C
*/
#ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
#endif
#define I2C_MUX_PCA_ADDR 0x75
#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
*/
#define RTC
#ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+#define CFG_SYS_I2C_RTC_ADDR 0x51
#else
#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
#endif
#define BOOT_TARGET_DEVICES(func) \
#include <asm/arch/config.h>
#include <asm/arch/soc.h>
-#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CFG_SYS_FLASH_BASE 0x20000000
/* DDR */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
#define CFG_SYS_SDRAM_SIZE 0x200000000UL
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
/* Serial Port */
#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
-#define CONFIG_SYS_SERIAL0 0x21c0000
-#define CONFIG_SYS_SERIAL1 0x21d0000
-#define CONFIG_SYS_SERIAL2 0x21e0000
-#define CONFIG_SYS_SERIAL3 0x21f0000
+#define CFG_SYS_SERIAL0 0x21c0000
+#define CFG_SYS_SERIAL1 0x21d0000
+#define CFG_SYS_SERIAL2 0x21e0000
+#define CFG_SYS_SERIAL3 0x21f0000
/*below might needs to be removed*/
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1, \
- (void *)CONFIG_SYS_SERIAL2, \
- (void *)CONFIG_SYS_SERIAL3 }
+#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
+ (void *)CFG_SYS_SERIAL1, \
+ (void *)CFG_SYS_SERIAL2, \
+ (void *)CFG_SYS_SERIAL3 }
/* MC firmware */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
/*
* Carve out a DDR region which will not be used by u-boot/Linux
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
#endif
/* I2C bus multiplexer */
/* RTC */
#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* Qixis */
-#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define CFG_SYS_I2C_FPGA_ADDR 0x66
/* USB */
#include "lx2160a_common.h"
/* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CFG_SYS_RTC_BUS_NUM 0
/* MAC/PHY configuration */
#include "lx2160a_common.h"
/* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM 4
+#define CFG_SYS_RTC_BUS_NUM 4
/* EMC2305 */
#define I2C_MUX_CH_EMC2305 0x09
/* USB */
/* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CFG_SYS_RTC_BUS_NUM 0
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/*
* U-Boot general configurations
#define CONFIG_FEC_MXC_PHYADDR 0x0
#endif
-#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
+#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */
/*
* RTC
*/
#ifdef CONFIG_CMD_DATE
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
#endif
/*
#endif
/* LVDS display */
-#define CONFIG_SYS_LDB_CLOCK 33260000
+#define CFG_SYS_LDB_CLOCK 33260000
#define CONFIG_IMX_VIDEO_SKIP
/* IIM Fuses */
#endif
#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/*
* Serial driver
* Flash configuration
*/
#ifdef CONFIG_64BIT
-# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000
+# define CFG_SYS_FLASH_BASE 0xffffffffbe000000
#else
-# define CONFIG_SYS_FLASH_BASE 0xbe000000
+# define CFG_SYS_FLASH_BASE 0xbe000000
#endif
/*
#include "mx6_common.h"
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
+#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + 0x80000)
/*
* Below defines are set but NOT really used since we by
#define CFG_SYS_FSL_ESDHC_ADDR 0
/* NOR 16-bit mode */
-#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
+#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
#define CONFIG_FLASH_VERIFY
/* NOR Flash MTD */
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
+#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) }
+#define CFG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
/* Ethernet Configuration */
#define CONFIG_FEC_MXC_PHYADDR 1
"nor_img_addr=0x11000000\0" \
"nor_img_file=core-image-lwn-mccmon6.nor\0" \
"emmc_img_file=core-image-lwn-mccmon6.ext4\0" \
- "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
+ "nor_bank_start=" __stringify(CFG_SYS_FLASH_BASE) "\0" \
"nor_img_size=0x02000000\0" \
"factory_script_file=factory.scr\0" \
"factory_load_script=" \
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment configs */
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
+#define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
/* Misc CPU related */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
/* NAND flash */
#ifdef CONFIG_CMD_NAND
/* uart */
/* The following table includes the supported baudrates */
-# define CONFIG_SYS_BAUDRATE_TABLE \
+# define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#define CONFIG_HOSTNAME "microblaze-generic"
/* SPL part */
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
#endif /* __CONFIG_H */
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 1
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7620_H */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED 0x1c000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x800000
+#define CFG_SYS_INIT_SP_OFFSET 0x800000
/* MMC */
#define MMC_SUPPORTS_TUNING
#endif
/* Serial common */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7621_H */
#define __MT7622_H
/* Uboot definition */
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* SPL -> Uboot */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
+#define CFG_SYS_INIT_SP_OFFSET 0x80000
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#endif
/* Serial common */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
#endif /* __CONFIG_MT7628_H */
/* Defines for SPL */
#define CONFIG_SPI_ADDR 0x30000000
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
+#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
/* SPL -> Uboot */
#define __MT7981_H
/* Uboot definition */
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* SPL -> Uboot */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
#define CFG_SYS_SDRAM_BASE 0x40000000
#define __MT7986_H
/* Uboot definition */
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/* SPL -> Uboot */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
#define CFG_SYS_SDRAM_BASE 0x40000000
#define __MT8512_H
/* Uboot definition */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
#define ENV_BOOT_READ_IMAGE \
"boot_rd_img=mmc dev 0" \
/*
* NS16550 Configuration
*/
-#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#if !defined(CONFIG_DM_SERIAL)
#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
-#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE)
-#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
+#if defined(CONFIG_ARMADA_38X) && !defined(CFG_SYS_BAUDRATE_TABLE)
+#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
921600, 1000000, 1152000, 1500000, \
/* additions for new ARM relocation support */
#define CFG_SYS_SDRAM_BASE 0x200000000
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
/* Default Env vars */
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_SYS_TCLK 325000000
+#define CFG_SYS_TCLK 325000000
#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
/* additions for new ARM relocation support */
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
+#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
921600, 1000000, 1152000, 1500000, \
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+#define CFG_SYS_TCLK 250000000 /* 250MHz */
/* additions for new ARM relocation support */
#define CFG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
/*
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-#define CONFIG_SYS_DDR_CLKSEL 0
-#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
-#define CONFIG_SYS_MAIN_PWR_ON
+#define CFG_SYS_DDR_CLKSEL 0
+#define CFG_SYS_CLKTL_CBCDR 0x59E35100
+#define CFG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
* environment organization
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* environment organization */
/* PMIC Controller */
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
-#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
+#define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* Command definition */
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* Framebuffer and LCD */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
/* FLASH and environment organization */
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#else
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
+#define CFG_SYS_PL310_BASE L2_PL310_BASE
#endif
#endif
/* Physical Memory Map */
#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+#define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
#include "mx6sabre_common.h"
#endif
#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
+#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
#endif
#define CFG_SYS_FSL_USDHC_NUM 2
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define PHYS_SDRAM_SIZE SZ_2G
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
/* UART */
#define LPUART_BASE LPUART4_RBASE
"bootz ${loadaddr} - ${fdt_addr}; " \
"fi;\0" \
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE SZ_256K
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif /* __CONFIG_H */
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
/* UART */
#define LPUART_BASE LPUART4_RBASE
"bootz; " \
"fi;\0" \
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE SZ_256K
#endif /* __CONFIG_H */
/* Memory sizes */
/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
+#define CFG_SYS_INIT_RAM_ADDR 0x00000000
#if defined(CONFIG_MX23)
-#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE (32 * 1024)
#elif defined(CONFIG_MX28)
-#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE (128 * 1024)
#endif
/* Point initial SP in SRAM so SPL can use it too. */
#define PHYS_SDRAM_SIZE SZ_256M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
*/
#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
/* USB device configuration */
#define CONFIG_USB_DEVICE
* Board ONENAND Info.
*/
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+#define CFG_SYS_ONENAND_BASE ONENAND_MAP
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2)
/*
* Physical Memory Map
*/
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CFG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CFG_SYS_INIT_RAM_SIZE 0x800
/*
* Attached kernel image
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* I2C */
#define CONFIG_I2C_MULTI_BUS
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_256M
/*
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#if IS_ENABLED(CONFIG_CMD_USB)
# define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define __OCTEON_COMMON_H__
#if defined(CONFIG_RAM_OCTEON)
-#define CONFIG_SYS_INIT_SP_OFFSET 0x20180000
+#define CFG_SYS_INIT_SP_OFFSET 0x20180000
#else
/* No DDR init -> run in L2 cache with limited resources */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
+#define CFG_SYS_INIT_SP_OFFSET 0x00180000
#endif
#define CFG_SYS_SDRAM_BASE 0xffffffff80000000
#include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0x10502000
+#define CFG_SYS_PL310_BASE 0x10502000
#endif
#define CFG_SYS_SDRAM_BASE 0x40000000
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#define CFG_SYS_FLASH_BASE NAND_BASE
#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CFG_SYS_NAND_ECCSIZE 512
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#define CFG_SYS_FLASH_BASE NAND_BASE
#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CFG_SYS_NAND_ECCSIZE 512
BOOTENV
/* OneNAND config */
-#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
+#define CFG_SYS_ONENAND_BASE ONENAND_MAP
+#define CFG_SYS_ONENAND_BLOCK_SIZE (128*1024)
/* NAND config */
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define CFG_SYS_FLASH_BASE 0x10000000
#endif
-#define CONFIG_SYS_FLASH_SIZE 0x4000000
+#define CFG_SYS_FLASH_SIZE 0x4000000
#endif /* __CONFIG_H */
/* Required support for the TCA642X GPIO we have on the uEVM */
#define CONFIG_TCA642X
-#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
-#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
+#define CFG_SYS_I2C_TCA642X_BUS_NUM 4
+#define CFG_SYS_I2C_TCA642X_ADDR 0x22
/* Enabled commands */
/*
* SoC Configuration
*/
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_OSCIN_FREQ 24000000
+#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/*
* Memory Info
/* memtest will be run on 16MB */
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
+#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
DAVINCI_SYSCFG_SUSPSRC_UART2 | \
*/
/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
-#define CONFIG_SYS_DA850_PLL0_PLLM 18
-#define CONFIG_SYS_DA850_PLL1_PLLM 21
+#define CFG_SYS_DA850_PLL0_PLLM 18
+#define CFG_SYS_DA850_PLL1_PLLM 21
/*
* DDR2 memory configuration
*/
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
DV_DDR_PHY_EXT_STRBEN | \
(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
+#define CFG_SYS_DA850_DDR2_SDBCR ( \
(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+#define CFG_SYS_DA850_DDR2_SDBCR2 0
-#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
+#define CFG_SYS_DA850_DDR2_SDTIMR ( \
(19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
(1 << DV_DDR_SDTMR1_RP_SHIFT) | \
(1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
(1 << DV_DDR_SDTMR1_WTR_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
+#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \
(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
(1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
(2 << DV_DDR_SDTMR2_CKE_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
-#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
+#define CFG_SYS_DA850_DDR2_SDRCR 0x00000492
+#define CFG_SYS_DA850_DDR2_PBBPR 0x30
/*
* Serial Driver info
*/
#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/*
* I2C Configuration
*/
-#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
/*
* Flash & Environment
/* Physical Memory Map */
#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* USB */
#ifdef CONFIG_USB_EHCI_MX6
#include <linux/stringify.h>
-#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR)
-#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required"
+#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CFG_SYS_I2C_PCA9557_ADDR)
+#error "CONFIG_SYS_SPD_BUS_NUM and CFG_SYS_I2C_PCA9557_ADDR are required"
#endif
-#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1
+#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CFG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CFG_SYS_I2C_PCA9557_ADDR 3 msk 1
#define __VAR_CMD(var, cmd) __stringify(var=cmd\0)
#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset)
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE
#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
+#define CFG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
#else
-#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CFG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#endif
#elif defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10)
*/
#define CONFIG_L2_CACHE
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xffe00000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
#define SPD_EEPROM_ADDRESS 0x52
#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
#endif
#define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* Default settings for DDR3 */
#ifndef CONFIG_TARGET_P2020RDB
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_MODE_1 0x40461520
-#define CONFIG_SYS_DDR_MODE_2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
+#define CFG_SYS_DDR_CS0_BNDS 0x0000003f
+#define CFG_SYS_DDR_CS0_CONFIG 0x80014302
+#define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CFG_SYS_DDR_CS1_BNDS 0x0040007f
+#define CFG_SYS_DDR_CS1_CONFIG 0x80014302
+#define CFG_SYS_DDR_CS1_CONFIG_2 0x00000000
+
+#define CFG_SYS_DDR_INIT_ADDR 0x00000000
+#define CFG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CFG_SYS_DDR_MODE_CONTROL 0x00000000
+
+#define CFG_SYS_DDR_ZQ_CONTROL 0x89080600
+#define CFG_SYS_DDR_WRLVL_CONTROL 0x8655A608
+#define CFG_SYS_DDR_SR_CNTR 0x00000000
+#define CFG_SYS_DDR_RCW_1 0x00000000
+#define CFG_SYS_DDR_RCW_2 0x00000000
+#define CFG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
+#define CFG_SYS_DDR_CONTROL_2 0x04401050
+#define CFG_SYS_DDR_TIMING_4 0x00220001
+#define CFG_SYS_DDR_TIMING_5 0x03402400
+
+#define CFG_SYS_DDR_TIMING_3 0x00020000
+#define CFG_SYS_DDR_TIMING_0 0x00330004
+#define CFG_SYS_DDR_TIMING_1 0x6f6B4846
+#define CFG_SYS_DDR_TIMING_2 0x0FA8C8CF
+#define CFG_SYS_DDR_CLK_CTRL 0x03000000
+#define CFG_SYS_DDR_MODE_1 0x40461520
+#define CFG_SYS_DDR_MODE_2 0x8000c000
+#define CFG_SYS_DDR_INTERVAL 0x0C300000
#endif
/*
* Local Bus Definitions
*/
#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_FLASH_BASE 0xec000000
+#define CFG_SYS_FLASH_BASE 0xec000000
#else
-#define CONFIG_SYS_FLASH_BASE 0xef000000
+#define CFG_SYS_FLASH_BASE 0xef000000
#endif
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \
| BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* Nand Flash */
#endif
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
/* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_CPLD_BASE 0xffa00000
+#define CFG_SYS_CPLD_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
+#define CFG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
#else
-#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
#endif
/* CPLD config size: 1Mb */
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000\0"
-#define CONFIG_SYS_VSC7385_BASE 0xffb00000
+#define CFG_SYS_VSC7385_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
+#define CFG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
#else
-#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
+#define CFG_SYS_VSC7385_BASE_PHYS CFG_SYS_VSC7385_BASE
#endif
/* The size of the VSC7385 firmware image */
*/
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#endif /* CONFIG_TPL_BUILD */
#endif
#endif
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/* I2C */
#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
+#define CFG_SYS_I2C_NOPROBES { {0, 0x29} }
#endif
/*
*/
#define CONFIG_RTC_PT7C4338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
+#define CFG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_PCA9557_ADDR 0x18
/* enable read and write access to EEPROM */
*/
#if defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10))
#endif
#endif
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
/*
* Environment Configuration
#define PHYS_SDRAM_SIZE SZ_256M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
#define PHYS_SDRAM_SIZE SZ_256M
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define ENV_MMC \
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* CLIPS FPGA Definitions */
-#define CONFIG_SYS_CSPR3_EXT (0x00)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
+#define CFG_SYS_CSPR3_EXT (0x00)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_40)
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
FTIM0_GPCM_TEADC(0x7) | \
FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x12))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
-#define CONFIG_SYS_CS3_FTIM3 0x04000000
+#define CFG_SYS_CS3_FTIM3 0x04000000
/* PRST */
#define WCOM_CLIPS_RST 0
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* PAXK FPGA Definitions */
-#define CONFIG_SYS_CSPR3_EXT (0x00)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
+#define CFG_SYS_CSPR3_EXT (0x00)
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_40)
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
FTIM0_GPCM_TEADC(0x7) | \
FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x12))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
-#define CONFIG_SYS_CS3_FTIM3 0x04000000
+#define CFG_SYS_CS3_FTIM3 0x04000000
/* PRST */
#define KM_LIU_RST 0
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
#define CFG_SYS_SDRAM_BASE 0x40000000
* Memory Layout
*/
/* Initial RAM for temporary stack, global data */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_INIT_RAM_ADDR \
- (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE)
+#define CFG_SYS_INIT_RAM_SIZE 0x10000
+#define CFG_SYS_INIT_RAM_ADDR \
+ (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE)
/* SDRAM Configuration (for final code, data, stack, heap) */
#define CFG_SYS_SDRAM_BASE 0x88000000
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#ifdef CONFIG_VIDEO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* PMIC */
#define CONFIG_POWER_PFUZE3000
/* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162
#define MAIN_PLL_DIV 2
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000
/* clocks */
/* CKGR_MOR - enable main osc. */
-#define CONFIG_SYS_MOR_VAL \
+#define CFG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
+#define CFG_SYS_PLLAR_VAL \
(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
AT91_PMC_PLLXR_OUT(3) | \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
+#define CFG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
+#define CFG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
+#define CFG_SYS_PIOC_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
+#define CFG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
+#define CFG_SYS_MATRIX_EBICSA_VAL \
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
+#define CFG_SYS_SDRC_TR_VAL1 0x13C
/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
+#define CFG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
(1 << 28)) /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
+#define CFG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
+#define CFG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+#define CFG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
+#define CFG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_MODE_DBW_16 | \
AT91_SMC_MODE_TDF | \
AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
+#define CFG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_CR_PROCRST | \
AT91_RSTC_MR_ERSTL(1) | \
AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
+#define CFG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_MR_WDV(0xfff) | \
AT91_WDT_MR_WDDIS | \
/* NOR flash */
#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000
#define CONFIG_EXTRA_ENV_SETTINGS \
"partition=nand0,0\0" \
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65
#define MAIN_PLL_DIV 2 /* 2 or 4 */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
/* clocks */
-#define CONFIG_SYS_MOR_VAL \
+#define CFG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
+#define CFG_SYS_PLLAR_VAL \
(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
AT91_PMC_PLLXR_OUT(3) | \
AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
+#define CFG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
+#define CFG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
#else
/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
+#define CFG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_4)
/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
+#define CFG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_4)
#endif
/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
+#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
+#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
+#define CFG_SYS_MATRIX_EBI0CSA_VAL \
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1 0
+#define CFG_SYS_SDRC_MR_VAL1 0
/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
+#define CFG_SYS_SDRC_TR_VAL1 0x3AA
/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
+#define CFG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
(8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
+#define CFG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
+#define CFG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+#define CFG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
+#define CFG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_MODE_DBW_16 | \
AT91_SMC_MODE_TDF | \
AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
+#define CFG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_CR_PROCRST | \
AT91_RSTC_MR_ERSTL(1) | \
AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
+#define CFG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_MR_WDV(0xfff) | \
AT91_WDT_MR_WDDIS | \
/* NOR flash, if populated */
#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* NAND flash */
#ifdef CONFIG_CMD_NAND
AT91_MATRIX_SCFG_SLOT_CYCLE(255))
/* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#define CONFIG_EXTRA_ENV_SETTINGS \
"partition=nand0,0\0" \
#define __CONFIG_H
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x70000000
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
-#define CONFIG_SYS_MASTER_CLOCK 132096000
-#define CONFIG_SYS_AT91_PLLA 0x20c73f03
-#define CONFIG_SYS_MCKR 0x1301
-#define CONFIG_SYS_MCKR_CSS 0x1302
+#define CFG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_AT91_PLLA 0x20c73f03
+#define CFG_SYS_MCKR 0x1301
+#define CFG_SYS_MCKR_CSS 0x1302
#endif
#define __CONFIG_POLEG_H
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/
+#define CFG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/
#endif
-#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20)
+#define CFG_SYS_BOOTMAPSZ (0x30 << 20)
#define CFG_SYS_SDRAM_BASE 0x0
/* Default environemnt variables */
#define __PRESIDIO_ASIC_H
/* Generic Timer Definitions */
-#define CONFIG_SYS_TIMER_RATE 25000000
-#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
+#define CFG_SYS_TIMER_RATE 25000000
+#define CFG_SYS_TIMER_COUNTER 0xf4321008
/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
* does not yet support DT. Thus define it here.
#define GICD_BASE 0xf7011000
#define GICC_BASE 0xf7012000
-#define CONFIG_SYS_TIMER_BASE 0xf4321000
+#define CFG_SYS_TIMER_BASE 0xf4321000
/* Use external clock source */
#define PRESIDIO_APB_CLK 125000000
/* Cortina Serial Configuration */
#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK)
-#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1}
+#define CORTINA_SERIAL_PORTS {(void *)CFG_SYS_SERIAL0, \
+ (void *)CFG_SYS_SERIAL1}
-#define CONFIG_SYS_SERIAL0 PER_UART0_CFG
-#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
+#define CFG_SYS_SERIAL0 PER_UART0_CFG
+#define CFG_SYS_SERIAL1 PER_UART1_CFG
/* SDRAM Bank #1 */
#define DDR_BASE 0x00000000
/* nand driver parameters */
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
- #define CFG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
+ #define CFG_SYS_NAND_BASE CFG_SYS_FLASH_BASE
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
#include <linux/sizes.h>
#include <asm/arch/sysmap-qcs404.h>
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x5000000\0" \
/* Needed to fill the ccsrbar pointer */
/* Virtual address to CCSRBAR */
-#define CONFIG_SYS_CCSRBAR 0xe0000000
+#define CFG_SYS_CCSRBAR 0xe0000000
/* Physical address should be a function call */
#ifndef __ASSEMBLY__
extern unsigned long long get_phys_ccsrbar_addr_early(void);
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
+#define CFG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
+#define CFG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
#else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
#endif
/* Virtual address to a temporary map if we need it (max 128MB) */
-#define CONFIG_SYS_TMPVIRT 0xe8000000
+#define CFG_SYS_TMPVIRT 0xe8000000
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CONFIG_HWCONFIG
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000
+#define CFG_SYS_INIT_RAM_ADDR 0x00100000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000
/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* RTC */
#define CONFIG_RTC_PT7C4338
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
#define CFG_SYS_SDRAM_SIZE 0x04000000
/* Address of u-boot image in Flash */
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+#define CFG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/*
* NOR Flash ( Spantion S29GL256P )
*/
-#define CONFIG_SYS_FLASH_BASE (0xA0000000)
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BASE (0xA0000000)
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif /* __CONFIG_H */
#endif
/* console */
-#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
+#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 }
#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
#define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
/* Timer */
#define CONFIG_TMU_TIMER
-#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
+#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
+#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
#endif /* __RCAR_GEN2_COMMON_H */
#define GICC_BASE 0xF1020000
/* console */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 }
/* PHY needs a longer autoneg timeout */
#define PHY_ANEG_TIMEOUT 20000
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000
+#define CFG_SYS_HZ_CLOCK 24000000
#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
#include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000
+#define CFG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0x10080000
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000
+#define CFG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0x10080000
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SYS_HZ_CLOCK 24000000
+#define CFG_SYS_HZ_CLOCK 24000000
#define CONFIG_IRAM_BASE 0xff700000
/* Use SoC timer for AArch32, but architected timer for AArch64 */
#ifndef CONFIG_ARM64
-#define CONFIG_SYS_TIMER_RATE 1000000
-#define CONFIG_SYS_TIMER_COUNTER \
+#define CFG_SYS_TIMER_RATE 1000000
+#define CFG_SYS_TIMER_COUNTER \
(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
#endif
/* Memory layout */
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/*
* The board really has 256M. However, the VC (VideoCore co-processor) shares
* the RAM, and uses a configurable portion at the top. We tell U-Boot that a
#define CONFIG_IRAM_BASE 0x10080000
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
+#define CFG_SYS_TIMER_RATE (24 * 1000 * 1000)
/* TIMER1,initialized by ddr initialize code */
-#define CONFIG_SYS_TIMER_BASE 0x10350020
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CFG_SYS_TIMER_BASE 0x10350020
+#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMER_BASE + 8)
#define CFG_SYS_SDRAM_BASE 0x60000000
/* FLASH and environment organization */
#define CONFIG_MMC_DEFAULT_DEV 0
-#define CONFIG_SYS_ONENAND_BASE 0xB0000000
+#define CFG_SYS_ONENAND_BASE 0xB0000000
#endif /* __CONFIG_H */
"mmcrootpart=3\0" \
"opts=always_resume=1"
-#define CONFIG_SYS_ONENAND_BASE 0x0C000000
+#define CFG_SYS_ONENAND_BASE 0x0C000000
#ifndef __ASSEMBLY__
void universal_spi_scl(int bit);
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __SALVATOR_X_H */
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID 0 /* ignored in arm */
#define __CONFIG_H__
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID 0 /* ignored in arm */
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SPL */
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
#include "at91-sama5_common.h"
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
/* NOR flash */
#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define CFG_SYS_FLASH_BASE 0x10000000
#endif
/* SDRAM */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x60000000
#define CFG_SYS_SDRAM_SIZE 0x20000000
#define CFG_SYS_SDRAM_SIZE \
(SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#ifndef SANDBOX_NO_SDL
#include <linux/sizes.h>
#include <asm/arch/sysmap-sdm845.h>
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x4000000\0" \
#define CFG_SYS_SDRAM_BASE PHYS_DRAM_1
/* Platform/Board specific defs */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
/* NS16550 Configuration */
#define CFG_SYS_NS16550_CLK (48000000)
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
/* misc settings */
* leaving the correct space for initial global data structure above that
* address while providing maximum stack area below.
*/
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* Defines for SPL */
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
+#define CFG_SYS_MASTER_CLOCK (198656000/2)
#define AT91_PLL_LOCK_TIMEOUT 1000000
-#define CONFIG_SYS_AT91_PLLA 0x2060bf09
-#define CONFIG_SYS_MCKR 0x100
-#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
-#define CONFIG_SYS_AT91_PLLB 0x10483f0e
+#define CFG_SYS_AT91_PLLA 0x2060bf09
+#define CFG_SYS_MCKR 0x100
+#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR)
+#define CFG_SYS_AT91_PLLB 0x10483f0e
#endif /* __CONFIG_H */
* Boot configuration
*/
-#define CONFIG_SYS_ONENAND_BASE 0xE7100000
+#define CFG_SYS_ONENAND_BASE 0xE7100000
/*
* Ethernet Contoller driver
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif
#include <linux/sizes.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
/* CPU */
/* SDRAM */
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6
#define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* Mem test settings */
* Clocks
*/
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
+#define CFG_SYS_TIMERBASE OMAP34XX_GPT2
#define V_NS16550_CLK 48000000
#define V_OSCK 26000000
#define CFG_SYS_NS16550_CLK V_NS16550_CLK
#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
115200 }
/*
/*
* Serial / UART configurations
*/
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
/*
* L4 OSC1 Timer 0
#include <linux/stringify.h>
/* Eternal oscillator */
-#define CONFIG_SYS_TIMER_RATE 40000000
+#define CFG_SYS_TIMER_RATE 40000000
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */
* the last two bytes of the 128 bytes large NVRAM in the
* RTC which begin at address 0x20
*/
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Environment settings */
/*
* Serial / UART configurations
*/
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_EXTRA_ENV_SETTINGS \
"autoload=no\0" \
*/
#define PHYS_SDRAM_1 0x0
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000
/* SPL memory allocation configuration, this is for FAT implementation */
-#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
+#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE)
#endif
* at this address to not overwrite the bootcounter by checking, if the
* bootcounter address is located in the internal SRAM.
*/
-#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
- (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE)))
+#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \
+ (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE)))
#endif
/*
/*
* Cache
*/
-#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
+#define CFG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
* L4 OSC1 Timer 0
*/
#ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-#ifndef CONFIG_SYS_TIMER_RATE
-#define CONFIG_SYS_TIMER_RATE 25000000
+#define CFG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
+#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4)
+#ifndef CFG_SYS_TIMER_RATE
+#define CFG_SYS_TIMER_RATE 25000000
#endif
#endif
/*
* U-Boot run time memory configurations
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000
+#define CFG_SYS_INIT_RAM_SIZE 0x40000
/*
* U-Boot environment configurations
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
+#define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_CCSRBAR 0xE0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xE0000000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
/* I2C addresses of SPD EEPROMs */
/* Hardcoded values, to use instead of SPD */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
-#define CONFIG_SYS_DDR_MODE 0x00480432
-#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
-#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
-#define CONFIG_SYS_DDR_CONFIG 0xC3008000
-#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
+#define CFG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CFG_SYS_DDR_CS0_CONFIG 0x80010102
+#define CFG_SYS_DDR_TIMING_0 0x00260802
+#define CFG_SYS_DDR_TIMING_1 0x3935D322
+#define CFG_SYS_DDR_TIMING_2 0x14904CC8
+#define CFG_SYS_DDR_MODE 0x00480432
+#define CFG_SYS_DDR_INTERVAL 0x030C0100
+#define CFG_SYS_DDR_CONFIG_2 0x04400000
+#define CFG_SYS_DDR_CONFIG 0xC3008000
+#define CFG_SYS_DDR_CLK_CONTROL 0x03800000
#define CFG_SYS_SDRAM_SIZE 256 /* in Megs */
/*
* Flash on the LocalBus
*/
-#define CONFIG_SYS_FLASH0 0xFE000000
-#define CONFIG_SYS_FLASH1 0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
+#define CFG_SYS_FLASH0 0xFE000000
+#define CFG_SYS_FLASH1 0xFC000000
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH1, CFG_SYS_FLASH0 }
-#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
+#define CFG_SYS_LBC_FLASH_BASE CFG_SYS_FLASH1 /* Localbus flash start */
+#define CFG_SYS_FLASH_BASE CFG_SYS_LBC_FLASH_BASE /* start of FLASH */
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
+#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
+#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* FPGA and NAND */
-#define CONFIG_SYS_FPGA_BASE 0xc0000000
-#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
+#define CFG_SYS_FPGA_BASE 0xc0000000
+#define CFG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
-#define CFG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
+#define CFG_SYS_NAND_BASE (CFG_SYS_FPGA_BASE + 0x70)
/* LIME GDC */
-#define CONFIG_SYS_LIME_BASE 0xc8000000
+#define CFG_SYS_LIME_BASE 0xc8000000
/*
* General PCI
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
*/
/* FIXME: This should be loaded from device tree... */
-#define CONFIG_SYS_PL310_BASE 0xa0412000
+#define CFG_SYS_PL310_BASE 0xa0412000
/* Linux does not boot if FDT / initrd is loaded to end of RAM */
#define BOOT_ENV \
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x3E000000
-#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */
+#define CFG_SYS_HZ_CLOCK 750000000 /* 750 MHz */
/* Environment */
* For booting Linux, use the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+#define CFG_SYS_BOOTMAPSZ SZ_256M
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
#include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_16M
+#define CFG_SYS_BOOTMAPSZ SZ_16M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#include <linux/sizes.h>
/* For booting Linux, use the first 12MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M
+#define CFG_SYS_BOOTMAPSZ SZ_8M + SZ_4M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#include <linux/sizes.h>
/* For booting Linux, use the first 6MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M
+#define CFG_SYS_BOOTMAPSZ SZ_4M + SZ_2M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
/*
* Configuration of the external SDRAM memory
*/
-#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
"ramdisk_addr_r=0xC0438000\0" \
BOOTENV
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
+#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \
CONFIG_SPL_PAD_TO)
/* For splashcreen */
#include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_16M
+#define CFG_SYS_BOOTMAPSZ SZ_16M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_HZ_CLOCK 1000000
+#define CFG_SYS_HZ_CLOCK 1000000
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ SZ_16M
+#define CFG_SYS_BOOTMAPSZ SZ_16M
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_HZ_CLOCK 1000000
+#define CFG_SYS_HZ_CLOCK 1000000
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#include <linux/sizes.h>
/* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M)
+#define CFG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M)
-#define CONFIG_SYS_FLASH_BASE 0x90000000
+#define CFG_SYS_FLASH_BASE 0x90000000
-#define CONFIG_SYS_HZ_CLOCK 1000000
+#define CFG_SYS_HZ_CLOCK 1000000
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
* For booting Linux, use the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+#define CFG_SYS_BOOTMAPSZ SZ_256M
/* NAND support */
#include <configs/stm32mp13_common.h>
/* uart with on-board st-link */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600, \
1000000, 2000000, 4000000}
* For booting Linux, use the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+#define CFG_SYS_BOOTMAPSZ SZ_256M
/* NAND support */
#include <configs/stm32mp15_common.h>
/* uart with on-board st-link */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600, \
1000000, 2000000 }
#define CONFIG_HOSTNAME "stmark2"
-#define CONFIG_SYS_UART_PORT 0
+#define CFG_SYS_UART_PORT 0
#define LDS_BOARD_TEXT \
board/sysam/stmark2/sbf_dram_init.o (.text*)
"sf write ${loadaddr} 0x00800000 ${filesize}\0" \
""
-#define CONFIG_SYS_SBFHDR_SIZE 0x7
+#define CFG_SYS_SBFHDR_SIZE 0x7
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_PRAM 2048 /* 2048 KB */
-#define CONFIG_SYS_MBAR 0xFC000000
+#define CFG_SYS_MBAR 0xFC000000
/*
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
/* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
+#define CFG_SYS_INIT_RAM_SIZE 0x10000
+#define CFG_SYS_INIT_RAM_CTRL 0x221
+#define CFG_SYS_INIT_SP_OFFSET ((CFG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
+#define CFG_SYS_SBFHDR_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - 32)
/*
* Start addresses for the final memory configuration
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
-#define CONFIG_SYS_DRAM_TEST
+#define CFG_SYS_DRAM_TEST
#if defined(CONFIG_CF_SBF)
#define CONFIG_SERIAL_BOOT
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
+#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
(CFG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment
*/
/* Cache Configuration */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CFG_SYS_DCACHE_INV (CF_CACR_DCINVA)
+#define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
+#define CFG_SYS_CACHE_DCACR ((CFG_SYS_CACHE_ICACR | \
CF_CACR_DEC | CF_CACR_DDCM_P | \
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 12)
+#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 12)
#endif /* __STMARK2_CONFIG_H */
#ifndef __CONFIG_STV0991_H
#define __CONFIG_STV0991_H
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
/* ram memory-related information */
#define PHYS_SDRAM_1 0x00000000
/* user interface */
/* MISC */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_INIT_RAM_ADDR 0x00190000
/* U-Boot Load Address */
/* Misc configuration */
* is known yet.
* H6 has SRAM A1 at 0x00020000.
*/
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
+#define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
/* FIXME: this may be larger on some SoCs */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
+#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
#define __CONFIG_H
/* Timers for fasp(TIMCLK) */
-#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
+#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
/*
* SDRAM (for initialize)
*/
/* RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+#define CFG_SYS_I2C_RTC_ADDR 0x51
/* Serial (pl011) */
#define UART_CLK (62500000)
#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
/* Support MTD */
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CFG_SYS_FLASH_BASE (0x08000000)
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE}
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/* Misc CPU related */
* leaving the correct space for initial global data structure above
* that address while providing maximum stack area below.
*/
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NAND flash */
#ifdef CONFIG_CMD_NAND
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_MASTER_CLOCK 132096000
#define AT91_PLL_LOCK_TIMEOUT 1000000
-#define CONFIG_SYS_AT91_PLLA 0x202A3F01
-#define CONFIG_SYS_MCKR 0x1300
-#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
-#define CONFIG_SYS_AT91_PLLB 0x10193F05
+#define CFG_SYS_AT91_PLLA 0x202A3F01
+#define CFG_SYS_MCKR 0x1300
+#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR)
+#define CFG_SYS_AT91_PLLB 0x10193F05
#endif
* Memory configuration
*/
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_128M
/*
/* Physical Memory Map */
#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_BOOTMAPSZ 0x10000000
+#define CFG_SYS_BOOTMAPSZ 0x10000000
/* Framebuffer */
#define CONFIG_IMX_HDMI
/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
#ifndef CONFIG_ARM64
-#define CONFIG_SYS_TIMER_RATE 1000000
-#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
+#define CFG_SYS_TIMER_RATE 1000000
+#define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
#endif
/* Environment */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#ifndef CONFIG_ARM64
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
+#define CFG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
+#define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
/* Defines for SPL */
#endif
#include "ls1088a_common.h"
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd"
#define SD_BOOTCOMMAND "run distro_bootcmd"
#define MEM_BASE 0x00500000
-#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
+#define CFG_SYS_LOWMEM_BASE MEM_BASE
/* Link Definitions */
/* Generic Interrupt Controller Definitions */
#define GICD_BASE (0x801000000000)
#define GICR_BASE (0x801000002000)
-#define CONFIG_SYS_SERIAL0 0x87e024000000
-#define CONFIG_SYS_SERIAL1 0x87e025000000
+#define CFG_SYS_SERIAL0 0x87e024000000
+#define CFG_SYS_SERIAL1 0x87e025000000
/* Miscellaneous configurable options */
/**
* Platform/Board specific defs
*/
-#define CONFIG_SYS_TIMERBASE 0x4802E000
+#define CFG_SYS_TIMERBASE 0x4802E000
/* NS16550 Configuration */
#define CFG_SYS_NS16550_CLK (48000000)
/**
* Platform/Board specific defs
*/
-#define CONFIG_SYS_TIMERBASE 0x4802E000
+#define CFG_SYS_TIMERBASE 0x4802E000
/*
* NS16550 Configuration
#define __CONFIG_TI_AM335X_COMMON_H__
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
-#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
/* SoC Configuration */
/* Memory Configuration */
-#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
+#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000
#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
#ifdef CONFIG_SYS_MALLOC_F_LEN
#endif
/* SPI Configuration */
-#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
+#define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
/* Keystone net */
#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
+#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
#else
-#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk)
+#define CFG_SYS_HZ_CLOCK get_external_clk(sys_clk)
#endif
#endif /* __CONFIG_KS2_EVM_H */
/* NS16550 Configuration */
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CFG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/* Select serial console configuration */
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2)
/* SPL */
#define __CONFIG_TI_OMAP4_COMMON_H
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0x48242000
+#define CFG_SYS_PL310_BASE 0x48242000
#endif
/* Get CPU defs */
#include <asm/arch/omap.h>
/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
+#define CFG_SYS_TIMERBASE GPT2_BASE
#include <configs/ti_armv7_omap.h>
#define __CONFIG_TI_OMAP5_COMMON_H
/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
+#define CFG_SYS_TIMERBASE GPT2_BASE
#include <linux/stringify.h>
* Else boot FIT image.
*/
-#define CONFIG_SYS_FLASH_BASE 0x0C000000
+#define CFG_SYS_FLASH_BASE 0x0C000000
#endif /* __TOTAL_COMPUTE_H */
#define CFG_SYS_SDRAM_BASE 0xa0000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE 0x8000
/*
* Serial Port
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/*
* All the defines above are for the TQMa6 SoM
/* Config on-board RTC */
#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_RTC_BUS_NUM 2
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_RTC_BUS_NUM 2
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Turn off RTC square-wave output to save battery */
#define CONFIG_RTC_DS1337_NOOSC
#include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0x10502000
+#define CFG_SYS_PL310_BASE 0x10502000
#endif
/* TRATS has 4 banks of DRAM */
#include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE 0x10502000
+#define CFG_SYS_PL310_BASE 0x10502000
#endif
/* TRATS2 has 4 banks of DRAM */
#define _CONFIG_TURRIS_MOX_H
#define CFG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
+#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
921600, 1000000, 1152000, 1500000, \
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* PMIC */
#define CONFIG_POWER_PFUZE3000
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
#endif /* __ULCB_H */
#if !defined(CONFIG_ARM64)
/* Time clock 1MHz */
-#define CONFIG_SYS_TIMER_RATE 1000000
+#define CFG_SYS_TIMER_RATE 1000000
#endif
#define CFG_SYS_NAND_REGS_BASE 0x68100000
LINUXBOOT_ENV_SETTINGS \
BOOTENV
-#define CONFIG_SYS_BOOTMAPSZ 0x20000000
+#define CFG_SYS_BOOTMAPSZ 0x20000000
/* only for SPL */
/* subtract sizeof(struct legacy_img_hdr) */
-#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40)
+#define CFG_SYS_UBOOT_BASE (0x130000 - 0x40)
#endif /* __CONFIG_UNIPHIER_H__ */
#include <asm/hardware.h>
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
/*
* Hardware drivers
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define PHYS_SDRAM_SIZE (gd->ram_size)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */
/* Onboard devices */
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \
"${blkcnt}; fi\0"
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_2M
#if defined(CONFIG_ENV_IS_IN_MMC)
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
"${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \
"${blkcnt}; fi\0"
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
+#define CFG_SYS_INIT_RAM_SIZE SZ_512K
/* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
#define CFG_SYS_SDRAM_BASE 0x40000000
BOOTENV
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CFG_SYS_FLASH_BASE 0x08000000
#else
-#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
+#define CFG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
#endif
#endif /* __VEXPRESS_AEMV8_H */
#define SCTL_BASE V2M_SYSCTL
#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
-#define CONFIG_SYS_TIMER_RATE 1000000
-#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
+#define CFG_SYS_TIMER_RATE 1000000
+#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
/* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 24000000
-#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
+ (void *)CFG_SYS_SERIAL1}
-#define CONFIG_SYS_SERIAL0 V2M_UART0
-#define CONFIG_SYS_SERIAL1 V2M_UART1
+#define CFG_SYS_SERIAL0 V2M_UART0
+#define CFG_SYS_SERIAL1 V2M_UART1
/* Miscellaneous configurable options */
#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
/* additions for new relocation code */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Basic environment settings */
#define BOOT_TARGET_DEVICES(func) \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
/* FLASH and environment organization */
-#define CONFIG_SYS_FLASH_SIZE 0x04000000
+#define CFG_SYS_FLASH_SIZE 0x04000000
/* Timeout values in ticks */
*/
/* Store environment at top of flash */
-#define CONFIG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 }
+#define CFG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 }
#endif /* VEXPRESS_COMMON_H */
#define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif
#define CONFIG_USART_ID 30
/* Timer */
-#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
+#define CFG_SYS_TIMER_COUNTER 0xfc06863c
/* SDRAM */
#define CFG_SYS_SDRAM_BASE 0x20000000
#ifdef CONFIG_CMD_MMC
#define ATMEL_BASE_MMCI 0xfc000000
-#define CONFIG_SYS_MMC_CLK_OD 500000
+#define CFG_SYS_MMC_CLK_OD 500000
/* For generating MMC partitions */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* RAM */
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CFG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
-#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE 0
+#define CFG_SYS_UBOOT_BASE 0
/* Serial SPL */
#define CFG_SYS_NS16550_CLK 40000000
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment organization */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* environment organization */
*/
/* driver configuration */
-#define CONFIG_SYS_MAX_NAND_CHIPS 1
+#define CFG_SYS_MAX_NAND_CHIPS 1
#define CFG_SYS_NAND_BASE MLC_NAND_BASE
/*
/*
* NS16550 Configuration
*/
-#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#if !defined(CONFIG_DM_SERIAL)
#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
* CPU Features
*/
-#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+#define CFG_SYS_STACK_SIZE (32 * 1024)
/*-----------------------------------------------------------------------
* Environment configuration
/* SPL */
-#define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M
-#define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K
-#define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K
+#define CFG_SYS_SPI_KERNEL_OFFS SZ_1M
+#define CFG_SYS_SPI_ARGS_OFFS SZ_512K
+#define CFG_SYS_SPI_ARGS_SIZE SZ_32K
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define GICR_BASE 0xF9080000
/* Serial setup */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
/* GUID for capsule updatable firmware image */
#define GICR_BASE 0xF9060000
/* Serial setup */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
#if defined(CONFIG_CMD_DFU)
#define GICC_BASE 0xF9020000
/* Serial setup */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
/* GUIDs for capsule updatable firmware images */
#endif
#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
-# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000
-# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000
-# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000
+# define CFG_SYS_SPI_KERNEL_OFFS 0x80000
+# define CFG_SYS_SPI_ARGS_OFFS 0xa0000
+# define CFG_SYS_SPI_ARGS_SIZE 0xa0000
#endif
/* u-boot is like dtb */
/* Serial drivers */
/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Boot configuration */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
/* Extend size of kernel image for uncompression */
#define PHYS_SDRAM_SIZE (128 << 20)
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* Environment is in stored in the eMMC boot partition */
/*===================*/
#if XCHAL_HAVE_PTP_MMU
-#define CONFIG_SYS_MEMORY_BASE \
+#define CFG_SYS_MEMORY_BASE \
(XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
-#define CONFIG_SYS_IO_BASE 0xf0000000
+#define CFG_SYS_IO_BASE 0xf0000000
#else
-#define CONFIG_SYS_MEMORY_BASE 0x60000000
-#define CONFIG_SYS_IO_BASE 0x90000000
+#define CFG_SYS_MEMORY_BASE 0x60000000
+#define CFG_SYS_IO_BASE 0x90000000
#define CONFIG_MAX_MEM_MAPPED 0x10000000
#endif
*/
/* FPGA core clock frequency in Hz (also input to UART) */
-#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
+#define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
/*
* DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
* Bits 0..5 set the lower 6 bits of the default ethernet MAC.
* Bit 6 is reserved for future use by Tensilica.
- * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
+ * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to
* the base of flash * (when on/1) or to the base of RAM (when off/0).
*/
-#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
+#define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
#define FPGAREG_MAC_WIDTH 6
#define FPGAREG_MAC_MASK 0x3f
#define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
/* Force hard reset of board by writing a code to this register */
-#define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
-#define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
+#define CFG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
+#define CFG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
/*====================*/
/* Serial Driver Info */
/*======================*/
#define CONFIG_ETHBASE 00:50:C2:13:6f:00
-#define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000)
-#define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
+#define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000)
+#define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
/*=====================*/
/* Flash & Environment */
/*=====================*/
#ifdef CONFIG_XTFPGA_LX60
-# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
-# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
+# define CFG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
+# define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
#elif defined(CONFIG_XTFPGA_KC705)
-# define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
-# define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000)
+# define CFG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
+# define CFG_SYS_FLASH_BASE IOADDR(0x00000000)
#else
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
-# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
+# define CFG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
+# define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
#endif
/*
/* Cache options */
#ifndef CONFIG_SYS_L2CACHE_OFF
-# define CONFIG_SYS_PL310_BASE 0xf8f02000
+# define CFG_SYS_PL310_BASE 0xf8f02000
#endif
#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
-#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
+#define CFG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR
+#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4)
/* GUIDs for capsule updatable firmware images */
#define XILINX_BOOT_IMAGE_GUID \
/* Serial drivers */
/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/* Ethernet driver */
/* Miscellaneous configurable options */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE 0x2000
/* Extend size of kernel image for uncompression */
/* qspi mode is working fine */
#ifdef CONFIG_ZYNQ_QSPI
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
-#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \
- CONFIG_SYS_SPI_ARGS_SIZE)
+#define CFG_SYS_SPI_ARGS_OFFS 0x200000
+#define CFG_SYS_SPI_ARGS_SIZE 0x80000
+#define CFG_SYS_SPI_KERNEL_OFFS (CFG_SYS_SPI_ARGS_OFFS + \
+ CFG_SYS_SPI_ARGS_SIZE)
#endif
/* SP location before relocation, must use scratch RAM */
/* Undef unneeded configs */
#undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_SYS_INIT_RAM_ADDR
-#undef CONFIG_SYS_INIT_RAM_SIZE
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#undef CFG_SYS_INIT_RAM_ADDR
+#undef CFG_SYS_INIT_RAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFDE000
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
#endif /* __CONFIG_ZYNQ_CSE_H */
int get_dpl_apply_status(void);
int is_lazy_dpl_addr_valid(void);
void fdt_fixup_mc_ddr(u64 *base, u64 *size);
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void);
#endif
u64 mc_get_dram_addr(void);
#define IFC_RREGS_64KOFFSET (64*1024)
#define IFC_FCM_BASE_ADDR \
- ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
+ ((struct fsl_ifc_fcm *)CFG_SYS_IFC_ADDR)
#define get_ifc_cspr_ext(i) \
(ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))
*/
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
-#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
+#if !defined(CFG_SYS_I2C_MAX_HOPS)
/* no muxes used bus = i2c adapters */
#define CONFIG_SYS_I2C_DIRECT_BUS 1
-#define CONFIG_SYS_I2C_MAX_HOPS 0
+#define CFG_SYS_I2C_MAX_HOPS 0
#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
#else
/* we use i2c muxes */
#endif
/* define the I2C bus number for RTC and DTT if not already done */
-#if !defined(CONFIG_SYS_RTC_BUS_NUM)
-#define CONFIG_SYS_RTC_BUS_NUM 0
+#if !defined(CFG_SYS_RTC_BUS_NUM)
+#define CFG_SYS_RTC_BUS_NUM 0
#endif
struct i2c_adapter {
struct i2c_bus_hose {
int adapter;
- struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS];
+ struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS];
};
#define I2C_NULL_HOP {{-1, ""}, 0, 0}
extern struct i2c_bus_hose i2c_bus[];
* completely to new multibus support.
*/
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
-# if !defined(CONFIG_SYS_MAX_I2C_BUS)
-# define CONFIG_SYS_MAX_I2C_BUS 2
+# if !defined(CFG_SYS_MAX_I2C_BUS)
+# define CFG_SYS_MAX_I2C_BUS 2
# endif
# define I2C_MULTI_BUS 1
#else
-# define CONFIG_SYS_MAX_I2C_BUS 1
+# define CFG_SYS_MAX_I2C_BUS 1
# define I2C_MULTI_BUS 0
#endif
* Define default values for some CCSR macros to make header files cleaner*
*
* To completely disable CCSR relocation in a board header file, define
- * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
- * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CFG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CFG_SYS_CCSRBAR.
*/
-#ifdef CONFIG_SYS_CCSRBAR_PHYS
-#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
-CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#ifdef CFG_SYS_CCSRBAR_PHYS
+#error "Do not define CFG_SYS_CCSRBAR_PHYS directly. Use \
+CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead."
#endif
#if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE)
-#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#undef CFG_SYS_CCSRBAR_PHYS_HIGH
+#undef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf
#else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#endif
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
#endif
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
- CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CFG_SYS_CCSRBAR_PHYS_LOW)
#endif /* __MPC85xx_H__ */
* platform register addresses
*/
-#define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4)
-#define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000)
-#define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008)
+#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4)
+#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000)
+#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008)
/*
* l2cr values. Look in config_<BOARD>.h for the actual setup
u8 minor_version;
} __attribute__((packed));
-#ifndef CONFIG_SYS_FLASH_BANKS_LIST
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#ifndef CFG_SYS_FLASH_BANKS_LIST
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
/*
#define MVEBU_MMC_CLOCKRATE_MAX 50000000
#define MVEBU_MMC_BASE_DIV_MAX 0x7ff
-#define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK
+#define MVEBU_MMC_BASE_FAST_CLOCK CFG_SYS_TCLK
#define MVEBU_MMC_BASE_FAST_CLK_100 100000000
#define MVEBU_MMC_BASE_FAST_CLK_200 200000000
#define CONFIG_SYS_POST_RTC 0x00000001
#define CONFIG_SYS_POST_WATCHDOG 0x00000002
-#define CONFIG_SYS_POST_MEMORY 0x00000004
+#define CFG_SYS_POST_MEMORY 0x00000004
#define CONFIG_SYS_POST_CPU 0x00000008
#define CONFIG_SYS_POST_I2C 0x00000010
#define CONFIG_SYS_POST_CACHE 0x00000020
#define CONFIG_SYS_POST_CODEC 0x00200000
#define CONFIG_SYS_POST_COPROC 0x00400000
#define CONFIG_SYS_POST_FLASH 0x00800000
-#define CONFIG_SYS_POST_MEM_REGIONS 0x01000000
+#define CFG_SYS_POST_MEM_REGIONS 0x01000000
#endif /* CONFIG_POST */
* spl_set_header_raw_uboot() - Set up a standard SPL image structure
*
* This sets up the given spl_image which the standard values obtained from
- * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START,
+ * config options: CONFIG_SYS_MONITOR_LEN, CFG_SYS_UBOOT_START,
* CONFIG_TEXT_BASE.
*
* @spl_image: Image description to set up
#define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR
#else
#ifdef CONFIG_MIPS
-#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET)
+#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CFG_SYS_INIT_SP_OFFSET)
#else
#define SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+ (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#endif
#endif
#define TCA642X_DIR_IN 1
/* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_TCA642X_ADDR
-#define CONFIG_SYS_I2C_TCA642X_ADDR (~0)
+#ifndef CFG_SYS_I2C_TCA642X_ADDR
+#define CFG_SYS_I2C_TCA642X_ADDR (~0)
#endif
/* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM
-#define CONFIG_SYS_I2C_TCA642X_BUS_NUM (0)
+#ifndef CFG_SYS_I2C_TCA642X_BUS_NUM
+#define CFG_SYS_I2C_TCA642X_BUS_NUM (0)
#endif
struct tca642x_bank_info {
#define RCTRL_PROM 0x00000008
-#ifndef CONFIG_SYS_TBIPA_VALUE
-# define CONFIG_SYS_TBIPA_VALUE 0x1f
+#ifndef CFG_SYS_TBIPA_VALUE
+# define CFG_SYS_TBIPA_VALUE 0x1f
#endif
#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SYS_TIMER_RATE
+#ifdef CFG_SYS_TIMER_RATE
/* Returns tick rate in ticks per second */
ulong notrace get_tbclk(void)
{
- return CONFIG_SYS_TIMER_RATE;
+ return CFG_SYS_TIMER_RATE;
}
#endif
-#ifdef CONFIG_SYS_TIMER_COUNTER
+#ifdef CFG_SYS_TIMER_COUNTER
unsigned long notrace timer_read_counter(void)
{
#ifdef CONFIG_SYS_TIMER_COUNTS_DOWN
- return ~readl(CONFIG_SYS_TIMER_COUNTER);
+ return ~readl(CFG_SYS_TIMER_COUNTER);
#else
- return readl(CONFIG_SYS_TIMER_COUNTER);
+ return readl(CFG_SYS_TIMER_COUNTER);
#endif
}
{
ulong count = timer_read_counter();
-#ifdef CONFIG_SYS_TIMER_RATE
- const ulong timer_rate = CONFIG_SYS_TIMER_RATE;
+#ifdef CFG_SYS_TIMER_RATE
+ const ulong timer_rate = CFG_SYS_TIMER_RATE;
if (timer_rate == 1000000)
return count;
#include <post.h>
#include <watchdog.h>
-#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS)
+#if CONFIG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS)
DECLARE_GLOBAL_DATA_PTR;
return ret;
}
-#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */
+#endif /* CONFIG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */
CONFIG_SYS_POST_RTC
},
#endif
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+#if CONFIG_POST & CFG_SYS_POST_MEMORY
{
"Memory test",
"memory",
&memory_post_test,
NULL,
NULL,
- CONFIG_SYS_POST_MEMORY
+ CFG_SYS_POST_MEMORY
},
#endif
#if CONFIG_POST & CONFIG_SYS_POST_CPU
CONFIG_SYS_POST_FLASH
},
#endif
-#if CONFIG_POST & CONFIG_SYS_POST_MEM_REGIONS
+#if CONFIG_POST & CFG_SYS_POST_MEM_REGIONS
{
"Memory regions test",
"mem_regions",
&memory_regions_post_test,
NULL,
NULL,
- CONFIG_SYS_POST_MEM_REGIONS
+ CFG_SYS_POST_MEM_REGIONS
},
#endif
};
#if defined(CONFIG_ENV_IS_IN_FLASH)
# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# define CONFIG_ENV_ADDR (CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
# endif
# ifndef CONFIG_ENV_OFFSET
-# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE)
# endif
# if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND)
-# define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
+# define CONFIG_ENV_ADDR_REDUND (CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
# endif
# ifndef CONFIG_ENV_SIZE
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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