i.MX6: add enable_sata_clock()

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 0f05432941750427e7bb9448b3e7185981f07d55..52d5dc4d90b9614a3156dd822a28b4c15c05cdb2 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -292,6 +292,37 @@ u32 imx_get_fecclk(void)
        return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
 }
 
+int enable_sata_clock(void)
+{
+       u32 reg = 0;
+       s32 timeout = 100000;
+       struct mxc_ccm_reg *const imx_ccm
+               = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
+
+       /* Enable sata clock */
+       reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
+       reg |= MXC_CCM_CCGR5_CG2_MASK;
+       writel(reg, &imx_ccm->CCGR5);
+
+       /* Enable PLLs */
+       reg = readl(&imx_ccm->analog_pll_enet);
+       reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
+       writel(reg, &imx_ccm->analog_pll_enet);
+       reg |= BM_ANADIG_PLL_SYS_ENABLE;
+       while (timeout--) {
+               if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+                       break;
+       }
+       if (timeout <= 0)
+               return -EIO;
+       reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
+       writel(reg, &imx_ccm->analog_pll_enet);
+       reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
+       writel(reg, &imx_ccm->analog_pll_enet);
+
+       return 0 ;
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
        switch (clk) {

diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 613809bdd672495727e4b3474cc8cd904820cb1a..b91d8bf45027f798b8e4825d71857246f0ee38ff 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -47,5 +47,6 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 void enable_usboh3_clk(unsigned char enable);
+int enable_sata_clock(void);
 
 #endif /* __ASM_ARCH_CLOCK_H */

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 6d25c8d983fa146f5c56ffa0cb0d92fc4bbb4448..e165810ddc3d5c57aba4c157068054443ff5e724 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -436,5 +436,14 @@ struct anatop_regs {
        u32     digprog;                /* 0x260 */
 };
 
+struct iomuxc_base_regs {
+       u32     gpr[14];        /* 0x000 */
+       u32     obsrv[5];       /* 0x038 */
+       u32     swmux_ctl[197]; /* 0x04c */
+       u32     swpad_ctl[250]; /* 0x360 */
+       u32     swgrp[26];      /* 0x748 */
+       u32     daisy[104];     /* 0x7b0..94c */
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */

diff --git a/arch/arm/include/asm/arch-mx6/iomux-v3.h b/arch/arm/include/asm/arch-mx6/iomux-v3.h
index 4558f4fba251c26172634d5180dc6e8d1f44c46b..788b413219c2a4885674caf82a628f2df63abd80 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/iomux-v3.h
+++ b/arch/arm/include/asm/arch-mx6/iomux-v3.h
@@ -100,4 +100,115 @@ typedef u64 iomux_v3_cfg_t;
 int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
 
+/*
+ * IOMUXC_GPR13 bit fields
+ */
+#define IOMUXC_GPR13_SDMA_STOP_REQ     (1<<30)
+#define IOMUXC_GPR13_CAN2_STOP_REQ     (1<<29)
+#define IOMUXC_GPR13_CAN1_STOP_REQ     (1<<28)
+#define IOMUXC_GPR13_ENET_STOP_REQ     (1<<27)
+#define IOMUXC_GPR13_SATA_PHY_8_MASK   (7<<24)
+#define IOMUXC_GPR13_SATA_PHY_7_MASK   (0x1f<<19)
+#define IOMUXC_GPR13_SATA_PHY_6_SHIFT  16
+#define IOMUXC_GPR13_SATA_PHY_6_MASK   (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+#define IOMUXC_GPR13_SATA_SPEED_MASK   (1<<15)
+#define IOMUXC_GPR13_SATA_PHY_5_MASK   (1<<14)
+#define IOMUXC_GPR13_SATA_PHY_4_MASK   (7<<11)
+#define IOMUXC_GPR13_SATA_PHY_3_MASK   (0x1f<<7)
+#define IOMUXC_GPR13_SATA_PHY_2_MASK   (0x1f<<2)
+#define IOMUXC_GPR13_SATA_PHY_1_MASK   (3<<0)
+
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB     (0b000<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB     (0b001<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB     (0b010<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB     (0b011<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB     (0b100<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB     (0b101<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB     (0b110<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB     (0b111<<24)
+
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19)
+
+#define IOMUXC_GPR13_SATA_SPEED_1P5G   (0<<15)
+#define IOMUXC_GPR13_SATA_SPEED_3G     (1<<15)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED       (0<<14)
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED                (1<<14)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16       (0<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16       (1<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16       (2<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16       (3<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16                (4<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16                (5<<11)
+
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB        (0b0000<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB        (0b0001<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB        (0b0010<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB        (0b0011<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB        (0b0100<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB        (0b0101<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB        (0b0110<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB        (0b0111<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB        (0b1000<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB        (0b1001<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB        (0b1010<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB        (0b1011<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB        (0b1100<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB        (0b1101<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB        (0b1110<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB        (0b1111<<7)
+
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V      (0b00000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V      (0b00001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V      (0b00010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V      (0b00011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V      (0b00100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V      (0b00101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V      (0b00110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V      (0b00111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V      (0b01000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V      (0b01001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V      (0b01010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V      (0b01011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V      (0b01100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V      (0b01101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V      (0b01110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V      (0b01111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V      (0b10000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V      (0b10001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V      (0b10010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V      (0b10011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V      (0b10100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V      (0b10101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V      (0b10110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V      (0b10111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V      (0b11000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V      (0b11001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V      (0b11010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V      (0b11011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V      (0b11100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V      (0b11101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V      (0b11110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V      (0b11111<<2)
+
+#define IOMUXC_GPR13_SATA_PHY_1_FAST   0
+#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
+#define IOMUXC_GPR13_SATA_PHY_1_SLOW   2
+
+#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_7_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_6_MASK \
+                               |IOMUXC_GPR13_SATA_SPEED_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_5_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_4_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_3_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_2_MASK \
+                               |IOMUXC_GPR13_SATA_PHY_1_MASK)
+
 #endif /* __MACH_IOMUX_V3_H__*/