MIPS: add support for Broadcom MIPS BCM6328 SoC family

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
new file mode 100644 (file)
index 0000000..b287239
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "brcm,bcm6328";
+
+       cpus {
+               reg = <0x10000000 0x4>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               u-boot,dm-pre-reloc;
+
+               cpu@0 {
+                       compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
+                       device_type = "cpu";
+                       reg = <0>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               cpu@1 {
+                       compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
+                       device_type = "cpu";
+                       reg = <1>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               periph_osc: periph-osc {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <50000000>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+
+       ubus {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               u-boot,dm-pre-reloc;
+
+               pll_cntl: syscon@10000068 {
+                       compatible = "syscon";
+                       reg = <0x10000068 0x4>;
+               };
+
+               syscon-reboot {
+                       compatible = "syscon-reboot";
+                       regmap = <&pll_cntl>;
+                       offset = <0x0>;
+                       mask = <0x1>;
+               };
+
+               uart0: serial@10000100 {
+                       compatible = "brcm,bcm6345-uart";
+                       reg = <0x10000100 0x18>;
+                       clocks = <&periph_osc>;
+
+                       status = "disabled";
+               };
+
+               uart1: serial@10000120 {
+                       compatible = "brcm,bcm6345-uart";
+                       reg = <0x10000120 0x18>;
+                       clocks = <&periph_osc>;
+
+                       status = "disabled";
+               };
+
+               memory-controller@10003000 {
+                       compatible = "brcm,bcm6328-mc";
+                       reg = <0x10003000 0x1000>;
+                       u-boot,dm-pre-reloc;
+               };
+       };
+};

diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 0300ae35a8b0e9c546e18ddb62acaefc95f0846b..467ba5bd1c9ec85835257dc14bd77606e27c43d4 100644 (file)
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -2,11 +2,23 @@ menu "Broadcom MIPS platforms"
        depends on ARCH_BMIPS
 
 config SYS_SOC
+       default "bcm6328" if SOC_BMIPS_BCM6328
        default "bcm6358" if SOC_BMIPS_BCM6358
 
 choice
        prompt "Broadcom MIPS SoC select"
 
+config SOC_BMIPS_BCM6328
+       bool "BMIPS BCM6328 family"
+       select SUPPORTS_BIG_ENDIAN
+       select SUPPORTS_CPU_MIPS32_R1
+       select MIPS_TUNE_4KC
+       select MIPS_L1_CACHE_SHIFT_4
+       select SWAP_IO_SPACE
+       select SYSRESET_SYSCON
+       help
+         This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
+
 config SOC_BMIPS_BCM6358
        bool "BMIPS BCM6358 family"
        select SUPPORTS_BIG_ENDIAN

diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
new file mode 100644 (file)
index 0000000..41c7838
--- /dev/null
+++ b/include/configs/bmips_bcm6328.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6328_H
+#define __CONFIG_BMIPS_BCM6328_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ     160000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET      0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6328_H */