andes: cpu: Enable cache and TLB ECC support

Andes CPU supports cache and TLB ECC.
Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>

diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index a23b7948d92d5920347ce70c09d350ea7b6303d0..d25ecba0e88d47d8d4758564d2bafaf518d297d4 100644 (file)
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -35,7 +35,8 @@ void harts_early_init(void)
 
                mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
                                MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
-                               MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN);
+                               MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
+                               MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
 
                if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
                        mcache_ctl_val |= MCACHE_CTL_IC_EN;

diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 3f3f05b348a0b781c080e95b5797c1d575a1dddb..028fd01c2f385ae52cc199f33ca426d0ef16f6e5 100644 (file)
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -18,11 +18,14 @@
 
 #define MCACHE_CTL_IC_EN               BIT(0)
 #define MCACHE_CTL_DC_EN               BIT(1)
+#define MCACHE_CTL_IC_ECCEN            BIT(3)
+#define MCACHE_CTL_DC_ECCEN            BIT(5)
 #define MCACHE_CTL_CCTL_SUEN           BIT(8)
 #define MCACHE_CTL_IC_PREFETCH_EN      BIT(9)
 #define MCACHE_CTL_DC_PREFETCH_EN      BIT(10)
 #define MCACHE_CTL_DC_WAROUND_EN       BIT(13)
 #define MCACHE_CTL_L2C_WAROUND_EN      BIT(15)
+#define MCACHE_CTL_TLB_ECCEN           BIT(18)
 #define MCACHE_CTL_DC_COHEN            BIT(19)
 #define MCACHE_CTL_DC_COHSTA           BIT(20)