ARM: dts: renesas: Synchronize R-Car R8A779A0 E3 DTs with Linux 6.5.3

Synchronize R-Car R8A779A0 E3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
index e06b8eda85e18155ebcaccc314dad1dab59e56b1..dbc8dcab109d15db556bd079b66642b3af6dfa18 100644 (file)
--- a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
+++ b/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
@@ -5,6 +5,8 @@
  * Copyright (C) 2021 Glider bv
  */
 
+#include <dt-bindings/media/video-interfaces.h>
+
 &csi40 {
        status = "okay";
 
@@ -105,6 +107,7 @@
                        port@4 {
                                reg = <4>;
                                max96712_out0: endpoint {
+                                       bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
                                        clock-lanes = <0>;
                                        data-lanes = <1 2 3 4>;
                                        remote-endpoint = <&csi40_in>;
@@ -125,6 +128,7 @@
                        port@4 {
                                reg = <4>;
                                max96712_out1: endpoint {
+                                       bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
                                        clock-lanes = <0>;
                                        data-lanes = <1 2 3 4>;
                                        lane-polarities = <0 0 0 0 1>;
@@ -146,6 +150,7 @@
                        port@4 {
                                reg = <4>;
                                max96712_out2: endpoint {
+                                       bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
                                        clock-lanes = <0>;
                                        data-lanes = <1 2 3 4>;
                                        lane-polarities = <0 0 0 0 1>;

diff --git a/arch/arm/dts/r8a779a0-falcon.dts b/arch/arm/dts/r8a779a0-falcon.dts
index b2e67b82caf6ec3402071c1e3ce849c57d813533..63db822e5f4662b659786568cd2288c1c331e18f 100644 (file)
--- a/arch/arm/dts/r8a779a0-falcon.dts
+++ b/arch/arm/dts/r8a779a0-falcon.dts
@@ -37,8 +37,12 @@
        };
 };
 
+&can_clk {
+       clock-frequency = <40000000>;
+};
+
 &canfd {
-       pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
+       pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
        pinctrl-names = "default";
        status = "okay";
 
@@ -80,6 +84,11 @@
 
        };
 
+       can_clk_pins: can-clk {
+               groups = "can_clk";
+               function = "can_clk";
+       };
+
        canfd0_pins: canfd0 {
                groups = "canfd0_data";
                function = "canfd0";

diff --git a/arch/arm/dts/r8a779a0.dtsi b/arch/arm/dts/r8a779a0.dtsi
index ed9400f903c9ecefde6a268fcb0b4d739b87303b..4e67a03564971b89a5b2fb7564b2eb93aa549819 100644 (file)
--- a/arch/arm/dts/r8a779a0.dtsi
+++ b/arch/arm/dts/r8a779a0.dtsi
@@ -606,7 +606,8 @@
                };
 
                canfd: can@e6660000 {
-                       compatible = "renesas,r8a779a0-canfd";
+                       compatible = "renesas,r8a779a0-canfd",
+                                    "renesas,rcar-gen4-canfd";
                        reg = <0 0xe6660000 0 0x8000>;
                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -656,7 +657,7 @@
 
                avb0: ethernet@e6800000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6800000 0 0x800>;
                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
@@ -704,7 +705,7 @@
 
                avb1: ethernet@e6810000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6810000 0 0x800>;
                        interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
@@ -752,7 +753,7 @@
 
                avb2: ethernet@e6820000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6820000 0 0x1000>;
                        interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
@@ -800,7 +801,7 @@
 
                avb3: ethernet@e6830000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6830000 0 0x1000>;
                        interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
@@ -848,7 +849,7 @@
 
                avb4: ethernet@e6840000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6840000 0 0x1000>;
                        interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
@@ -896,7 +897,7 @@
 
                avb5: ethernet@e6850000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6850000 0 0x1000>;
                        interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
@@ -942,6 +943,56 @@
                        status = "disabled";
                };
 
+               pwm0: pwm@e6e30000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e30000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm1: pwm@e6e31000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e31000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm2: pwm@e6e32000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e32000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm3: pwm@e6e33000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e33000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
+               pwm4: pwm@e6e34000 {
+                       compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+                       reg = <0 0xe6e34000 0 0x10>;
+                       #pwm-cells = <2>;
+                       clocks = <&cpg CPG_MOD 628>;
+                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+                       resets = <&cpg 628>;
+                       status = "disabled";
+               };
+
                scif0: serial@e6e60000 {
                        compatible = "renesas,scif-r8a779a0",
                                     "renesas,rcar-gen4-scif", "renesas,scif";
@@ -1019,7 +1070,7 @@
 
                msiof0: spi@e6e90000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6e90000 0 0x0064>;
                        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 618>;
@@ -1034,7 +1085,7 @@
 
                msiof1: spi@e6ea0000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6ea0000 0 0x0064>;
                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 619>;
@@ -1049,7 +1100,7 @@
 
                msiof2: spi@e6c00000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c00000 0 0x0064>;
                        interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 620>;
@@ -1064,7 +1115,7 @@
 
                msiof3: spi@e6c10000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c10000 0 0x0064>;
                        interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 621>;
@@ -1079,7 +1130,7 @@
 
                msiof4: spi@e6c20000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c20000 0 0x0064>;
                        interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 622>;
@@ -1094,7 +1145,7 @@
 
                msiof5: spi@e6c28000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c28000 0 0x0064>;
                        interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 623>;
@@ -2097,7 +2148,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xee480000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 10>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2106,7 +2157,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xee4c0000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 19>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2115,7 +2166,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeed00000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 0>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2124,7 +2175,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeed40000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 1>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2133,7 +2184,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeed80000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 3>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_A3IR>;
                        #iommu-cells = <1>;
                };
@@ -2142,7 +2193,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeedc0000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 12>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2151,7 +2202,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeee80000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 14>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2160,7 +2211,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeeec0000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 15>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2169,7 +2220,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeee00000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 6>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2178,7 +2229,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeef00000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 5>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2187,7 +2238,7 @@
                        compatible = "renesas,ipmmu-r8a779a0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
                        reg = <0 0xeef40000 0 0x20000>;
-                       renesas,ipmmu-main = <&ipmmu_mm 11>;
+                       renesas,ipmmu-main = <&ipmmu_mm>;
                        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
                };
@@ -2209,8 +2260,7 @@
                        interrupt-controller;
                        reg = <0x0 0xf1000000 0 0x20000>,
                              <0x0 0xf1060000 0 0x110000>;
-                       interrupts = <GIC_PPI 9
-                                     (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
                };
 
                fcpvd0: fcp@fea10000 {
@@ -2857,9 +2907,9 @@
 
        timer {
                compatible = "arm,armv8-timer";
-               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
        };
 };