x86: apl: Generate CPU tables

Add ACPI generation to the APL CPU driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
index 0a6d2ad7a4ac65becadcd895262b851fe6813ed1..8da2e64e226a70a033d3ed1416fe36e27080d345 100644 (file)
--- a/arch/x86/cpu/apollolake/cpu.c
+++ b/arch/x86/cpu/apollolake/cpu.c
@@ -6,14 +6,90 @@
 #include <common.h>
 #include <cpu.h>
 #include <dm.h>
+#include <log.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_table.h>
 #include <asm/cpu_common.h>
 #include <asm/cpu_x86.h>
+#include <asm/intel_acpi.h>
+#include <asm/msr.h>
+#include <dm/acpi.h>
+
+#define CSTATE_RES(address_space, width, offset, address)              \
+       {                                                               \
+       .space_id = address_space,                                      \
+       .bit_width = width,                                             \
+       .bit_offset = offset,                                           \
+       .addrl = address,                                               \
+       }
+
+static struct acpi_cstate cstate_map[] = {
+       {
+               /* C1 */
+               .ctype = 1,             /* ACPI C1 */
+               .latency = 1,
+               .power = 1000,
+               .resource = {
+                       .space_id = ACPI_ADDRESS_SPACE_FIXED,
+               },
+       }, {
+               .ctype = 2,             /* ACPI C2 */
+               .latency = 50,
+               .power = 10,
+               .resource = {
+                       .space_id = ACPI_ADDRESS_SPACE_IO,
+                       .bit_width = 8,
+                       .addrl = 0x415,
+               },
+       }, {
+               .ctype = 3,             /* ACPI C3 */
+               .latency = 150,
+               .power = 10,
+               .resource = {
+                       .space_id = ACPI_ADDRESS_SPACE_IO,
+                       .bit_width = 8,
+                       .addrl = 0x419,
+               },
+       },
+};
 
 static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
 {
        return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
 }
 
+static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+       uint core_id = dev->req_seq;
+       int cores_per_package;
+       int ret;
+
+       cores_per_package = cpu_get_cores_per_package();
+       ret = acpi_generate_cpu_header(ctx, core_id, cstate_map,
+                                      ARRAY_SIZE(cstate_map));
+
+       /* Generate P-state tables */
+       generate_p_state_entries(ctx, core_id, cores_per_package);
+
+       /* Generate T-state tables */
+       generate_t_state_entries(ctx, core_id, cores_per_package, NULL, 0);
+
+       acpigen_pop_len(ctx);
+
+       if (device_is_last_sibling(dev)) {
+               ret = acpi_generate_cpu_package_final(ctx, cores_per_package);
+
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+struct acpi_ops apl_cpu_acpi_ops = {
+       .fill_ssdt      = acpi_cpu_fill_ssdt,
+};
+
 static const struct cpu_ops cpu_x86_apl_ops = {
        .get_desc       = cpu_x86_get_desc,
        .get_info       = apl_get_info,
@@ -32,5 +108,6 @@ U_BOOT_DRIVER(cpu_x86_apl_drv) = {
        .of_match       = cpu_x86_apl_ids,
        .bind           = cpu_x86_bind,
        .ops            = &cpu_x86_apl_ops,
+       ACPI_OPS_PTR(&apl_cpu_acpi_ops)
        .flags          = DM_FLAG_PRE_RELOC,
 };

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index f04d275dd9a1305fc690cb9c42d3089c153da6db..1bcbb49a61f2281ee5e95b1174f82f2e0593d65b 100644 (file)
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -38,7 +38,8 @@ obj-y += sfi.o
 obj-y  += acpi.o
 obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o
 ifndef CONFIG_QEMU
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o acpigen.o
+obj-y += acpigen.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 endif
 obj-y  += tables.o
 ifndef CONFIG_SPL_BUILD

diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index c9006e2f93438e2066e2d8d5d6f624cd7e5aacf7..ef4dabbe26e009a5066761e31ae907913f4ad965 100644 (file)
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -72,6 +72,7 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_INTEL_ACPIGEN=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y