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For Layerscape based platforms, ESBC image Address in Header is 64bit.
+config SYS_FSL_SFP_BE
+ def_bool y
+ depends on CHAIN_OF_TRUST && (PPC || FSL_LSCH2 || ARCH_LS1021A)
+
+config SYS_FSL_SFP_LE
+ def_bool y
+ depends on CHAIN_OF_TRUST && !SYS_FSL_SFP_BE
+
+choice
+ prompt "SFP IP revision"
+ depends on CHAIN_OF_TRUST
+ default SYS_FSL_SFP_VER_3_0 if PPC
+ default SYS_FSL_SFP_VER_3_4
+
+config SYS_FSL_SFP_VER_3_0
+ bool "SFP version 3.0"
+
+config SYS_FSL_SFP_VER_3_2
+ bool "SFP version 3.2"
+
+config SYS_FSL_SFP_VER_3_4
+ bool "SFP version 3.4"
+
+endchoice
+
+config SYS_FSL_SRK_LE
+ def_bool y
+ depends on CHAIN_OF_TRUST && ARM
+
+config KEY_REVOCATION
+ def_bool y
+ depends on CHAIN_OF_TRUST
+
config DEEP_SLEEP
bool "Enable SoC deep sleep feature"
depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
/* SMMU Defintions */
#define SMMU_BASE 0x05000000 /* GR0 Base */
-/* SFP */
-#define CONFIG_SYS_FSL_SFP_VER_3_4
-#define CONFIG_SYS_FSL_SFP_LE
-#define CONFIG_SYS_FSL_SRK_LE
-
/* DCFG - GUR */
#define CONFIG_SYS_FSL_CCSR_GUR_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-/* SFP */
-#define CONFIG_SYS_FSL_SFP_VER_3_4
-#define CONFIG_SYS_FSL_SFP_LE
-#define CONFIG_SYS_FSL_SRK_LE
-
/* DCFG - GUR */
#define CONFIG_SYS_FSL_CCSR_GUR_LE
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
/* SMMU Definitions */
#define SMMU_BASE 0x05000000 /* GR0 Base */
-/* SFP */
-#define CONFIG_SYS_FSL_SFP_VER_3_4
-#define CONFIG_SYS_FSL_SFP_LE
-#define CONFIG_SYS_FSL_SRK_LE
-
/* DCFG - GUR */
#define CONFIG_SYS_FSL_CCSR_GUR_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-/* SFP */
-#define CONFIG_SYS_FSL_SFP_VER_3_4
-#define CONFIG_SYS_FSL_SFP_LE
-#define CONFIG_SYS_FSL_SRK_LE
-
/* SEC */
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SRK_LE
-#define CONFIG_KEY_REVOCATION
/* SMMU Defintions */
#define SMMU_BASE 0x09000000
#elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
-#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SRK_LE
-#define CONFIG_KEY_REVOCATION
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SRK_LE
-#define CONFIG_KEY_REVOCATION
/* SMMU Defintions */
#define SMMU_BASE 0x09000000
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SRK_LE
#define DCU_LAYER_MAX_NUM 16
#define CONFIG_SPL_UBOOT_KEY_HASH NULL
#endif /* ifdef CONFIG_SPL_BUILD */
-#define CONFIG_KEY_REVOCATION
-
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
select SYS_FSL_ERRATUM_A006475
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007075
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_ERRATUM_A006475
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007075
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
- select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
select SYS_FSL_ERRATUM_A007798
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SFP_BE
#if defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_LIODN
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_ARCH_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_T1024)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_T2080)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
-#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_C29X)
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CPC_REINIT_F
#endif
-#define CONFIG_KEY_REVOCATION
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
#endif
#endif
#endif
-#if defined(CONFIG_TARGET_C29XPCIE)
-#define CONFIG_KEY_REVOCATION
-#endif
-
#if defined(CONFIG_ARCH_P3041) || \
defined(CONFIG_ARCH_P4080) || \
defined(CONFIG_ARCH_P5040) || \
#define sfp_in32(a) in_be32(a)
#define sfp_out32(a, v) out_be32(a, v)
#define sfp_in16(a) in_be16(a)
-#else
-#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
#endif
/* Number of SRKH registers */