x86: baytrail: Support multiple microcode copies

Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 8f0e192db4986e9a13442b7acd65594f81fb6f17..d646987ff885a5697cf697a25bbf042c40632d49 100644 (file)
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -230,6 +230,12 @@
                update@0 {
 #include "microcode/m0230671117.dtsi"
                };
+               update@1 {
+#include "microcode/m0130673322.dtsi"
+               };
+               update@2 {
+#include "microcode/m0130679901.dtsi"
+               };
        };
 
 };

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index daac24e4511a6d7933cef3743821991920a16578..f4e0a353f2b1f5c219ed777d932f1a0921752948 100644 (file)
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -256,6 +256,9 @@
                update@0 {
 #include "microcode/m0130673322.dtsi"
                };
+               update@1 {
+#include "microcode/m0130679901.dtsi"
+               };
        };
 
 };