]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
riscv: t-head: licheepi4a: initial support added
authorYixun Lan <dlan@gentoo.org>
Sat, 8 Jul 2023 11:24:32 +0000 (19:24 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Wed, 12 Jul 2023 05:21:41 +0000 (13:21 +0800)
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's
TH1520 SoC, only minimal device tree and serial console are enabled,
so it's capable of chain booting from T-HEAD's vendor u-boot.

Reviewed-by: Wei Fu <wefu@redhat.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
arch/riscv/Kconfig
board/thead/th1520_lpi4a/Kconfig [new file with mode: 0644]
board/thead/th1520_lpi4a/MAINTAINERS [new file with mode: 0644]
board/thead/th1520_lpi4a/Makefile [new file with mode: 0644]
board/thead/th1520_lpi4a/board.c [new file with mode: 0644]
include/configs/th1520_lpi4a.h [new file with mode: 0644]

index de7d5a954926ada44f2d93ccb6e9b9110a57b7a9..867cbcbe74eb52f1c4a98a4e488f7699442cd01d 100644 (file)
@@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED
 config TARGET_STARFIVE_VISIONFIVE2
        bool "Support StarFive VisionFive2 Board"
 
+config TARGET_TH1520_LPI4A
+       bool "Support Sipeed's TH1520 Lichee PI 4A Board"
+       select SYS_CACHE_SHIFT_6
+
 config TARGET_SIPEED_MAIX
        bool "Support Sipeed Maix Board"
        select SYS_CACHE_SHIFT_6
@@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
+source "board/thead/th1520_lpi4a/Kconfig"
 source "board/openpiton/riscv64/Kconfig"
 source "board/sipeed/maix/Kconfig"
 source "board/starfive/visionfive2/Kconfig"
diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig
new file mode 100644 (file)
index 0000000..6222461
--- /dev/null
@@ -0,0 +1,42 @@
+if TARGET_TH1520_LPI4A
+
+config ARCH_THEAD
+       bool
+       default y
+
+config SYS_BOARD
+       default "th1520_lpi4a"
+
+config SYS_VENDOR
+       default "thead"
+
+config SYS_CPU
+       default "generic"
+
+config SYS_CONFIG_NAME
+       default "th1520_lpi4a"
+
+config TEXT_BASE
+       default 0x01b00000 if SPL
+       default 0x01c00000 if !RISCV_SMODE
+       default 0x01c00000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+       default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+       default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS
+       def_bool y
+       select ARCH_EARLY_INIT_R
+       imply CPU
+       imply CPU_RISCV
+       imply RISCV_TIMER if RISCV_SMODE
+       imply CMD_CPU
+       imply SMP
+       imply SUPPORT_OF_CONTROL
+       imply OF_CONTROL
+       imply OF_REAL
+
+endif
diff --git a/board/thead/th1520_lpi4a/MAINTAINERS b/board/thead/th1520_lpi4a/MAINTAINERS
new file mode 100644 (file)
index 0000000..36c7ab7
--- /dev/null
@@ -0,0 +1,7 @@
+Lichee PI 4A
+M:     Wei Fu <wefu@redhat.com>
+M:     Yixun Lan <dlan@gentoo.org>
+S:     Maintained
+F:     board/thead/th1520_lpi4a/
+F:     configs/th1520_lpi4a_defconfig
+F:     doc/board/thead/lpi4a.rst
diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile
new file mode 100644 (file)
index 0000000..9671b3b
--- /dev/null
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023, Yixun Lan <dlan@gentoo.org>
+
+obj-y += board.o
diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c
new file mode 100644 (file)
index 0000000..16c3e45
--- /dev/null
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023, Yixun Lan <dlan@gentoo.org>
+ *
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+
+int board_init(void)
+{
+       enable_caches();
+
+       return 0;
+}
diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h
new file mode 100644 (file)
index 0000000..87496a5
--- /dev/null
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Yixun Lan <dlan@gentoo.org>
+ *
+ */
+
+#ifndef __TH1520_LPI4A_H
+#define __TH1520_LPI4A_H
+
+#include <linux/sizes.h>
+
+#define CFG_SYS_SDRAM_BASE             0x00000000
+
+#define UART_BASE      0xffe7014000
+#define UART_REG_WIDTH  32
+
+/* Environment options */
+
+#define CFG_EXTRA_ENV_SETTINGS \
+       "PS1=[LPi4A]# \0"
+
+#endif /* __TH1520_LPI4A_H */