dm: pci: Use driver model PCI API in auto-config

At present we are using legacy functions even in the auto-configuration code
used by driver model. Add a new pci_auto.c version which uses the correct
API.

Create a new pci_internal.h header to hold functions that are used within
the PCI subsystem, but are not exported to other drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 6b761b453d92e4ff3b2656ddc7fc9afad4bdac50..62232fcfb6c3d62893bce91483193c9f958b74d9 100644 (file)
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -6,15 +6,15 @@
 #
 
 ifneq ($(CONFIG_DM_PCI),)
-obj-$(CONFIG_PCI) += pci-uclass.o
+obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
 obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
 obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
 obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
 obj-$(CONFIG_X86) += pci_x86.o
 else
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
 endif
-obj-$(CONFIG_PCI) +=  pci_auto_common.o pci_auto_old.o pci_common.o pci_rom.o
+obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o pci_rom.o
 
 obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
 obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 28280553dadd80f4fa02cb697bd69fb5f9e4d8df..792d9cbeebf487cc93afdb7a7666803462991546 100644 (file)
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -17,6 +17,7 @@
 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
 #include <asm/fsp/fsp_support.h>
 #endif
+#include "pci_internal.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -404,7 +405,7 @@ int pci_auto_config_devices(struct udevice *bus)
                int ret;
 
                debug("%s: device %s\n", __func__, dev->name);
-               ret = pciauto_config_device(hose, dm_pci_get_bdf(dev));
+               ret = dm_pciauto_config_device(dev);
                if (ret < 0)
                        return ret;
                max_bus = ret;
@@ -419,26 +420,16 @@ int pci_auto_config_devices(struct udevice *bus)
        return sub_bus;
 }
 
-int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
+int dm_pci_hose_probe_bus(struct udevice *bus)
 {
-       struct udevice *parent, *bus;
        int sub_bus;
        int ret;
 
        debug("%s\n", __func__);
-       parent = hose->bus;
-
-       /* Find the bus within the parent */
-       ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
-       if (ret) {
-               debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
-                     bdf, parent->name, ret);
-               return ret;
-       }
 
        sub_bus = pci_get_bus_max() + 1;
        debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
-       pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
+       dm_pciauto_prescan_setup_bridge(bus, sub_bus);
 
        ret = device_probe(bus);
        if (ret) {
@@ -452,7 +443,7 @@ int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
                return -EPIPE;
        }
        sub_bus = pci_get_bus_max();
-       pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
+       dm_pciauto_postscan_setup_bridge(bus, sub_bus);
 
        return sub_bus;
 }

diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
new file mode 100644 (file)
index 0000000..842eafc
--- /dev/null
+++ b/drivers/pci/pci_auto.c
@@ -0,0 +1,386 @@
+/*
+ * PCI autoconfiguration library
+ *
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pci.h>
+
+/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
+#endif
+
+void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
+                            struct pci_region *mem,
+                            struct pci_region *prefetch, struct pci_region *io,
+                            bool enum_only)
+{
+       u32 bar_response;
+       pci_size_t bar_size;
+       u16 cmdstat = 0;
+       int bar, bar_nr = 0;
+       u8 header_type;
+       int rom_addr;
+       pci_addr_t bar_value;
+       struct pci_region *bar_res;
+       int found_mem64 = 0;
+       u16 class;
+
+       dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+       cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
+                       PCI_COMMAND_MASTER;
+
+       for (bar = PCI_BASE_ADDRESS_0;
+            bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
+               /* Tickle the BAR and get the response */
+               if (!enum_only)
+                       dm_pci_write_config32(dev, bar, 0xffffffff);
+               dm_pci_read_config32(dev, bar, &bar_response);
+
+               /* If BAR is not implemented go to the next BAR */
+               if (!bar_response)
+                       continue;
+
+               found_mem64 = 0;
+
+               /* Check the BAR type and set our address mask */
+               if (bar_response & PCI_BASE_ADDRESS_SPACE) {
+                       bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
+                                  & 0xffff) + 1;
+                       if (!enum_only)
+                               bar_res = io;
+
+                       debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
+                             bar_nr, (unsigned long long)bar_size);
+               } else {
+                       if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+                            PCI_BASE_ADDRESS_MEM_TYPE_64) {
+                               u32 bar_response_upper;
+                               u64 bar64;
+
+                               if (!enum_only) {
+                                       dm_pci_write_config32(dev, bar + 4,
+                                                             0xffffffff);
+                               }
+                               dm_pci_read_config32(dev, bar + 4,
+                                                    &bar_response_upper);
+
+                               bar64 = ((u64)bar_response_upper << 32) |
+                                               bar_response;
+
+                               bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
+                                               + 1;
+                               if (!enum_only)
+                                       found_mem64 = 1;
+                       } else {
+                               bar_size = (u32)(~(bar_response &
+                                               PCI_BASE_ADDRESS_MEM_MASK) + 1);
+                       }
+                       if (!enum_only) {
+                               if (prefetch && (bar_response &
+                                           PCI_BASE_ADDRESS_MEM_PREFETCH)) {
+                                       bar_res = prefetch;
+                               } else {
+                                       bar_res = mem;
+                               }
+                       }
+
+                       debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
+                             bar_nr, bar_res == prefetch ? "Prf" : "Mem",
+                             (unsigned long long)bar_size);
+               }
+
+               if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
+                                                         &bar_value) == 0) {
+                       /* Write it out and update our limit */
+                       dm_pci_write_config32(dev, bar, (u32)bar_value);
+
+                       if (found_mem64) {
+                               bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+                               dm_pci_write_config32(dev, bar,
+                                                     (u32)(bar_value >> 32));
+#else
+                               /*
+                                * If we are a 64-bit decoder then increment to
+                                * the upper 32 bits of the bar and force it to
+                                * locate in the lower 4GB of memory.
+                                */
+                               dm_pci_write_config32(dev, bar, 0x00000000);
+#endif
+                       }
+               }
+
+               cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
+                       PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
+
+               debug("\n");
+
+               bar_nr++;
+       }
+
+       if (!enum_only) {
+               /* Configure the expansion ROM address */
+               dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+               header_type &= 0x7f;
+               if (header_type != PCI_HEADER_TYPE_CARDBUS) {
+                       rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
+                               PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
+                       dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
+                       dm_pci_read_config32(dev, rom_addr, &bar_response);
+                       if (bar_response) {
+                               bar_size = -(bar_response & ~1);
+                               debug("PCI Autoconfig: ROM, size=%#x, ",
+                                     (unsigned int)bar_size);
+                               if (pciauto_region_allocate(mem, bar_size,
+                                                           &bar_value) == 0) {
+                                       dm_pci_write_config32(dev, rom_addr,
+                                                             bar_value);
+                               }
+                               cmdstat |= PCI_COMMAND_MEMORY;
+                               debug("\n");
+                       }
+               }
+       }
+
+       /* PCI_COMMAND_IO must be set for VGA device */
+       dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+       if (class == PCI_CLASS_DISPLAY_VGA)
+               cmdstat |= PCI_COMMAND_IO;
+
+       dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
+       dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
+                            CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+       dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
+}
+
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+       struct pci_region *pci_mem;
+       struct pci_region *pci_prefetch;
+       struct pci_region *pci_io;
+       u16 cmdstat, prefechable_64;
+       /* The root controller has the region information */
+       struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+       pci_mem = ctlr_hose->pci_mem;
+       pci_prefetch = ctlr_hose->pci_prefetch;
+       pci_io = ctlr_hose->pci_io;
+
+       dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+       dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
+       prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+       /* Configure bus number registers */
+       dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
+                            PCI_BUS(dm_pci_get_bdf(dev)));
+       dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus);
+       dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
+
+       if (pci_mem) {
+               /* Round memory allocator to 1MB boundary */
+               pciauto_region_align(pci_mem, 0x100000);
+
+               /*
+                * Set up memory and I/O filter limits, assume 32-bit
+                * I/O space
+                */
+               dm_pci_write_config16(dev, PCI_MEMORY_BASE,
+                                     (pci_mem->bus_lower & 0xfff00000) >> 16);
+
+               cmdstat |= PCI_COMMAND_MEMORY;
+       }
+
+       if (pci_prefetch) {
+               /* Round memory allocator to 1MB boundary */
+               pciauto_region_align(pci_prefetch, 0x100000);
+
+               /*
+                * Set up memory and I/O filter limits, assume 32-bit
+                * I/O space
+                */
+               dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
+                               (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+               if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+                       dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
+                                             pci_prefetch->bus_lower >> 32);
+#else
+                       dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
+#endif
+
+               cmdstat |= PCI_COMMAND_MEMORY;
+       } else {
+               /* We don't support prefetchable memory for now, so disable */
+               dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
+               dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+               if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
+                       dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
+                       dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+               }
+       }
+
+       if (pci_io) {
+               /* Round I/O allocator to 4KB boundary */
+               pciauto_region_align(pci_io, 0x1000);
+
+               dm_pci_write_config8(dev, PCI_IO_BASE,
+                                    (pci_io->bus_lower & 0x0000f000) >> 8);
+               dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
+                                     (pci_io->bus_lower & 0xffff0000) >> 16);
+
+               cmdstat |= PCI_COMMAND_IO;
+       }
+
+       /* Enable memory and I/O accesses, enable bus master */
+       dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
+}
+
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+       struct pci_region *pci_mem;
+       struct pci_region *pci_prefetch;
+       struct pci_region *pci_io;
+
+       /* The root controller has the region information */
+       struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+       pci_mem = ctlr_hose->pci_mem;
+       pci_prefetch = ctlr_hose->pci_prefetch;
+       pci_io = ctlr_hose->pci_io;
+
+       /* Configure bus number registers */
+       dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus);
+
+       if (pci_mem) {
+               /* Round memory allocator to 1MB boundary */
+               pciauto_region_align(pci_mem, 0x100000);
+
+               dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
+                                     (pci_mem->bus_lower - 1) >> 16);
+       }
+
+       if (pci_prefetch) {
+               u16 prefechable_64;
+
+               dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
+                                    &prefechable_64);
+               prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+               /* Round memory allocator to 1MB boundary */
+               pciauto_region_align(pci_prefetch, 0x100000);
+
+               dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
+                                     (pci_prefetch->bus_lower - 1) >> 16);
+               if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+                       dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
+                                       (pci_prefetch->bus_lower - 1) >> 32);
+#else
+                       dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+#endif
+       }
+
+       if (pci_io) {
+               /* Round I/O allocator to 4KB boundary */
+               pciauto_region_align(pci_io, 0x1000);
+
+               dm_pci_write_config8(dev, PCI_IO_LIMIT,
+                               ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
+               dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
+                               ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
+       }
+}
+
+/*
+ * HJF: Changed this to return int. I think this is required
+ * to get the correct result when scanning bridges
+ */
+int dm_pciauto_config_device(struct udevice *dev)
+{
+       struct pci_region *pci_mem;
+       struct pci_region *pci_prefetch;
+       struct pci_region *pci_io;
+       unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
+       unsigned short class;
+       bool enum_only = false;
+       int n;
+
+#ifdef CONFIG_PCI_ENUM_ONLY
+       enum_only = true;
+#endif
+       /* The root controller has the region information */
+       struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+       pci_mem = ctlr_hose->pci_mem;
+       pci_prefetch = ctlr_hose->pci_prefetch;
+       pci_io = ctlr_hose->pci_io;
+
+       dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+
+       switch (class) {
+       case PCI_CLASS_BRIDGE_PCI:
+               debug("PCI Autoconfig: Found P2P bridge, device %d\n",
+                     PCI_DEV(dm_pci_get_bdf(dev)));
+
+               dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
+                                       enum_only);
+
+               n = dm_pci_hose_probe_bus(dev);
+               if (n < 0)
+                       return n;
+               sub_bus = (unsigned int)n;
+               break;
+
+       case PCI_CLASS_BRIDGE_CARDBUS:
+               /*
+                * just do a minimal setup of the bridge,
+                * let the OS take care of the rest
+                */
+               dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
+                                       enum_only);
+
+               debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
+                     PCI_DEV(dm_pci_get_bdf(dev)));
+
+               break;
+
+#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
+       case PCI_CLASS_BRIDGE_OTHER:
+               debug("PCI Autoconfig: Skipping bridge device %d\n",
+                     PCI_DEV(dm_pci_get_bdf(dev)));
+               break;
+#endif
+#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+       case PCI_CLASS_BRIDGE_OTHER:
+               /*
+                * The host/PCI bridge 1 seems broken in 8349 - it presents
+                * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
+                * device claiming resources io/mem/irq.. we only allow for
+                * the PIMMR window to be allocated (BAR0 - 1MB size)
+                */
+               debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
+               dm_pciauto_setup_device(dev, 0, hose->pci_mem,
+                                       hose->pci_prefetch, hose->pci_io,
+                                       enum_only);
+               break;
+#endif
+
+       case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+               debug("PCI AutoConfig: Found PowerPC device\n");
+
+       default:
+               dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
+                                       enum_only);
+               break;
+       }
+
+       return sub_bus;
+}

diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c
index 1ff88b1ac14bd0c5ec4ecf84c443632c9a14d42f..9126f78b890b199f6aab2c6ac0927160e49e7263 100644 (file)
--- a/drivers/pci/pci_auto_old.c
+++ b/drivers/pci/pci_auto_old.c
@@ -180,18 +180,9 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
        struct pci_region *pci_io;
        u16 cmdstat, prefechable_64;
 
-#ifdef CONFIG_DM_PCI
-       /* The root controller has the region information */
-       struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
-       pci_mem = ctlr_hose->pci_mem;
-       pci_prefetch = ctlr_hose->pci_prefetch;
-       pci_io = ctlr_hose->pci_io;
-#else
        pci_mem = hose->pci_mem;
        pci_prefetch = hose->pci_prefetch;
        pci_io = hose->pci_io;
-#endif
 
        pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
        pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
@@ -199,15 +190,10 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
        prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 
        /* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
-       pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
-       pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
-#else
        pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
                                   PCI_BUS(dev) - hose->first_busno);
        pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
                                   sub_bus - hose->first_busno);
-#endif
        pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 
        if (pci_mem) {
@@ -274,26 +260,13 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose,
        struct pci_region *pci_prefetch;
        struct pci_region *pci_io;
 
-#ifdef CONFIG_DM_PCI
-       /* The root controller has the region information */
-       struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
-       pci_mem = ctlr_hose->pci_mem;
-       pci_prefetch = ctlr_hose->pci_prefetch;
-       pci_io = ctlr_hose->pci_io;
-#else
        pci_mem = hose->pci_mem;
        pci_prefetch = hose->pci_prefetch;
        pci_io = hose->pci_io;
-#endif
 
        /* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
-       pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
-#else
        pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
                                   sub_bus - hose->first_busno);
-#endif
 
        if (pci_mem) {
                /* Round memory allocator to 1MB boundary */
@@ -353,18 +326,9 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
        unsigned short class;
        int n;
 
-#ifdef CONFIG_DM_PCI
-       /* The root controller has the region information */
-       struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
-       pci_mem = ctlr_hose->pci_mem;
-       pci_prefetch = ctlr_hose->pci_prefetch;
-       pci_io = ctlr_hose->pci_io;
-#else
        pci_mem = hose->pci_mem;
        pci_prefetch = hose->pci_prefetch;
        pci_io = hose->pci_io;
-#endif
 
        pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 
@@ -376,12 +340,6 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
                pciauto_setup_device(hose, dev, 2, pci_mem,
                                     pci_prefetch, pci_io);
 
-#ifdef CONFIG_DM_PCI
-               n = dm_pci_hose_probe_bus(hose, dev);
-               if (n < 0)
-                       return n;
-               sub_bus = (unsigned int)n;
-#else
                /* Passing in current_busno allows for sibling P2P bridges */
                hose->current_busno++;
                pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
@@ -396,7 +354,6 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
                pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 
                sub_bus = hose->current_busno;
-#endif
                break;
 
        case PCI_CLASS_BRIDGE_CARDBUS:
@@ -410,9 +367,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
                debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
                      PCI_DEV(dev));
 
-#ifndef CONFIG_DM_PCI
                hose->current_busno++;
-#endif
                break;
 
 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)

diff --git a/drivers/pci/pci_internal.h b/drivers/pci/pci_internal.h
new file mode 100644 (file)
index 0000000..0867575
--- /dev/null
+++ b/drivers/pci/pci_internal.h
@@ -0,0 +1,50 @@
+/*
+ * Internal PCI functions, not exported outside drivers/pci
+ *
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __pci_internal_h
+#define __pci_internal_h
+
+/**
+ * dm_pciauto_prescan_setup_bridge() - Set up a bridge for scanning
+ *
+ * This gets a bridge ready so that its downstream devices can be scanned.
+ * It sets up the bus number and memory range registers. Once the scan is
+ * completed, dm_pciauto_postscan_setup_bridge() should be called.
+ *
+ * @dev:       Bridge device to be scanned
+ * @sub_bus:   Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_postscan_setup_bridge() - Finish set up of a bridge after scanning
+ *
+ * This should be called after a bus scan is complete. It adjusts the memory
+ * ranges to fit with the devices actually found on the other side (downstream)
+ * of the bridge.
+ *
+ * @dev:       Bridge device that was scanned
+ * @sub_bus:   Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_config_device() - Configure a PCI device ready for use
+ *
+ * If the device is a bridge, downstream devices will be probed.
+ *
+ * @dev:       Device to configure
+ * @return the maximum PCI bus number found by this device. If there are no
+ * bridges, this just returns the device's bus number. If the device is a
+ * bridge then it will return a larger number, depending on the devices on
+ * that bridge. On error, returns a -ve error number.
+ */
+int dm_pciauto_config_device(struct udevice *dev);
+
+#endif

diff --git a/include/pci.h b/include/pci.h
index 586197610b9791e5ba73a18397ac15ffc667b95a..182290c3c27650b253d48e320f42af271eda696c 100644 (file)
--- a/include/pci.h
+++ b/include/pci.h
@@ -995,7 +995,7 @@ int pci_find_device_id(struct pci_device_id *ids, int index,
  * @bdf:       PCI bus address to scan (PCI_BUS(bdf) is the bus number)
  * @return 0 if OK, -ve on error
  */
-int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf);
+int dm_pci_hose_probe_bus(struct udevice *bus);
 
 /**
  * pci_bus_read_config() - Read a configuration value from a device