actux4 xscale/ixp
dvlhost xscale/ixp
-Andrea Scian <andrea.scian@dave-tech.it>
-
- B2 ARM7TDMI (S3C44B0X)
-
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)
#########################################################################
LIST_ARM7=" \
- B2 \
ep7312 \
evb4510 \
impa7 \
+++ /dev/null
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialization
- */
-
-int board_init (void)
-{
- u32 temp;
-
- /* Configuration Port Control Register*/
- /* Port A */
- PCONA = 0x3ff;
-
- /* Port B */
- PCONB = 0xff;
- PDATB = 0xFFFF;
-
- /* Port C */
- /*
- PCONC = 0xff55ff15;
- PDATC = 0x0;
- PUPC = 0xffff;
- */
-
- /* Port D */
- /*
- PCOND = 0xaaaa;
- PUPD = 0xff;
- */
-
- /* Port E */
- PCONE = 0x0001aaa9;
- PDATE = 0x0;
- PUPE = 0xff;
-
- /* Port F */
- PCONF = 0x124955;
- PDATF = 0xff; /* B2-eth_reset tied high level */
- /*
- PUPF = 0x1e3;
- */
-
- /* Port G */
- PUPG = 0x1;
- PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/
-
- INTMSK = 0x03fffeff;
- INTCON = 0x05;
-
- /*
- Configure chip ethernet interrupt as High level
- Port G EINT 0-7 EINT0 -> CHIP ETHERNET
- */
- temp = EXTINT;
- temp &= ~0x7;
- temp |= 0x1; /*LEVEL_HIGH*/
- EXTINT = temp;
-
- /*
- Reset SMSC LAN91C96 chip
- */
- temp= PCONF;
- temp |= 0x00000040;
- PCONF = temp;
-
- /* Reset high */
- temp = PDATF;
- temp |= (1 << 3);
- PDATF = temp;
-
- /* Short delay */
- for (temp=0;temp<10;temp++)
- {
- /* NOP */
- }
-
- /* Reset low */
- temp = PDATF;
- temp &= ~(1 << 3);
- PDATF = temp;
-
- /* arch number MACH_TYPE_MBA44B0 */
- gd->bd->bi_arch_number = MACH_TYPE_S3C44B0;
-
- /* location of boot parameters */
- gd->bd->bi_boot_params = 0x0c000100;
-
- return 0;
-}
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := B2.o flash.o
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x0C100000
-
-PLATFORM_CPPFLAGS += -Uarm
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-#ifdef __DEBUG_START_FROM_SRAM__
- return CONFIG_SYS_DUMMY_FLASH_SIZE;
-#else
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (0, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-#endif
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
- * Modified By MATTO
- *
- * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-/*
- * Documentation:
- * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
- * Advanced Developer's manual, December 1999
- *
- * Intel has a very hard to find SDRAM configurator on their web site:
- * http://appzone.intel.com/hcd/sa1110/memory/index.asp
- *
- * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
- * appears to be true, but it might be possible that somebody designs a
- * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
- *
- * 04-10-2001: SELETZ
- * - separated memory config for multiple platform support
- * - perform SA1110 Hardware Reset Procedure
- *
- */
-
-.equ B0_Tacs, 0x0 /* 0clk */
-.equ B0_Tcos, 0x0 /* 0clk */
-.equ B0_Tacc, 0x4 /* 6clk */
-.equ B0_Tcoh, 0x0 /* 0clk */
-.equ B0_Tah, 0x0 /* 0clk */
-.equ B0_Tacp, 0x0 /* 0clk */
-.equ B0_PMC, 0x0 /* normal(1data) */
-/* Bank 1 parameter */
-.equ B1_Tacs, 0x3 /* 4clk */
-.equ B1_Tcos, 0x3 /* 4clk */
-.equ B1_Tacc, 0x7 /* 14clkv */
-.equ B1_Tcoh, 0x3 /* 4clk */
-.equ B1_Tah, 0x3 /* 4clk */
-.equ B1_Tacp, 0x3 /* 6clk */
-.equ B1_PMC, 0x0 /* normal(1data) */
-
-/* Bank 2 parameter - LAN91C96 */
-.equ B2_Tacs, 0x3 /* 4clk */
-.equ B2_Tcos, 0x3 /* 4clk */
-.equ B2_Tacc, 0x7 /* 14clk */
-.equ B2_Tcoh, 0x3 /* 4clk */
-.equ B2_Tah, 0x3 /* 4clk */
-.equ B2_Tacp, 0x3 /* 6clk */
-.equ B2_PMC, 0x0 /* normal(1data) */
-
-/* Bank 3 parameter */
-.equ B3_Tacs, 0x3 /* 4clk */
-.equ B3_Tcos, 0x3 /* 4clk */
-.equ B3_Tacc, 0x7 /* 14clk */
-.equ B3_Tcoh, 0x3 /* 4clk */
-.equ B3_Tah, 0x3 /* 4clk */
-.equ B3_Tacp, 0x3 /* 6clk */
-.equ B3_PMC, 0x0 /* normal(1data) */
-
-/* Bank 4 parameter */
-.equ B4_Tacs, 0x3 /* 4clk */
-.equ B4_Tcos, 0x3 /* 4clk */
-.equ B4_Tacc, 0x7 /* 14clk */
-.equ B4_Tcoh, 0x3 /* 4clk */
-.equ B4_Tah, 0x3 /* 4clk */
-.equ B4_Tacp, 0x3 /* 6clk */
-.equ B4_PMC, 0x0 /* normal(1data) */
-
-/* Bank 5 parameter */
-.equ B5_Tacs, 0x3 /* 4clk */
-.equ B5_Tcos, 0x3 /* 4clk */
-.equ B5_Tacc, 0x7 /* 14clk */
-.equ B5_Tcoh, 0x3 /* 4clk */
-.equ B5_Tah, 0x3 /* 4clk */
-.equ B5_Tacp, 0x3 /* 6clk */
-.equ B5_PMC, 0x0 /* normal(1data) */
-
-/* Bank 6(if SROM) parameter */
-.equ B6_Tacs, 0x3 /* 4clk */
-.equ B6_Tcos, 0x3 /* 4clk */
-.equ B6_Tacc, 0x7 /* 14clk */
-.equ B6_Tcoh, 0x3 /* 4clk */
-.equ B6_Tah, 0x3 /* 4clk */
-.equ B6_Tacp, 0x3 /* 6clk */
-.equ B6_PMC, 0x0 /* normal(1data) */
-
-/* Bank 7(if SROM) parameter */
-.equ B7_Tacs, 0x3 /* 4clk */
-.equ B7_Tcos, 0x3 /* 4clk */
-.equ B7_Tacc, 0x7 /* 14clk */
-.equ B7_Tcoh, 0x3 /* 4clk */
-.equ B7_Tah, 0x3 /* 4clk */
-.equ B7_Tacp, 0x3 /* 6clk */
-.equ B7_PMC, 0x0 /* normal(1data) */
-
-/* Bank 6 parameter */
-.equ B6_MT, 0x3 /* SDRAM */
-.equ B6_Trcd, 0x0 /* 2clk */
-.equ B6_SCAN, 0x0 /* 10bit */
-
-.equ B7_MT, 0x3 /* SDRAM */
-.equ B7_Trcd, 0x0 /* 2clk */
-.equ B7_SCAN, 0x0 /* 10bit */
-
-
-/* REFRESH parameter */
-.equ REFEN, 0x1 /* Refresh enable */
-.equ TREFMD, 0x0 /* CBR(CAS before RAS)/Auto refresh */
-.equ Trp, 0x0 /* 2clk */
-.equ Trc, 0x3 /* 0x1=5clk 0x3=11clk*/
-.equ Tchr, 0x0 /* 0x2=3clk 0x0=0clks */
-.equ REFCNT, 879
-
-MEMORY_CONFIG:
- .long 0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
- .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
- .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
- .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
- .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
- .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
- .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /*GCS6*/
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /*GCS7*/
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
- .word 0x17 /*SCLK power down mode, BANKSIZE 16M/16M*/
- .word 0x20 /*MRSR6 CL=2clk*/
- .word 0x20 /*MRSR7*/
-
-
-.globl lowlevel_init
-lowlevel_init:
-
- /*
- the next instruction fail due memory relocation...
- we'll find the right MEMORY_CONFIG address with the next 3 lines...
- */
- /*ldr r0, =MEMORY_CONFIG*/
- mov r0, pc
- ldr r1, =(0x38+4)
- sub r0, r0, r1
-
- ldmia r0, {r1-r13}
- ldr r0, =0x01c80000
- stmia r0, {r1-r13}
- mov pc, lr
xm250 arm pxa
zipitz2 arm pxa
zylonite arm pxa
-B2 arm s3c44b0 - dave
dnp1110 arm sa1100
gcplus arm sa1100
jornada arm sa1100
Board Arch CPU removed Commit last known maintainer/contact
=============================================================================
+B2 arm s3c44b0 - 2011-07-16 Andrea Scian <andrea.scian@dave-tech.it>
armadillo arm arm720t - 2011-07-16 Rowel Atienza <rowel@diwalabs.com>
assabet arm sa1100 - 2011-07-16 George G. Davis <gdavis@mvista.com>
trab arm S3C2400 - 2011-05-01 Gary Jennejohn <garyj@denx.de>
+++ /dev/null
-/*
- * (C) Copyright 2004
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * Configuation settings for the B2 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
-#define CONFIG_B2 1 /* on an B2 Board */
-#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
-#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/
-
-
-#undef CONFIG_USE_IRQ /* don't need them anymore */
-
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024 )
-
-/*
- * Hardware drivers
- */
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */
-#define CONFIG_SMC_USE_32_BIT
-#undef CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_S3C44B0_SERIAL
-#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
-
-#define CONFIG_S3C44B0_I2C
-#define CONFIG_RTC_S3C44B0
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-
-#define CONFIG_NET_MULTI
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_ETHADDR 00:50:c2:1e:af:fb
-#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \
- ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb"
-#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_IPADDR 192.168.0.70
-#define CONFIG_SERVERIP 192.168.0.23
-#define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot"
-#define CONFIG_BOOTCOMMAND "bootm 20000 f0000"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0C400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x0c700000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* 1 kHz */
-
- /* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
-#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x0 /* environment starts at the beginning of the EEPROM */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (STM24C02W6) for environment
- */
-#define CONFIG_HARD_I2C /* I2c with hardware support */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0xA8 /* EEPROM STM24C02W6 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/* Flash banks JFFS2 should use */
-/*
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 2
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-*/
-
-/*
- Linux TAGs (see arch/arm/lib/armlinux.c)
-*/
-#define CONFIG_CMDLINE_TAG
-#undef CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#endif /* __CONFIG_H */
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