ppc4xx: Adapt DLVision 10G to new FPGA firmware

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index 86a3ec882b98878916927f8b03bb01877debb2ef..8b80533d9828c9737811488c27d1620258a462c3 100644 (file)
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -110,6 +110,11 @@ int board_early_init_f(void)
 
        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
                ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+               u16 *reflection_target = &fpga->reflection_low;
+#else
+               u16 *reflection_target = &fpga->reflection_high;
+#endif
                /*
                 * wait for fpga out of reset
                 */
@@ -117,9 +122,11 @@ int board_early_init_f(void)
                while (1) {
                        out_le16(&fpga->reflection_low,
                                REFLECTION_TESTPATTERN);
-                       if (in_le16(&fpga->reflection_high) ==
+
+                       if (in_le16(reflection_target) ==
                                REFLECTION_TESTPATTERN_INV)
                                break;
+
                        udelay(100000);
                        if (ctr++ > 5) {
                                gd->fpga_state[k] |=

diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index d7b4fb21ddbe99b7ea2217e5978d12f1df0b725f..038854161fc505ee3df975d916cc803dfec3be67 100644 (file)
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -34,6 +34,8 @@
 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
 #define LATCH2_MC2_PRESENT_N 0x0080
 
+#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
+
 enum {
        UNITTYPE_VIDEO_USER = 0,
        UNITTYPE_MAIN_USER = 1,
@@ -63,6 +65,20 @@ enum {
        RAM_DDR2_64 = 2,
 };
 
+static unsigned int get_hwver(void)
+{
+       u16 latch3 = in_le16((void *)LATCH3_BASE);
+
+       return latch3 & 0x0003;
+}
+
+static unsigned int get_mc2_present(void)
+{
+       u16 latch2 = in_le16((void *)LATCH2_BASE);
+
+       return !(latch2 & LATCH2_MC2_PRESENT_N);
+}
+
 static void print_fpga_info(unsigned dev)
 {
        ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
@@ -210,7 +226,6 @@ static void print_fpga_info(unsigned dev)
 int checkboard(void)
 {
        char *s = getenv("serial#");
-       u16 latch2 = in_le16((void *)LATCH2_BASE);
 
        printf("Board: ");
 
@@ -224,7 +239,7 @@ int checkboard(void)
        puts("\n");
 
        print_fpga_info(0);
-       if (!(latch2 & LATCH2_MC2_PRESENT_N))
+       if (get_mc2_present())
                print_fpga_info(1);
 
        return 0;
@@ -234,15 +249,15 @@ int last_stage_init(void)
 {
        ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
        u16 versions = in_le16(&fpga->versions);
-       u16 latch2 = in_le16((void *)LATCH2_BASE);
 
        if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
                return 0;
 
-       if (!get_fpga_state(0))
+       if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
                osd_probe(0);
 
-       if (!(latch2 & LATCH2_MC2_PRESENT_N) && !get_fpga_state(1))
+       if (get_mc2_present() &&
+           (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
                osd_probe(1);
 
        return 0;

diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index ae209fa15737aa6b7cc2f48081db7f9d2aff9e8f..548b7ebd9496f16766e33358bcd8e59bbeb2b031 100644 (file)
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -136,6 +136,8 @@
 #define CONFIG_SYS_LATCH1_RESET                0xffcf
 #define CONFIG_SYS_LATCH1_BOOT         0xffff
 
+#define CONFIG_SYS_FPGA_NO_RFL_HI
+
 /*
  * FLASH organization
  */

diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 1fccd27cc02f16ffa93532b45be1533b0868e49a..eaf6daafb9b653cb61f0a7e00c4df22830c691a5 100644 (file)
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -94,13 +94,11 @@ typedef struct ihs_fpga {
        u16 extended_interrupt; /* 0x001c */
        u16 reserved_1[9];      /* 0x001e */
        ihs_i2c_t i2c;          /* 0x0030 */
-       u16 reserved_2[35];     /* 0x0038 */
-       u16 reflection_high;    /* 0x007e */
-       u16 reserved_3[15];     /* 0x0080 */
+       u16 reserved_2[51];     /* 0x0038 */
        u16 videocontrol;       /* 0x009e */
-       u16 reserved_4[176];    /* 0x00a0 */
+       u16 reserved_3[176];    /* 0x00a0 */
        ihs_osd_t osd;          /* 0x0200 */
-       u16 reserved_5[764];    /* 0x0208 */
+       u16 reserved_4[764];    /* 0x0208 */
        u16 videomem;           /* 0x0800 */
 } ihs_fpga_t;
 #endif