clk: zynq: Show watchdog clock rate properly

watchdog clock is also connected to cpu 1X clocksource.

Zynq> clk dump
...

Before:
      swdt          4294967290
After:
      swdt           111111110

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index 50f2a65c205edc1dbc41c2d6c1a8a5f8d260b314..3845e0730978e602e6df83e317c8fe1a2ab0e846 100644 (file)
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -394,7 +394,7 @@ static ulong zynq_clk_get_rate(struct clk *clk)
                return zynq_clk_get_peripheral_rate(priv, id, two_divs);
        case dma_clk:
                return zynq_clk_get_cpu_rate(priv, cpu_2x_clk);
-       case usb0_aper_clk ... smc_aper_clk:
+       case usb0_aper_clk ... swdt_clk:
                return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
        default:
                return -ENXIO;