sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3

Secure Memory Touch Arbiter is the same thing as the TrustZone
Protection Controller found on A31/A31s.

Access to many peripherals on the H3 can be controlled by the SMTA,
and the settings default to secure access only.

This patch supports the new settings, and sets them to allow non-secure
access.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index dfb0a3e3c099a5bd9615f3ff0bac0d8915279805..ce8e5717e702314961be4a57caa7b0db5d21138a 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN8I)      += clock_sun6i.o
 endif
 obj-$(CONFIG_MACH_SUN9I)       += clock_sun9i.o
 obj-$(CONFIG_MACH_SUN6I)       += tzpc.o
+obj-$(CONFIG_MACH_SUN8I_H3)    += tzpc.o
 
 obj-$(CONFIG_AXP152_POWER)     += pmic_bus.o
 obj-$(CONFIG_AXP209_POWER)     += pmic_bus.o

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 7dfb7f5340dba4c93ff3ba7a67c33221aef613c7..eb5f4b686ea7416f02cb9377d2e4d78413ad350e 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -127,8 +127,8 @@ void s_init(void)
                "orr r0, r0, #1 << 6\n"
                "mcr p15, 0, r0, c1, c0, 1\n");
 #endif
-#if defined CONFIG_MACH_SUN6I
-       /* Enable non-secure access to the RTC */
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
+       /* Enable non-secure access to some peripherals */
        tzpc_init();
 #endif
 

diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
index 5c9c69b20bf89cee6c953525a1a0d0c798885e40..6c8a0fd9a25bab942a67a4118be9500726d75a32 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
@@ -13,6 +13,15 @@ void tzpc_init(void)
 {
        struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;
 
+#ifdef CONFIG_MACH_SUN6I
        /* Enable non-secure access to the RTC */
-       writel(SUNXI_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
+       writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
+#endif
+
+#ifdef CONFIG_MACH_SUN8I_H3
+       /* Enable non-secure access to all peripherals */
+       writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set);
+       writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set);
+       writel(SUN8I_H3_TZPC_DECPORT2_ALL, &tzpc->decport2_set);
+#endif
 }

diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h
index ba4d43bc3a2ec248a830b6f23dc7b8a895921b5d..95c55cd4d1307d99c4c09f17e94de4429d2a3355 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
@@ -13,10 +13,21 @@ struct sunxi_tzpc {
        u32 decport0_status;    /* 0x04 Status of decode protection port 0 */
        u32 decport0_set;       /* 0x08 Set decode protection port 0 */
        u32 decport0_clear;     /* 0x0c Clear decode protection port 0 */
+       /* For A80 and later SoCs */
+       u32 decport1_status;    /* 0x10 Status of decode protection port 1 */
+       u32 decport1_set;       /* 0x14 Set decode protection port 1 */
+       u32 decport1_clear;     /* 0x18 Clear decode protection port 1 */
+       u32 decport2_status;    /* 0x1c Status of decode protection port 2 */
+       u32 decport2_set;       /* 0x20 Set decode protection port 2 */
+       u32 decport2_clear;     /* 0x24 Clear decode protection port 2 */
 };
 #endif
 
-#define SUNXI_TZPC_DECPORT0_RTC        (1 << 1)
+#define SUN6I_TZPC_DECPORT0_RTC        (1 << 1)
+
+#define SUN8I_H3_TZPC_DECPORT0_ALL  0xbe
+#define SUN8I_H3_TZPC_DECPORT1_ALL  0xff
+#define SUN8I_H3_TZPC_DECPORT2_ALL  0x7f
 
 void tzpc_init(void);