sunxi: Add support for I2C on H6 like SoCs

I2C support, especially R_I2C port, will be needed in future. Upcoming
support for H616 will need R_I2C to adjust DRAM voltage.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 426069fc69a4f89496c0c5b630443a8d3fa499fe..e83e84ab6cab040828d0129f27e65b071a075d8d 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -297,6 +297,7 @@ struct sunxi_ccm_reg {
 
 /* Module gate/reset shift*/
 #define RESET_SHIFT                    (16)
+#define GATE_SHIFT                     (0)
 
 /* DRAM clock bit field */
 #define DRAM_MOD_RESET                 BIT(30)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 36b142588fa67bb8e76bf344ee080736122ca4a4..edb9973cf2bd77492bb0fed1b798f276a134e4d8 100644 (file)
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -730,7 +730,7 @@ config I2C3_ENABLE
        See I2C0_ENABLE help text.
 endif
 
-if SUNXI_GEN_SUN6I
+if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
 config R_I2C_ENABLE
        bool "Enable the PRCM I2C/TWI controller"
        # This is used for the pmic on H3

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index ba8a26eb0d3634997ce2ca58a90902ecb175b62f..6bd466915c119670e2168c38d494217f8a6c981b 100644 (file)
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -2,6 +2,7 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
 
 #ifdef CONFIG_SPL_BUILD
 void clock_init_safe(void)
@@ -92,3 +93,31 @@ unsigned int clock_get_pll6(void)
        /* The register defines PLL6-4X, not plain PLL6 */
        return 24000000 / 4 * n / div1 / div2;
 }
+
+int clock_twi_onoff(int port, int state)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       struct sunxi_prcm_reg *const prcm =
+               (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+       u32 value, *ptr;
+       int shift;
+
+       value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT);
+
+       if (port == 5) {
+               shift = 0;
+               ptr = &prcm->twi_gate_reset;
+       } else {
+               shift = port;
+               ptr = &ccm->twi_gate_reset;
+       }
+
+       /* set the apb clock gate and reset for twi */
+       if (state)
+               setbits_le32(ptr, value << shift);
+       else
+               clrbits_le32(ptr, value << shift);
+
+       return 0;
+}