rockchip: clk: rk322x: fix assert clock value

BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index 4b599fbb242c68d63937f970fb291d95aec941d7..f09730c91b452be2880d7e5fcfb40b2f95fbce6f 100644 (file)
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -121,10 +121,10 @@ static void rkclk_init(struct rk322x_cru *cru)
        assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 
        pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
-       assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
+       assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
 
        hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
-       assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
+       assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
 
        rk_clrsetreg(&cru->cru_clksel_con[0],
                     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,