riscv: timer: Update the sifive clint timer driver to support aclint

This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.

The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.

[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c
index 939b99d937d166127ff12087cb050563f3619605..be45f17ddfbdfa5472ea4b8e6d3a8a32791c306a 100644 (file)
--- a/drivers/timer/sifive_clint_timer.c
+++ b/drivers/timer/sifive_clint_timer.c
@@ -12,12 +12,16 @@
 #include <dm/device-internal.h>
 #include <linux/err.h>
 
+#define CLINT_MTIME_OFFSET             0xbff8
+#define ACLINT_MTIME_OFFSET            0
+
 /* mtime register */
-#define MTIME_REG(base)                        ((ulong)(base) + 0xbff8)
+#define MTIME_REG(base, offset)                ((ulong)(base) + (offset))
 
 static u64 notrace sifive_clint_get_count(struct udevice *dev)
 {
-       return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
+       return readq((void __iomem *)MTIME_REG(dev_get_priv(dev),
+                                              dev_get_driver_data(dev)));
 }
 
 #if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
@@ -35,7 +39,8 @@ unsigned long notrace timer_early_get_rate(void)
  */
 u64 notrace timer_early_get_count(void)
 {
-       return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
+       return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
+                                              RISCV_MMODE_TIMEROFF));
 }
 #endif
 
@@ -53,8 +58,9 @@ static int sifive_clint_probe(struct udevice *dev)
 }
 
 static const struct udevice_id sifive_clint_ids[] = {
-       { .compatible = "riscv,clint0" },
-       { .compatible = "sifive,clint0" },
+       { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET },
+       { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET },
+       { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET },
        { }
 };
 

diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index 20135f569eb23c9481ec2387d6f00b3c20b592e7..f6d326bda0d85a021eeae77b2ef0d3c856d047a0 100644 (file)
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -11,8 +11,8 @@
 #define CFG_SYS_SDRAM_BASE             0x80000000
 
 #define RISCV_MMODE_TIMERBASE          0x2000000
+#define RISCV_MMODE_TIMEROFF           0xbff8
 #define RISCV_MMODE_TIMER_FREQ         1000000
-
 #define RISCV_SMODE_TIMER_FREQ         1000000
 
 /* Environment options */

diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index de3a0dcdd592cd27825598263f333fad399e335b..f208f5e20db927ec46a070ab2984a01544c6a94b 100644 (file)
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -14,8 +14,8 @@
 #define CFG_SYS_SDRAM_BASE             0x80000000
 
 #define RISCV_MMODE_TIMERBASE          0x2000000
+#define RISCV_MMODE_TIMEROFF           0xbff8
 #define RISCV_MMODE_TIMER_FREQ         1000000
-
 #define RISCV_SMODE_TIMER_FREQ         1000000
 
 /* Environment options */

diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
index 93dcc22d3662e0e4273c771bad22102c351e10d1..4ee02b8420f0beb945ba6bb05b302aabf4d285d8 100644 (file)
--- a/include/configs/starfive-visionfive2.h
+++ b/include/configs/starfive-visionfive2.h
@@ -9,6 +9,7 @@
 #define _STARFIVE_VISIONFIVE2_H
 
 #define RISCV_MMODE_TIMERBASE          0x2000000
+#define RISCV_MMODE_TIMEROFF           0xbff8
 #define RISCV_MMODE_TIMER_FREQ         4000000
 #define RISCV_SMODE_TIMER_FREQ         4000000