KARO TX25: Fix NAND Flash R/W cycle times

The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W
cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using
the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle)
resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses.

This patch fixes this issue by setting the NFC clock to the highest frequency
complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Daniel Gachet <Daniel.Gachet@hefr.ch>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S
index 823df10701e9c093c67ec04ea0cb134d8fbd1772..eb3f187806eac216b12030f6f53671735bb35ba5 100644 (file)
--- a/board/karo/tx25/lowlevel_init.S
+++ b/board/karo/tx25/lowlevel_init.S
@@ -66,6 +66,14 @@
        write32 0x53f80064, 0x45600000
        write32 0x53f80008, 0x20034000
 
+       /*
+        * PCDR2: NFC = 33.25 MHz
+        * This is required for the NAND Flash of this board, which is a Samsung
+        * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
+        * the NFC driver in symmetric (i.e. one-cycle) mode.
+        */
+       write32 0x53f80020, 0x01010103
+
        /*
         * enable all implemented clocks in all three
         * clock control registers