clk: Check that composite clock's div has set_rate()

It's possible for composite clocks to have a divider that does not
implement set_rate() operation. For example, sandbox_clk_composite()
registers composite clock with a divider that only has get_rate().
Currently clk_composite_set_rate() only checks thate rate_ops are
present, so for sandbox it will cause NULL dereference during
clk_set_rate().

This patch adds rate_ops->set_rate check tp clk_composite_set_rate().

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231205232334.2931-2-ivprusov@salutedevices.com

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 6eb2b8133a3b958d017e5a5ddf5e3ea2807b389f..d2e5a1ae401dcd038d484397294395eb0f0d2209 100644 (file)
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -66,7 +66,7 @@ static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
        const struct clk_ops *rate_ops = composite->rate_ops;
        struct clk *clk_rate = composite->rate;
 
-       if (rate && rate_ops)
+       if (rate && rate_ops && rate_ops->set_rate)
                return rate_ops->set_rate(clk_rate, rate);
        else
                return clk_get_rate(clk);