85xx: Remove old style of LAW init

All boards are now using the new fsl_law code so we can drop the old version.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index bb5dc1f44a572c0fdaaa92e6cf3ed15dd9bc7985..90c3d444a8753a164fb90e6f47d7dc7d63974617 100644 (file)
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -1023,9 +1023,6 @@ spd_sdram(void)
 static unsigned int
 setup_laws_and_tlbs(unsigned int memsize)
 {
-#ifndef CONFIG_FSL_LAW
-       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
-#endif
        unsigned int tlb_size;
        unsigned int law_size;
        unsigned int ram_tlb_index;
@@ -1104,13 +1101,6 @@ setup_laws_and_tlbs(unsigned int memsize)
 
 #ifdef CONFIG_FSL_LAW
        set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
-#else
-       ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-       ecm->lawar1 = (LAWAR_EN
-                      | LAWAR_TRGT_IF_DDR
-                      | (LAWAR_SIZE & law_size));
-       debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
-       debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
 #endif
 
        /*

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 346369cc31c14a3de5ce456a74052350996804f4..204472261152053049206a80dc515de6aac6ff1d 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -201,24 +201,6 @@ _start_e500:
        lis     r7,CFG_CCSRBAR@h
        ori     r7,r7,CFG_CCSRBAR@l
 
-#ifndef CONFIG_FSL_LAW
-       bl      law_entry
-       mr      r6,r0
-       lwzu    r5,0(r6)        /* how many windows we actually use */
-       mtctr   r5
-
-       li      r2,0x0c28       /* the first pair is reserved for */
-       li      r1,0x0c30       /* boot-over-rio-or-pci */
-
-0:     lwzu    r4,4(r6)
-       lwzu    r3,4(r6)
-       stwx    r4,r7,r2
-       stwx    r3,r7,r1
-       addi    r2,r2,0x0020
-       addi    r1,r1,0x0020
-       bdnz    0b
-#endif
-
        /* Clear and set up some registers. */
        li      r0,0
        mtmsr   r0