4:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
switch_el x7, _dead_loop, 0f, _dead_loop
-0: armv8_switch_to_el1_m x4, x6, x7
+0: armv8_switch_to_el1_m x4, x6, x7, x9
#else
switch_el x7, 0f, _dead_loop, _dead_loop
0: armv8_switch_to_el2_m x4, x6, x7
* now, jump to the address saved in x4.
*/
br x4
-1: armv8_switch_to_el1_m x4, x5, x6
+1: armv8_switch_to_el1_m x4, x5, x6, x7
ENDPROC(armv8_switch_to_el1)
.popsection
* For loading 64-bit OS, x0 is physical address to the FDT blob.
* They will be passed to the guest.
*/
-.macro armv8_switch_to_el1_m, ep, flag, tmp
+.macro armv8_switch_to_el1_m, ep, flag, tmp, tmp2
/* Initialize Generic Timers */
mrs \tmp, cnthctl_el2
/* Enable EL1 access to timers */
b.eq 1f
/* Initialize HCR_EL2 */
- ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
+ /* Only disable PAuth traps if PAuth is supported */
+ mrs \tmp, id_aa64isar1_el1
+ ldr \tmp2, =(ID_AA64ISAR1_EL1_GPI | ID_AA64ISAR1_EL1_GPA | \
+ ID_AA64ISAR1_EL1_API | ID_AA64ISAR1_EL1_APA)
+ tst \tmp, \tmp2
+ mov \tmp2, #(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
+ orr \tmp, \tmp2, #(HCR_EL2_APK | HCR_EL2_API)
+ csel \tmp, \tmp2, \tmp, eq
msr hcr_el2, \tmp
/* Return to the EL1_SP1 mode from EL2 */
/*
* HCR_EL2 bits definitions
*/
+#define HCR_EL2_API (1 << 41) /* Trap pointer authentication
+ instructions */
+#define HCR_EL2_APK (1 << 40) /* Trap pointer authentication
+ key access */
#define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
#define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
+/*
+ * ID_AA64ISAR1_EL1 bits definitions
+ */
+#define ID_AA64ISAR1_EL1_GPI (0xF << 28) /* Implementation-defined generic
+ code auth algorithm */
+#define ID_AA64ISAR1_EL1_GPA (0xF << 24) /* QARMA generic code auth
+ algorithm */
+#define ID_AA64ISAR1_EL1_API (0xF << 8) /* Implementation-defined address
+ auth algorithm */
+#define ID_AA64ISAR1_EL1_APA (0xF << 4) /* QARMA address auth algorithm */
+
/*
* ID_AA64PFR0_EL1 bits definitions
*/