M52277EVB mcf5227x
M5235EVB mcf52x2
M5253DEMO mcf52x2
+ M53017EVB mcf532x
M5329EVB mcf532x
M5373EVB mcf532x
M54455EVB mcf5445x
M5272C3 \
M5275EVB \
M5282EVB \
+ M53017EVB \
M5329AFEE \
M5373EVB \
M54451EVB \
M5282EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb freescale
+M53017EVB_config : unconfig
+ @$(MKCONFIG) $(@:_config=) m68k mcf532x m53017evb freescale
+
M5329AFEE_config \
M5329BFEE_config : unconfig
@case "$@" in \
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M53017EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+ sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+#endif
+ sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+ sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+ udelay(500);
+
+ /* Issue PALL */
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ /* Perform two refresh cycles */
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ asm("nop");
+
+ /* Issue LEMR */
+ sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ asm("nop");
+ sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ asm("nop");
+
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ asm("nop");
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf532x/start.o (.text)
+ cpu/mcf532x/libmcf532x.a (.text)
+ lib_m68k/libm68k.a (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
msk = (ccm->cir >> 6);
ver = (ccm->cir & 0x003f);
switch (msk) {
+#ifdef CONFIG_MCF5301x
+ case 0x78:
+ id = 53010;
+ break;
+ case 0x77:
+ id = 53012;
+ break;
+ case 0x76:
+ id = 53015;
+ break;
+ case 0x74:
+ id = 53011;
+ break;
+ case 0x73:
+ id = 53013;
+ break;
+#endif
+#ifdef CONFIG_MCF532x
case 0x54:
id = 5329;
break;
case 0x6B:
id = 5372;
break;
+#endif
}
if (id) {
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#include <asm/fec.h>
#endif
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
+#ifdef CONFIG_MCF5301x
+void cpu_init_f(void)
+{
+ volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ /* watchdog is enabled by default - disable the watchdog */
+#ifndef CONFIG_WATCHDOG
+ /*wdog->cr = 0; */
+#endif
+
+ scm1->mpr = 0x77777777;
+ scm1->pacra = 0;
+ scm1->pacrb = 0;
+ scm1->pacrc = 0;
+ scm1->pacrd = 0;
+ scm1->pacre = 0;
+ scm1->pacrf = 0;
+ scm1->pacrg = 0;
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS0_CS0;
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS1_CS1;
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS4;
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS5;
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+#endif
+
+#ifdef CONFIG_FSL_I2C
+ gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
+#endif
+
+ icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+#ifdef CONFIG_MCFFEC
+ volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+#endif
+#ifdef CONFIG_MCFRTC
+ volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
+ volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
+
+ rtcex->gocu = CONFIG_SYS_RTC_CNT;
+ rtcex->gocl = CONFIG_SYS_RTC_SETUP;
+
+#endif
+#ifdef CONFIG_MCFFEC
+ if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
+ ccm->misccr |= CCM_MISCCR_FECM;
+ else
+ ccm->misccr &= ~CCM_MISCCR_FECM;
+#endif
+
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ break;
+ case 1:
+#ifdef CONFIG_SYS_UART1_ALT1_GPIO
+ gpio->par_simp1h &=
+ ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
+ gpio->par_simp1h |=
+ (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
+#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
+ gpio->par_ssih &=
+ ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
+ gpio->par_ssih |=
+ (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
+#endif
+ break;
+ case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+ gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
+#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
+ gpio->par_dspih &=
+ ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
+ gpio->par_dspih |=
+ (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+ gpio->par_feci2c &=
+ ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+ break;
+ }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+ if (setclear) {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_fec |=
+ GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
+ } else {
+ gpio->par_fec |=
+ GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
+ }
+ } else {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_fec &=
+ ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
+ } else {
+ gpio->par_fec &=
+ ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
+ }
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_MCF5301x */
+
+#ifdef CONFIG_MCF532x
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
/* Port configuration */
gpio->par_cs = 0;
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
gpio->par_cs |= GPIO_PAR_CS1;
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS2;
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS3;
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
-#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS4;
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
-#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS5;
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
return 0;
}
#endif
+#endif /* CONFIG_MCF532x */
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#define MAX_FVCO 500000 /* KHz */
#define MAX_FSYS 80000 /* KHz */
#define MIN_FSYS 58333 /* KHz */
+
+#ifdef CONFIG_MCF5301x
+#define FREF 20000 /* KHz */
+#define MAX_MFD 63 /* Multiplier */
+#define MIN_MFD 0 /* Multiplier */
+#define USBDIV 8
+
+/* Low Power Divider specifications */
+#define MIN_LPD (0) /* Divider (not encoded) */
+#define MAX_LPD (15) /* Divider (not encoded) */
+#define DEFAULT_LPD (0) /* Divider (not encoded) */
+#endif
+
+#ifdef CONFIG_MCF532x
#define FREF 16000 /* KHz */
#define MAX_MFD 135 /* Multiplier */
#define MIN_MFD 88 /* Multiplier */
-#define BUSDIV 6 /* Divider */
-/*
- * Low Power Divider specifications
- */
+
+/* Low Power Divider specifications */
#define MIN_LPD (1 << 0) /* Divider (not encoded) */
#define MAX_LPD (1 << 15) /* Divider (not encoded) */
#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
+#endif
-/*
- * Get the value of the current system clock
- *
- * Parameters:
- * none
- *
- * Return Value:
- * The current output system frequency
- */
+#define BUSDIV 6 /* Divider */
+
+/* Get the value of the current system clock */
int get_sys_clock(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
/* Test to see if device is in LIMP mode */
if (ccm->misccr & CCM_MISCCR_LIMP) {
divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
+#ifdef CONFIG_MCF5301x
+ return (FREF / (3 * (1 << divider)));
+#endif
+#ifdef CONFIG_MCF532x
return (FREF / (2 << divider));
+#endif
} else {
+#ifdef CONFIG_MCF5301x
+ u32 pfdr = (pll->pcr & 0x3F) + 1;
+ u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
+ u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
+
+ return (((FREF * pfdr) / refdiv) / busdiv);
+#endif
+#ifdef CONFIG_MCF532x
return ((FREF * pll->pfdr) / (BUSDIV * 4));
+#endif
}
}
div = MAX_LPD;
/* Save of the current value of the SSIDIV so we don't overwrite the value */
- temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
+ temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
/* Apply the divider to the system clock */
ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
return (FREF / (3 * (1 << div)));
}
-/*
- * Exit low power LIMP mode
- *
- * Parameters:
- * div Desired system frequency divider
- *
- * Return Value:
- * The resulting output system frequency
- */
+/* Exit low power LIMP mode */
int clock_exit_limp(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
*/
int clock_pll(int fsys, int flags)
{
+#ifdef CONFIG_MCF532x
volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
+#endif
+ volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
int fref, temp, fout, mfd;
u32 i;
if (fsys == 0) {
/* Return current PLL output */
+#ifdef CONFIG_MCF5301x
+ u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
+ mfd = (pll->pcr & 0x3F) + 1;
+
+ return (fref * mfd) / busdiv;
+#endif
+#ifdef CONFIG_MCF532x
mfd = pll->pfdr;
return (fref * mfd / (BUSDIV * 4));
+#endif
}
/* Check bounds of requested system clock */
if (fsys < MIN_FSYS)
fsys = MIN_FSYS;
- /* Multiplying by 100 when calculating the temp value,
- and then dividing by 100 to calculate the mfd allows
- for exact values without needing to include floating
- point libraries. */
+ /*
+ * Multiplying by 100 when calculating the temp value,
+ * and then dividing by 100 to calculate the mfd allows
+ * for exact values without needing to include floating
+ * point libraries.
+ */
temp = (100 * fsys) / fref;
+#ifdef CONFIG_MCF5301x
+ mfd = (BUSDIV * temp) / 100;
+
+ /* Determine the output frequency for selected values */
+ fout = ((fref * mfd) / BUSDIV);
+#endif
+#ifdef CONFIG_MCF532x
mfd = (4 * BUSDIV * temp) / 100;
/* Determine the output frequency for selected values */
fout = ((fref * mfd) / (BUSDIV * 4));
+#endif
/*
* Check to see if the SDRAM has already been initialized.
* If it has then the SDRAM needs to be put into self refresh
* mode before reprogramming the PLL.
*/
+ if (sdram->ctrl & SDRAMC_SDCR_REF)
+ sdram->ctrl &= ~SDRAMC_SDCR_CKE;
/*
* Initialize the PLL to generate the new system clock frequency.
/* Enter LIMP mode */
clock_limp(DEFAULT_LPD);
+#ifdef CONFIG_MCF5301x
+ pll->pdr =
+ PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
+ PLL_PDR_OUTDIV2(BUSDIV - 1) |
+ PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
+ PLL_PDR_OUTDIV4(USBDIV - 1);
+
+ pll->pcr &= PLL_PCR_FBDIV_MASK;
+ pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
+#endif
+#ifdef CONFIG_MCF532x
/* Reprogram PLL for desired fsys */
pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
pll->pfdr = mfd;
+#endif
/* Exit LIMP mode */
clock_exit_limp();
+ /* Return the SDRAM to normal operation if it is in use. */
+ if (sdram->ctrl & SDRAMC_SDCR_REF)
+ sdram->ctrl |= SDRAMC_SDCR_CKE;
+
+#ifdef CONFIG_MCF532x
/*
- * Return the SDRAM to normal operation if it is in use.
+ * software workaround for SDRAM opeartion after exiting LIMP
+ * mode errata
*/
-
- /* software workaround for SDRAM opeartion after exiting LIMP mode errata */
*sdram_workaround = CONFIG_SYS_SDRAM_BASE;
+#endif
/* wait for DQS logic to relock */
for (i = 0; i < 0x200; i++) ;
return fout;
}
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
+ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
movec %d0, %ACR0
movec %d0, %ACR1
+#ifdef CONFIG_MCF5301x
+ move.l #(0xFC0a0010), %a0
+ move.w (%a0), %d0
+ and.l %d0, 0xEFFF
+
+ move.w %d0, (%a0)
+#endif
+
/* initialize general use internal ram */
move.l #0, %d0
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
--- /dev/null
+Freescale MCF53017EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 10/22/08
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m53017evb/m53017evb.c Dram setup
+- board/freescale/m53017evb/mii.c Mii access
+- board/freescale/m53017evb/Makefile Makefile
+- board/freescale/m53017evb/config.mk config make
+- board/freescale/m53017evb/u-boot.lds Linker description
+
+- cpu/mcf532x/cpu.c cpu specific code
+- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- cpu/mcf532x/interrupts.c cpu specific interrupt support
+- cpu/mcf532x/speed.c system, flexbus, and cpu clock
+- cpu/mcf532x/Makefile Makefile
+- cpu/mcf532x/config.mk config make
+- cpu/mcf532x/start.S start up assembly code
+
+- doc/README.m53017evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/net/mcfmii.c ColdFire common Mii driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+- drivers/rtc/mcfrtc.c Realtime clock Driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5301x.h mcf5301x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m532x.h mcf5301x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M53017EVB.h Board specific configuration file
+
+- lib_m68k/board.c board init function
+- lib_m68k/cache.c
+- lib_m68k/interrupts Coldfire common interrupt functions
+- lib_m68k/m68k_linux.c
+- lib_m68k/time.c Timer functions (Dma timer and PIT)
+- lib_m68k/traps.c Exception init code
+
+1 MCF5301x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M53017EVB Development Board
+CONFIG_MCF5301x -- define for all MCF5301x CPUs
+CONFIG_M53015 -- define for MCF53015 CPUs
+CONFIG_M53017EVB -- define for M53017EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFFEC -- define to use common CF FEC driver
+CONFIG_NET_MULTI -- define to use multi FEC in u-boot
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN --
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ IP: 0xFC000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Flash0: 0x00000000-0x00FFFFFF (16MB)
+ DDR: 0x40000000-0x4FFFFFFF (256MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot
+ make distclean
+ make M53017EVB_config
+ make
+
+4. SCREEN DUMP
+==============
+4.1 M53017EVB Development board
+ (NOTE: May not show exactly the same)
+
+U-Boot 2008.10 (Oct 22 2007 - 11:07:57)
+
+CPU: Freescale MCF53015 (Mask:76 Version:0)
+ CPU CLK 240 Mhz BUS CLK 80 Mhz
+Board: Freescale M53017EVB
+I2C: ready
+DRAM: 64 MB
+FLASH: 16 MB
+In: serial
+Out: serial
+Err: serial
+NAND: 16 MiB
+Net: FEC0, FEC1
+-> print
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+hostname=M53017EVB
+netdev=eth0
+loadaddr=40010000
+u-boot=u-boot.bin
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=65024k
+
+Environment size: 437/4092 bytes
+->
#endif
#endif /* CONFIG_M5282 */
+#if defined(CONFIG_MCF5301x)
+#include <asm/immap_5301x.h>
+#include <asm/m5301x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+
+#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI (6)
+#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE (6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS (128)
+#endif /* CONFIG_M5301x */
+
#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
#include <asm/immap_5329.h>
#include <asm/m5329.h>
--- /dev/null
+/*
+ * MCF5301x Internal Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5301X__
+#define __IMMAP_5301X__
+
+#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
+#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000)
+#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
+#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000)
+#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
+#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
+#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
+#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
+#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000)
+#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000)
+#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000)
+#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000)
+#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000)
+#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
+#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000)
+#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000)
+#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000)
+#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000)
+#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
+#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
+#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
+#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000)
+#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000)
+#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000)
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/rtc.h>
+
+/* System Controller Module */
+typedef struct scm1 {
+ u32 mpr; /* 0x00 Master Privilege */
+ u32 rsvd1[7];
+ u32 pacra; /* 0x20 Peripheral Access Ctrl A */
+ u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
+ u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
+ u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
+ u32 rsvd2[4];
+ u32 pacre; /* 0x40 Peripheral Access Ctrl E */
+ u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
+ u32 pacrg; /* 0x48 Peripheral Access Ctrl G */
+} scm1_t;
+
+typedef struct scm2 {
+ u8 rsvd1[19]; /* 0x00 - 0x12 */
+ u8 wcr; /* 0x13 */
+ u16 rsvd2; /* 0x14 - 0x15 */
+ u16 cwcr; /* 0x16 */
+ u8 rsvd3[3]; /* 0x18 - 0x1A */
+ u8 cwsr; /* 0x1B */
+ u8 rsvd4[3]; /* 0x1C - 0x1E */
+ u8 scmisr; /* 0x1F */
+ u32 rsvd5; /* 0x20 - 0x23 */
+ u8 bcr; /* 0x24 */
+ u8 rsvd6[74]; /* 0x25 - 0x6F */
+ u32 cfadr; /* 0x70 */
+ u8 rsvd7; /* 0x74 */
+ u8 cfier; /* 0x75 */
+ u8 cfloc; /* 0x76 */
+ u8 cfatr; /* 0x77 */
+ u32 rsvd8; /* 0x78 - 0x7B */
+ u32 cfdtr; /* 0x7C */
+} scm2_t;
+
+/* PWM module */
+typedef struct pwm_ctrl {
+ u8 en; /* 0x00 PWM Enable */
+ u8 pol; /* 0x01 Polarity */
+ u8 clk; /* 0x02 Clock Select */
+ u8 prclk; /* 0x03 Prescale Clock Select */
+ u8 cae; /* 0x04 Center Align Enable */
+ u8 ctl; /* 0x05 Ctrl */
+ u8 res1[2]; /* 0x06 - 0x07 */
+ u8 scla; /* 0x08 Scale A */
+ u8 sclb; /* 0x09 Scale B */
+ u8 res2[2]; /* 0x0A - 0x0B */
+ u8 cnt0; /* 0x0C Channel 0 Counter */
+ u8 cnt1; /* 0x0D Channel 1 Counter */
+ u8 cnt2; /* 0x0E Channel 2 Counter */
+ u8 cnt3; /* 0x0F Channel 3 Counter */
+ u8 cnt4; /* 0x10 Channel 4 Counter */
+ u8 cnt5; /* 0x11 Channel 5 Counter */
+ u8 cnt6; /* 0x12 Channel 6 Counter */
+ u8 cnt7; /* 0x13 Channel 7 Counter */
+ u8 per0; /* 0x14 Channel 0 Period */
+ u8 per1; /* 0x15 Channel 1 Period */
+ u8 per2; /* 0x16 Channel 2 Period */
+ u8 per3; /* 0x17 Channel 3 Period */
+ u8 per4; /* 0x18 Channel 4 Period */
+ u8 per5; /* 0x19 Channel 5 Period */
+ u8 per6; /* 0x1A Channel 6 Period */
+ u8 per7; /* 0x1B Channel 7 Period */
+ u8 dty0; /* 0x1C Channel 0 Duty */
+ u8 dty1; /* 0x1D Channel 1 Duty */
+ u8 dty2; /* 0x1E Channel 2 Duty */
+ u8 dty3; /* 0x1F Channel 3 Duty */
+ u8 dty4; /* 0x20 Channel 4 Duty */
+ u8 dty5; /* 0x21 Channel 5 Duty */
+ u8 dty6; /* 0x22 Channel 6 Duty */
+ u8 dty7; /* 0x23 Channel 7 Duty */
+ u8 sdn; /* 0x24 Shutdown */
+ u8 res3[3]; /* 0x25 - 0x27 */
+} pwm_t;
+
+/* Chip configuration module */
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+typedef struct ccm_ctrl {
+ u16 ccr; /* 0x00 Chip Cfg */
+ u16 res1; /* 0x02 */
+ u16 rcon; /* 0x04 Reset Cfg */
+ u16 cir; /* 0x06 Chip ID */
+ u32 res2; /* 0x08 */
+ u16 misccr; /* 0x0A Misc Ctrl */
+ u16 cdr; /* 0x0C Clock divider */
+ u16 uhcsr; /* 0x10 USB Host status */
+ u16 uocsr; /* 0x12 USB On-the-Go Status */
+ u16 res3; /* 0x14 */
+ u16 codeccr; /* 0x16 Codec Control */
+ u16 misccr2; /* 0x18 Misc2 Ctrl */
+} ccm_t;
+
+/* GPIO port */
+typedef struct gpio_ctrl {
+ /* Port Output Data */
+ u8 podr_fbctl; /* 0x00 */
+ u8 podr_be; /* 0x01 */
+ u8 podr_cs; /* 0x02 */
+ u8 podr_dspi; /* 0x03 */
+ u8 res01; /* 0x04 */
+ u8 podr_fec0; /* 0x05 */
+ u8 podr_feci2c; /* 0x06 */
+ u8 res02[2]; /* 0x07 - 0x08 */
+ u8 podr_simp1; /* 0x09 */
+ u8 podr_simp0; /* 0x0A */
+ u8 podr_timer; /* 0x0B */
+ u8 podr_uart; /* 0x0C */
+ u8 podr_debug; /* 0x0D */
+ u8 res03; /* 0x0E */
+ u8 podr_sdhc; /* 0x0F */
+ u8 podr_ssi; /* 0x10 */
+ u8 res04[3]; /* 0x11 - 0x13 */
+
+ /* Port Data Direction */
+ u8 pddr_fbctl; /* 0x14 */
+ u8 pddr_be; /* 0x15 */
+ u8 pddr_cs; /* 0x16 */
+ u8 pddr_dspi; /* 0x17 */
+ u8 res05; /* 0x18 */
+ u8 pddr_fec0; /* 0x19 */
+ u8 pddr_feci2c; /* 0x1A */
+ u8 res06[2]; /* 0x1B - 0x1C */
+ u8 pddr_simp1; /* 0x1D */
+ u8 pddr_simp0; /* 0x1E */
+ u8 pddr_timer; /* 0x1F */
+ u8 pddr_uart; /* 0x20 */
+ u8 pddr_debug; /* 0x21 */
+ u8 res07; /* 0x22 */
+ u8 pddr_sdhc; /* 0x23 */
+ u8 pddr_ssi; /* 0x24 */
+ u8 res08[3]; /* 0x25 - 0x27 */
+
+ /* Port Data Direction */
+ u8 ppdr_fbctl; /* 0x28 */
+ u8 ppdr_be; /* 0x29 */
+ u8 ppdr_cs; /* 0x2A */
+ u8 ppdr_dspi; /* 0x2B */
+ u8 res09; /* 0x2C */
+ u8 ppdr_fec0; /* 0x2D */
+ u8 ppdr_feci2c; /* 0x2E */
+ u8 res10[2]; /* 0x2F - 0x30 */
+ u8 ppdr_simp1; /* 0x31 */
+ u8 ppdr_simp0; /* 0x32 */
+ u8 ppdr_timer; /* 0x33 */
+ u8 ppdr_uart; /* 0x34 */
+ u8 ppdr_debug; /* 0x35 */
+ u8 res11; /* 0x36 */
+ u8 ppdr_sdhc; /* 0x37 */
+ u8 ppdr_ssi; /* 0x38 */
+ u8 res12[3]; /* 0x39 - 0x3B */
+
+ /* Port Clear Output Data */
+ u8 pclrr_fbctl; /* 0x3C */
+ u8 pclrr_be; /* 0x3D */
+ u8 pclrr_cs; /* 0x3E */
+ u8 pclrr_dspi; /* 0x3F */
+ u8 res13; /* 0x40 */
+ u8 pclrr_fec0; /* 0x41 */
+ u8 pclrr_feci2c; /* 0x42 */
+ u8 res14[2]; /* 0x43 - 0x44 */
+ u8 pclrr_simp1; /* 0x45 */
+ u8 pclrr_simp0; /* 0x46 */
+ u8 pclrr_timer; /* 0x47 */
+ u8 pclrr_uart; /* 0x48 */
+ u8 pclrr_debug; /* 0x49 */
+ u8 res15; /* 0x4A */
+ u8 pclrr_sdhc; /* 0x4B */
+ u8 pclrr_ssi; /* 0x4C */
+ u8 res16[3]; /* 0x4D - 0x4F */
+
+ /* Pin Assignment */
+ u8 par_fbctl; /* 0x50 */
+ u8 par_be; /* 0x51 */
+ u8 par_cs; /* 0x52 */
+ u8 res17; /* 0x53 */
+ u8 par_dspih; /* 0x54 */
+ u8 par_dspil; /* 0x55 */
+ u8 par_fec; /* 0x56 */
+ u8 par_feci2c; /* 0x57 */
+ u8 par_irq0h; /* 0x58 */
+ u8 par_irq0l; /* 0x59 */
+ u8 par_irq1h; /* 0x5A */
+ u8 par_irq1l; /* 0x5B */
+ u8 par_simp1h; /* 0x5C */
+ u8 par_simp1l; /* 0x5D */
+ u8 par_simp0; /* 0x5E */
+ u8 par_timer; /* 0x5F */
+ u8 par_uart; /* 0x60 */
+ u8 res18; /* 0x61 */
+ u8 par_debug; /* 0x62 */
+ u8 par_sdhc; /* 0x63 */
+ u8 par_ssih; /* 0x64 */
+ u8 par_ssil; /* 0x65 */
+ u8 res19[2]; /* 0x66 - 0x67 */
+
+ /* Mode Select Control */
+ /* Drive Strength Control */
+ u8 mscr_mscr1; /* 0x68 */
+ u8 mscr_mscr2; /* 0x69 */
+ u8 mscr_mscr3; /* 0x6A */
+ u8 mscr_mscr45; /* 0x6B */
+ u8 srcr_dspi; /* 0x6C */
+ u8 dscr_fec; /* 0x6D */
+ u8 srcr_i2c; /* 0x6E */
+ u8 srcr_irq; /* 0x6F */
+
+ u8 srcr_sim; /* 0x70 */
+ u8 srcr_timer; /* 0x71 */
+ u8 srcr_uart; /* 0x72 */
+ u8 res20; /* 0x73 */
+ u8 srcr_sdhc; /* 0x74 */
+ u8 srcr_ssi; /* 0x75 */
+ u8 res21[2]; /* 0x76 - 0x77 */
+ u8 pcr_pcrh; /* 0x78 */
+ u8 pcr_pcrl; /* 0x79 */
+} gpio_t;
+
+/* SDRAM controller */
+typedef struct sdram_ctrl {
+ u32 mode; /* 0x00 Mode/Extended Mode */
+ u32 ctrl; /* 0x04 Ctrl */
+ u32 cfg1; /* 0x08 Cfg 1 */
+ u32 cfg2; /* 0x0C Cfg 2 */
+ u32 res1[64]; /* 0x10 - 0x10F */
+ u32 cs0; /* 0x110 Chip Select 0 Cfg */
+ u32 cs1; /* 0x114 Chip Select 1 Cfg */
+} sdram_t;
+
+/* Clock Module */
+typedef struct pll_ctrl {
+ u32 pcr; /* 0x00 Ctrl */
+ u32 pdr; /* 0x04 Divider */
+ u32 psr; /* 0x08 Status */
+} pll_t;
+
+typedef struct rtcex {
+ u32 rsvd1[3];
+ u32 gocu;
+ u32 gocl;
+} rtcex_t;
+#endif /* __IMMAP_5301X__ */
--- /dev/null
+/*
+ * m5301x.h -- Definitions for Freescale Coldfire 5301x
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef m5301x_h
+#define m5301x_h
+
+/* *** System Control Module (SCM) *** */
+#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28)
+#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24)
+#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20)
+#define SCM_MPR_MPROT4(x) (((x) & 0x0F) << 12)
+#define SCM_MPR_MPROT5(x) (((x) & 0x0F) << 8)
+#define SCM_MPR_MPROT6(x) (((x) & 0x0F) << 4)
+#define MPROT_MTR 4
+#define MPROT_MTW 2
+#define MPROT_MPL 1
+
+#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28)
+#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24)
+#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20)
+#define SCM_PACRA_PACR5(x) (((x) & 0x0F) << 8)
+
+#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12)
+#define SCM_PACRB_PACR13(x) (((x) & 0x0F) << 8)
+
+#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28)
+#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24)
+#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20)
+#define SCM_PACRC_PACR19(x) (((x) & 0x0F) << 16)
+#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8)
+#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4)
+#define SCM_PACRC_PACR23(x) ((x) & 0x0F)
+
+#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28)
+#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24)
+#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20)
+#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12)
+#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8)
+#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4)
+#define SCM_PACRD_PACR31(x) ((x) & 0x0F)
+
+#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28)
+#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24)
+#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20)
+#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16)
+#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12)
+#define SCM_PACRE_PACR37(x) (((x) & 0x0F) << 8)
+#define SCM_PACRE_PACR39(x) ((x) & 0x0F)
+
+#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28)
+#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24)
+#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20)
+#define SCM_PACRF_PACR43(x) (((x) & 0x0F) << 16)
+#define SCM_PACRF_PACR44(x) (((x) & 0x0F) << 12)
+#define SCM_PACRF_PACR45(x) (((x) & 0x0F) << 8)
+#define SCM_PACRF_PACR46(x) (((x) & 0x0F) << 4)
+#define SCM_PACRF_PACR47(x) ((x) & 0x0F)
+
+#define SCM_PACRG_PACR48(x) (((x) & 0x0F) << 28)
+#define SCM_PACRG_PACR49(x) (((x) & 0x0F) << 24)
+#define SCM_PACRG_PACR50(x) (((x) & 0x0F) << 20)
+#define SCM_PACRG_PACR51(x) (((x) & 0x0F) << 16)
+
+#define PACR_SP 4
+#define PACR_WP 2
+#define PACR_TP 1
+
+#define SCM_CWCR_RO (0x8000)
+#define SCM_CWCR_CWR_WH (0x0100)
+#define SCM_CWCR_CWE (0x0080)
+#define SCM_CWCR_CWRI_WINDOW (0x0060)
+#define SCM_CWCR_CWRI_RESET (0x0040)
+#define SCM_CWCR_CWRI_INT_RESET (0x0020)
+#define SCM_CWCR_CWRI_INT (0x0000)
+#define SCM_CWCR_CWT(x) (((x) & 0x001F))
+
+#define SCM_ISR_CFEI (0x02)
+#define SCM_ISR_CWIC (0x01)
+
+#define BCR_GBR (0x00000200)
+#define BCR_GBW (0x00000100)
+#define BCR_S7 (0x00000080)
+#define BCR_S6 (0x00000040)
+#define BCR_S4 (0x00000010)
+#define BCR_S1 (0x00000002)
+
+#define SCM_CFIER_ECFEI (0x01)
+
+#define SCM_CFLOC_LOC (0x80)
+
+#define SCM_CFATR_WRITE (0x80)
+#define SCM_CFATR_SZ32 (0x20)
+#define SCM_CFATR_SZ16 (0x10)
+#define SCM_CFATR_SZ08 (0x00)
+#define SCM_CFATR_CACHE (0x08)
+#define SCM_CFATR_MODE (0x02)
+#define SCM_CFATR_TYPE (0x01)
+
+/* *** Interrupt Controller (INTC) *** */
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_EDMA_00 (8)
+#define INT0_LO_EDMA_01 (9)
+#define INT0_LO_EDMA_02 (10)
+#define INT0_LO_EDMA_03 (11)
+#define INT0_LO_EDMA_04 (12)
+#define INT0_LO_EDMA_05 (13)
+#define INT0_LO_EDMA_06 (14)
+#define INT0_LO_EDMA_07 (15)
+#define INT0_LO_EDMA_08 (16)
+#define INT0_LO_EDMA_09 (17)
+#define INT0_LO_EDMA_10 (18)
+#define INT0_LO_EDMA_11 (19)
+#define INT0_LO_EDMA_12 (20)
+#define INT0_LO_EDMA_13 (21)
+#define INT0_LO_EDMA_14 (22)
+#define INT0_LO_EDMA_15 (23)
+#define INT0_LO_EDMA_ERR (24)
+#define INT0_LO_SCM_CWIC (25)
+#define INT0_LO_UART0 (26)
+#define INT0_LO_UART1 (27)
+#define INT0_LO_UART2 (28)
+#define INT0_LO_RSVD1 (29)
+#define INT0_LO_I2C (30)
+#define INT0_LO_DSPI (31)
+#define INT0_HI_DTMR0 (32)
+#define INT0_HI_DTMR1 (33)
+#define INT0_HI_DTMR2 (34)
+#define INT0_HI_DTMR3 (35)
+#define INT0_HI_FEC0_TXF (36)
+#define INT0_HI_FEC0_TXB (37)
+#define INT0_HI_FEC0_UN (38)
+#define INT0_HI_FEC0_RL (39)
+#define INT0_HI_FEC0_RXF (40)
+#define INT0_HI_FEC0_RXB (41)
+#define INT0_HI_FEC0_MII (42)
+#define INT0_HI_FEC0_LC (43)
+#define INT0_HI_FEC0_HBERR (44)
+#define INT0_HI_FEC0_GRA (45)
+#define INT0_HI_FEC0_EBERR (46)
+#define INT0_HI_FEC0_BABT (47)
+#define INT0_HI_FEC0_BABR (48)
+#define INT0_HI_FEC1_TXF (49)
+#define INT0_HI_FEC1_TXB (50)
+#define INT0_HI_FEC1_UN (51)
+#define INT0_HI_FEC1_RL (52)
+#define INT0_HI_FEC1_RXF (53)
+#define INT0_HI_FEC1_RXB (54)
+#define INT0_HI_FEC1_MII (55)
+#define INT0_HI_FEC1_LC (56)
+#define INT0_HI_FEC1_HBERR (57)
+#define INT0_HI_FEC1_GRA (58)
+#define INT0_HI_FEC1_EBERR (59)
+#define INT0_HI_FEC1_BABT (60)
+#define INT0_HI_FEC1_BABR (61)
+#define INT0_HI_SCM_CFEI (62)
+
+/* 0 - 24 reserved */
+#define INT1_LO_EPORT1_FLAG0 (25)
+#define INT1_LO_EPORT1_FLAG1 (26)
+#define INT1_LO_EPORT1_FLAG2 (27)
+#define INT1_LO_EPORT1_FLAG3 (28)
+#define INT1_LO_EPORT1_FLAG4 (29)
+#define INT1_LO_EPORT1_FLAG5 (30)
+#define INT1_LO_EPORT1_FLAG6 (31)
+#define INT1_LO_EPORT1_FLAG7 (32)
+#define INT1_HI_DSPI_EOQF (33)
+#define INT1_HI_DSPI_TFFF (34)
+#define INT1_HI_DSPI_TCF (35)
+#define INT1_HI_DSPI_TFUF (36)
+#define INT1_HI_DSPI_RFDF (37)
+#define INT1_HI_DSPI_RFOF (38)
+#define INT1_HI_DSPI_RFOF_TFUF (39)
+#define INT1_HI_RNG_EI (40)
+#define INT1_HI_PLL_LOCF (41)
+#define INT1_HI_PLL_LOLF (42)
+#define INT1_HI_PIT0 (43)
+#define INT1_HI_PIT1 (44)
+#define INT1_HI_PIT2 (45)
+#define INT1_HI_PIT3 (46)
+#define INT1_HI_USBOTG_STS (47)
+#define INT1_HI_USBHOST_STS (48)
+#define INT1_HI_SSI (49)
+/* 50 - 51 reserved */
+#define INT1_HI_RTC (52)
+#define INT1_HI_CCM_USBSTAT (53)
+#define INT1_HI_CODEC_OR (54)
+#define INT1_HI_CODEC_RF_TE (55)
+#define INT1_HI_CODEC_ROE (56)
+#define INT1_HI_CODEC_TUE (57)
+/* 58 reserved */
+#define INT1_HI_SIM1_DATA (59)
+#define INT1_HI_SIM1_GENERAL (60)
+/* 61 - 62 reserved */
+#define INT1_HI_SDHC (63)
+
+/* *** Reset Controller Module (RCM) *** */
+#define RCM_RCR_SOFTRST (0x80)
+#define RCM_RCR_FRCRSTOUT (0x40)
+
+#define RCM_RSR_SOFT (0x20)
+#define RCM_RSR_LOC (0x10)
+#define RCM_RSR_POR (0x08)
+#define RCM_RSR_EXT (0x04)
+#define RCM_RSR_WDR_CORE (0x02)
+#define RCM_RSR_LOL (0x01)
+
+/* *** Chip Configuration Module (CCM) *** */
+#define CCM_CCR_CSC (0x0020)
+#define CCM_CCR_BOOTPS (0x0010)
+#define CCM_CCR_LOAD (0x0008)
+#define CCM_CCR_OSC_MODE (0x0004)
+#define CCM_CCR_SDR_MODE (0x0002)
+#define CCM_CCR_RESERVED (0x0001)
+
+#define CCM_RCON_SDR_32BIT_UNIFIED (0x0012)
+#define CCM_RCON_DDR_8BIT_SPLIT (0x0010)
+#define CCM_RCON_SDR_16BIT_UNIFIED (0x0002)
+#define CCM_RCON_DDR_16BIT_SPLIT (0x0000)
+
+#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
+#define CCM_CIR_PRN(x) ((x) & 0x003F)
+
+#define CCM_MISCCR_FECM (0x8000)
+#define CCM_MISCCR_CDCSRC (0x4000)
+#define CCM_MISCCR_PLL_LOCK (0x2000)
+#define CCM_MISCCR_LIMP (0x1000)
+#define CCM_MISCCR_BME (0x8000)
+#define CCM_MISCCR_BMT_MASK (0xF8FF)
+#define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8)
+#define CCM_MISCCR_BMT_512 (0x0700)
+#define CCM_MISCCR_BMT_1024 (0x0600)
+#define CCM_MISCCR_BMT_2048 (0x0500)
+#define CCM_MISCCR_BMT_4096 (0x0400)
+#define CCM_MISCCR_BMT_8192 (0x0300)
+#define CCM_MISCCR_BMT_16384 (0x0200)
+#define CCM_MISCCR_BMT_32768 (0x0100)
+#define CCM_MISCCR_BMT_65536 (0x0000)
+#define CCM_MISCCR_TIM_DMA (0x0020)
+#define CCM_MISCCR_SSI_SRC (0x0010)
+#define CCM_MISCCR_USBH_OC (0x0008)
+#define CCM_MISCCR_USBO_OC (0x0004)
+#define CCM_MISCCR_USB_PUE (0x0002)
+#define CCM_MISCCR_USB_SRC (0x0001)
+
+#define CCM_CDR_LPDIV(x) (((x) & 0x0F) << 8)
+#define CCM_CDR_SSIDIV(x) ((x) & 0xFF)
+
+#define CCM_UOCSR_DPPD (0x2000)
+#define CCM_UOCSR_DMPD (0x1000)
+#define CCM_UOCSR_DRV_VBUS (0x0800)
+#define CCM_UOCSR_CRG_VBUS (0x0400)
+#define CCM_UOCSR_DCR_VBUS (0x0200)
+#define CCM_UOCSR_DPPU (0x0100)
+#define CCM_UOCSR_AVLD (0x0080)
+#define CCM_UOCSR_BVLD (0x0040)
+#define CCM_UOCSR_VVLD (0x0020)
+#define CCM_UOCSR_SEND (0x0010)
+#define CCM_UOCSR_PWRFLT (0x0008)
+#define CCM_UOCSR_WKUP (0x0004)
+#define CCM_UOCSR_UOMIE (0x0002)
+#define CCM_UOCSR_XPDE (0x0001)
+
+#define CCM_UHCSR_PORTIND(x) (((x) & 0x0003) << 14)
+#define CCM_UHCSR_DRV_VBUS (0x0010)
+#define CCM_UHCSR_PWRFLT (0x0008)
+#define CCM_UHCSR_WKUP (0x0004)
+#define CCM_UHCSR_UHMIE (0x0002)
+#define CCM_UHCSR_XPDE (0x0001)
+
+#define CCM_CODCR_BGREN (0x8000)
+#define CCM_CODCR_REGEN (0x0080)
+
+#define CCM_MISC2_IGNLL (0x0008)
+#define CCM_MISC2_DPS (0x0001)
+
+/* *** General Purpose I/O (GPIO) *** */
+#define GPIO_PDR_FBCTL ((x) & 0x0F)
+#define GPIO_PDR_BE ((x) & 0x0F)
+#define GPIO_PDR_CS32 (((x) & 0x03) << 4)
+#define GPIO_PDR_CS10 (((x) & 0x03) << 4)
+#define GPIO_PDR_DSPI ((x) & 0x7F)
+#define GPIO_PDR_FEC0 ((x) & 0x7F)
+#define GPIO_PDR_FECI2C ((x) & 0x3F)
+#define GPIO_PDR_SIMP1 ((x) & 0x1F)
+#define GPIO_PDR_SIMP0 ((x) & 0x1F)
+#define GPIO_PDR_TIMER ((x) & 0x0F)
+#define GPIO_PDR_UART ((x) & 0x3F)
+#define GPIO_PDR_DEBUG (0x01)
+#define GPIO_PDR_SDHC ((x) & 0x3F)
+#define GPIO_PDR_SSI ((x) & 0x1F)
+
+#define GPIO_PAR_FBCTL_OE (0x80)
+#define GPIO_PAR_FBCTL_TA (0x40)
+#define GPIO_PAR_FBCTL_RWB (0x20)
+#define GPIO_PAR_FBCTL_TS (0x18)
+
+#define GPIO_PAR_BE3 (0x40)
+#define GPIO_PAR_BE2 (0x10)
+#define GPIO_PAR_BE1 (0x04)
+#define GPIO_PAR_BE0 (0x01)
+
+#define GPIO_PAR_CS5 (0x40)
+#define GPIO_PAR_CS4 (0x10)
+#define GPIO_PAR_CS1_MASK (0xF3)
+#define GPIO_PAR_CS1_CS1 (0x0C)
+#define GPIO_PAR_CS1_SDCS1 (0x08)
+#define GPIO_PAR_CS0_MASK (0xFC)
+#define GPIO_PAR_CS0_CS0 (0x03)
+#define GPIO_PAR_CS0_CS4 (0x02)
+
+#define GPIO_PAR_DSPIH_SIN_MASK (0x3F)
+#define GPIO_PAR_DSPIH_SIN (0xC0)
+#define GPIO_PAR_DSPIH_SIN_U2RXD (0x80)
+#define GPIO_PAR_DSPIH_SOUT_MASK (0xCF)
+#define GPIO_PAR_DSPIH_SOUT (0x30)
+#define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20)
+#define GPIO_PAR_DSPIH_SCK_MASK (0xF3)
+#define GPIO_PAR_DSPIH_SCK (0x0C)
+#define GPIO_PAR_DSPIH_SCK_U2CTS (0x08)
+#define GPIO_PAR_DSPIH_PCS0_MASK (0xFC)
+#define GPIO_PAR_DSPIH_PCS0 (0x03)
+#define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02)
+
+#define GPIO_PAR_DSPIL_PCS1_MASK (0x3F)
+#define GPIO_PAR_DSPIL_PCS1 (0xC0)
+#define GPIO_PAR_DSPIL_PCS2_MASK (0xCF)
+#define GPIO_PAR_DSPIL_PCS2 (0x30)
+#define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20)
+#define GPIO_PAR_DSPIL_PCS3_MASK (0xF3)
+#define GPIO_PAR_DSPIL_PCS3 (0x0C)
+#define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08)
+
+#define GPIO_PAR_FEC1_7W_FEC (0x40)
+#define GPIO_PAR_FEC1_RMII_FEC (0x10)
+#define GPIO_PAR_FEC0_7W_FEC (0x04)
+#define GPIO_PAR_FEC0_RMII_FEC (0x01)
+
+/* GPIO_PAR_FECI2C */
+#define GPIO_PAR_FECI2C_RMII0_MASK (0x3F)
+#define GPIO_PAR_FECI2C_MDC0 (0x80)
+#define GPIO_PAR_FECI2C_MDIO0 (0x40)
+#define GPIO_PAR_FECI2C_RMII1_MASK (0xCF)
+#define GPIO_PAR_FECI2C_MDC1 (0x20)
+#define GPIO_PAR_FECI2C_MDIO1 (0x10)
+#define GPIO_PAR_FECI2C_SDA_MASK (0xF3)
+#define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2)
+#define GPIO_PAR_FECI2C_SDA_SDA (0x0C)
+#define GPIO_PAR_FECI2C_SDA_U2TXD (0x08)
+#define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04)
+#define GPIO_PAR_FECI2C_SCL_MASK (0xFC)
+#define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03)
+#define GPIO_PAR_FECI2C_SCL_SCL (0x03)
+#define GPIO_PAR_FECI2C_SCL_U2RXD (0x02)
+#define GPIO_PAR_FECI2C_SCL_MDC1 (0x01)
+
+#define GPIO_PAR_IRQ0H_IRQ07_MASK (0x3F)
+#define GPIO_PAR_IRQ0H_IRQ06_MASK (0xCF)
+#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10)
+#define GPIO_PAR_IRQ0H_IRQ04_MASK (0xFC)
+#define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02)
+
+#define GPIO_PAR_IRQ0L_IRQ01_MASK (0xF3)
+#define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08)
+
+#define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40)
+#define GPIO_PAR_IRQ1H_IRQ16_DDATA2 (0x10)
+#define GPIO_PAR_IRQ1H_IRQ15_DDATA1 (0x04)
+#define GPIO_PAR_IRQ1H_IRQ14_DDATA0 (0x01)
+
+#define GPIO_PAR_IRQ1L_IRQ13_PST3 (0x40)
+#define GPIO_PAR_IRQ1L_IRQ12_PST2 (0x10)
+#define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04)
+#define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01)
+
+#define GPIO_PAR_SIMP1H_DATA1_MASK (0x3F)
+#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0)
+#define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80)
+#define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40)
+#define GPIO_PAR_SIMP1H_VEN1_MASK (0xCF)
+#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30)
+#define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20)
+#define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10)
+#define GPIO_PAR_SIMP1H_RST1_MASK (0xF3)
+#define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C)
+#define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08)
+#define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04)
+#define GPIO_PAR_SIMP1H_PD1_MASK (0xFC)
+#define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03)
+#define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02)
+#define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01)
+
+#define GPIO_PAR_SIMP1L_CLK_MASK (0x3F)
+#define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0)
+#define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80)
+
+#define GPIO_PAR_SIMP0_DATA0 (0x10)
+#define GPIO_PAR_SIMP0_VEN0 (0x08)
+#define GPIO_PAR_SIMP0_RST0 (0x04)
+#define GPIO_PAR_SIMP0_PD0 (0x02)
+#define GPIO_PAR_SIMP0_CLK0 (0x01)
+
+#define GPIO_PAR_TIN3(x) (((x) & 0x03) << 6)
+#define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4)
+#define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2)
+#define GPIO_PAR_TIN0(x) ((x) & 0x03)
+#define GPIO_PAR_TIN3_MASK (0x3F)
+#define GPIO_PAR_TIN3_TIN3 (0xC0)
+#define GPIO_PAR_TIN3_TOUT3 (0x80)
+#define GPIO_PAR_TIN3_IRQ03 (0x40)
+#define GPIO_PAR_TIN2_MASK (0xCF)
+#define GPIO_PAR_TIN2_TIN2 (0x30)
+#define GPIO_PAR_TIN2_TOUT2 (0x20)
+#define GPIO_PAR_TIN2_IRQ02 (0x10)
+#define GPIO_PAR_TIN1_MASK (0xF3)
+#define GPIO_PAR_TIN1_TIN1 (0x0C)
+#define GPIO_PAR_TIN1_TOUT1 (0x08)
+#define GPIO_PAR_TIN1_DACK1 (0x04)
+#define GPIO_PAR_TIN0_MASK (0xFC)
+#define GPIO_PAR_TIN0_TIN0 (0x03)
+#define GPIO_PAR_TIN0_TOUT0 (0x02)
+#define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01)
+
+#define GPIO_PAR_UART_U2TXD (0x80)
+#define GPIO_PAR_UART_U2RXD (0x40)
+#define GPIO_PAR_UART_U0TXD (0x20)
+#define GPIO_PAR_UART_U0RXD (0x10)
+#define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2)
+#define GPIO_PAR_UART_CTS0(x) ((x) & 0x03)
+#define GPIO_PAR_UART_RTS0_MASK (0xF3)
+#define GPIO_PAR_UART_RTS0_U0RTS (0x0C)
+#define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08)
+#define GPIO_PAR_UART_CTS0_MASK (0xFC)
+#define GPIO_PAR_UART_CTS0_U0CTS (0x03)
+#define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02)
+#define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01)
+
+#define GPIO_PAR_DEBUG_ALLPST (0x80)
+
+#define GPIO_PAR_SDHC_DATA3 (0x20)
+#define GPIO_PAR_SDHC_DATA2 (0x10)
+#define GPIO_PAR_SDHC_DATA1 (0x08)
+#define GPIO_PAR_SDHC_DATA0 (0x04)
+#define GPIO_PAR_SDHC_CMD (0x02)
+#define GPIO_PAR_SDHC_CLK (0x01)
+
+#define GPIO_PAR_SSIH_RXD(x) (((x) & 0x03) << 6)
+#define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4)
+#define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2)
+#define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03)
+#define GPIO_PAR_SSIH_RXD_MASK (0x3F)
+#define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0)
+#define GPIO_PAR_SSIH_RXD_U1RXD (0x40)
+#define GPIO_PAR_SSIH_TXD_MASK (0xCF)
+#define GPIO_PAR_SSIH_TXD_SSIRXD (0x30)
+#define GPIO_PAR_SSIH_TXD_U1TXD (0x10)
+#define GPIO_PAR_SSIH_FS_MASK (0xF3)
+#define GPIO_PAR_SSIH_FS_SSIFS (0x0C)
+#define GPIO_PAR_SSIH_FS_U1RTS (0x04)
+#define GPIO_PAR_SSIH_MCLK_MASK (0xFC)
+#define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03)
+#define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01)
+
+#define GPIO_PAR_SSIL_MASK (0x3F)
+#define GPIO_PAR_SSIL_BCLK (0xC0)
+#define GPIO_PAR_SSIL_U1CTS (0x40)
+
+#define GPIO_MSCR_MSCR1(x) (((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCRn_MASK (0x1F)
+#define GPIO_MSCR_MSCRn_SDR (0xE0)
+#define GPIO_MSCR_MSCRn_25VDDR (0x60)
+#define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20)
+#define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00)
+
+#define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2)
+#define GPIO_MSCR_MSCR5_MASK (0xE3)
+#define GPIO_MSCR_MSCR5_SDR (0x1C)
+#define GPIO_MSCR_MSCR5_25VDDR (0x0C)
+#define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04)
+#define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00)
+
+#define GPIO_SRCR_DSPI_MASK (0xFC)
+#define GPIO_SRCR_DSPI(x) ((x) & 0x03)
+#define GPIO_SRCR_I2C_MASK (0xFC)
+#define GPIO_SRCR_I2C(x) ((x) & 0x03)
+#define GPIO_SRCR_IRQ_IRQ0_MASK (0xF3)
+#define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2)
+#define GPIO_SRCR_IRQ_IRQ1DBG_MASK (0xFC)
+#define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03)
+#define GPIO_SRCR_SIM_SIMP0_MASK (0xF3)
+#define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2)
+#define GPIO_SRCR_SIM_SIMP1_MASK (0xFC)
+#define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03)
+#define GPIO_SRCR_TIMER_MASK (0xFC)
+#define GPIO_SRCR_TIMER(x) ((x) & 0x03)
+#define GPIO_SRCR_UART2_MASK (0xF3)
+#define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2)
+#define GPIO_SRCR_UART0_MASK (0xFC)
+#define GPIO_SRCR_UART0(x) ((x) & 0x03)
+#define GPIO_SRCR_SDHC_MASK (0xFC)
+#define GPIO_SRCR_SDHC(x) ((x) & 0x03)
+#define GPIO_SRCR_SSI_MASK (0xFC)
+#define GPIO_SRCR_SSI(x) ((x) & 0x03)
+
+#define SRCR_HIGHEST (0x03)
+#define SRCR_HIGH (0x02)
+#define SRCR_LOW (0x01)
+#define SRCR_LOWEST (0x00)
+
+#define GPIO_DSCR_FEC_RMIICLK_MASK (0xCF)
+#define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4)
+#define GPIO_DSCR_FEC_RMII0_MASK (0xF3)
+#define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2)
+#define GPIO_DSCR_FEC_RMII1_MASK (0xFC)
+#define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03)
+
+#define DSCR_50PF (0x03)
+#define DSCR_30PF (0x02)
+#define DSCR_20PF (0x01)
+#define DSCR_10PF (0x00)
+
+#define GPIO_PCRH_DSPI_PCS0_PULLUP_EN (0x80)
+#define GPIO_PCRH_SIM_VEN1_PULLUP_EN (0x40)
+#define GPIO_PCRH_SIM_VEN1_PULLUP (0x20)
+#define GPIO_PCRH_SIM_DATA1_PULLUP_EN (0x10)
+#define GPIO_PCRH_SIM_DATA1_PULLUP (0x08)
+#define GPIO_PCRH_SSI_PULLUP_EN (0x02)
+#define GPIO_PCRH_SSI_PULLUP (0x01)
+
+#define GPIO_PCRL_SDHC_DATA3_PULLUP_EN (0x80)
+#define GPIO_PCRL_SDHC_DATA3_PULLUP (0x40)
+#define GPIO_PCRL_SDHC_DATA2_PULLUP_EN (0x20)
+#define GPIO_PCRL_SDHC_DATA1_PULLUP_EN (0x10)
+#define GPIO_PCRL_SDHC_DATA0_PULLUP_EN (0x08)
+#define GPIO_PCRL_SDHC_CMD_PULLUP_EN (0x04)
+
+/* *** Phase Locked Loop (PLL) *** */
+#define PLL_PCR_LOC_IRQ (0x00040000)
+#define PLL_PCR_LOC_RE (0x00020000)
+#define PLL_PCR_LOC_EN (0x00010000)
+#define PLL_PCR_LOL_IRQ (0x00004000)
+#define PLL_PCR_LOL_RE (0x00002000)
+#define PLL_PCR_LOL_EN (0x00001000)
+#define PLL_PCR_REFDIV_MASK (0xFFFFF8FF)
+#define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8)
+#define PLL_PCR_FBDIV_MASK (0xFFFFFFC0)
+#define PLL_PCR_FBDIV(x) ((x) & 0x3F)
+
+#define PLL_PDR_OUTDIV4_MASK (0x0FFF)
+#define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12)
+#define PLL_PDR_OUTDIV3_MASK (0xF0FF)
+#define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8)
+#define PLL_PDR_OUTDIV2_MASK (0xFF0F)
+#define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4)
+#define PLL_PDR_OUTDIV1_MASK (0xFFF0)
+#define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F)
+#define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x)
+#define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x)
+#define PLL_PDR_FB(x) PLL_PDR_OUTDIV2(x)
+#define PLL_PDR_CPU(x) PLL_PDR_OUTDIV1(x)
+
+#define PLL_PSR_LOCF (0x00000200)
+#define PLL_PSR_LOC (0x00000100)
+#define PLL_PSR_LOLF (0x00000040)
+#define PLL_PSR_LOCKS (0x00000020)
+#define PLL_PSR_LOCK (0x00000010)
+#define PLL_PSR_MODE(x) ((x) & 0x07)
+
+/* *** Real Time Clock *** */
+#define RTC_OCEN_OSCBYP (0x00000010)
+#define RTC_OCEN_CLKEN (0x00000008)
+
+#endif /* m5301x_h */
--- /dev/null
+/*
+ * Configuation settings for the Freescale MCF53017EVB.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M53017EVB_H
+#define _M53017EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5301x /* define processor family */
+#define CONFIG_M53015 /* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 5000
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CONFIG_MII_INIT 1
+# define CONFIG_SYS_DISCOVER_PHY
+# define CONFIG_SYS_RX_ETH_BUFFER 8
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_HAS_ETH1
+
+# define CONFIG_SYS_FEC0_PINMUX 0
+# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
+# define CONFIG_SYS_FEC1_PINMUX 0
+# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CONFIG_SYS_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_CNT (0x8000)
+#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED 80000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
+# define CONFIG_IPADDR 192.162.1.2
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.162.1.1
+# define CONFIG_GATEWAYIP 192.162.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_HOSTNAME M53017
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off 0 3ffff;" \
+ "era 0 3ffff;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+
+#define CONFIG_PRAM 512 /* 512 KB */
+#define CONFIG_SYS_PROMPT "-> "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
+#define CONFIG_SYS_LOAD_ADDR 0x40010000
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_CLK 80000000
+#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
+
+#define CONFIG_SYS_MBAR 0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
+#define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL 0x21
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1 0x43711630
+#define CONFIG_SYS_SDRAM_CFG2 0x56670000
+#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
+#define CONFIG_SYS_SDRAM_EMOD 0x80010000
+#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+# define CONFIG_FLASH_CFI_DRIVER 1
+# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
+# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
+# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET 0x8000
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_SECT_SIZE 0x8000
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Ext SRAM
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE 0
+#define CONFIG_SYS_CS0_MASK 0x00FF0001
+#define CONFIG_SYS_CS0_CTRL 0x00001FA0
+
+#define CONFIG_SYS_CS1_BASE 0xC0000000
+#define CONFIG_SYS_CS1_MASK 0x00070001
+#define CONFIG_SYS_CS1_CTRL 0x00001FA0
+
+#endif /* _M53017EVB_H */
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