arm: k3: Enable instruction cache for main domain SPL

Change spl_enable_dcache so it also enable icache on SPL
initialization for the main domain part of the boot flow. This
improves bootloader booting time.

Link: https://lore.kernel.org/all/20231109140958.1093235-1-joao.goncalves@toradex.com/
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Tested-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 8fa36f7b913ea1cd3b395087367f2ed74282c2a3..1d4ef35e7b4c029f61ae2383c66ae3d16cb78fa3 100644 (file)
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -209,7 +209,7 @@ void board_init_f(ulong dummy)
                if (ret)
                        panic("DRAM init failed: %d\n", ret);
        }
-       spl_enable_dcache();
+       spl_enable_cache();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c
index 4235296774cfa0022800113791dc374fb37d272e..7c2a143ed1bd07536baa55fecff40a5dfa5de22e 100644 (file)
--- a/arch/arm/mach-k3/am654_init.c
+++ b/arch/arm/mach-k3/am654_init.c
@@ -258,7 +258,7 @@ void board_init_f(ulong dummy)
        if (ret)
                panic("DRAM init failed: %d\n", ret);
 #endif
-       spl_enable_dcache();
+       spl_enable_cache();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 4c7b03fe6e0c2440e69d8825492ec333a2a96916..fd400e7e3dd87c636d1a74d98d78c748bd059e47 100644 (file)
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -521,7 +521,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
        }
 }
 
-void spl_enable_dcache(void)
+void spl_enable_cache(void)
 {
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
        phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
@@ -542,7 +542,7 @@ void spl_enable_dcache(void)
              gd->arch.tlb_addr + gd->arch.tlb_size);
        gd->relocaddr = gd->arch.tlb_addr;
 
-       dcache_enable();
+       enable_caches();
 #endif
 }
 

diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 04f3c0b85bd103087a804a0ab1576269ee3b2fdc..e9db9fbfb63dfa4e172c72d39c90c61831e142db 100644 (file)
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -37,7 +37,7 @@ void disable_linefill_optimization(void);
 void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
 int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
 void k3_sysfw_print_ver(void);
-void spl_enable_dcache(void);
+void spl_enable_cache(void);
 void mmr_unlock(uintptr_t base, u32 partition);
 bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
 enum k3_device_type get_device_type(void);

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 8738f91ee3c562804d3e52cd90b30af026435dff..c2976c4ea0dff92cb136ef8a9a460dc0e40dc785 100644 (file)
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -286,7 +286,7 @@ void board_init_f(ulong dummy)
        if (ret)
                panic("DRAM init failed: %d\n", ret);
 #endif
-       spl_enable_dcache();
+       spl_enable_cache();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index 39499be271523e83e0e520c1d9080165afa18a04..fb0708bae162a4206b3d6c77205089f0875c7b90 100644 (file)
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -231,7 +231,7 @@ void k3_mem_init(void)
                if (ret)
                        panic("DRAM 1 init failed: %d\n", ret);
        }
-       spl_enable_dcache();
+       spl_enable_cache();
 }
 
 /* Support for the various EVM / SK families */