Fix MPC85xx PCI support (pci_register_hose() before pci config access)

Patch by Stefan Roese, 07 Nov 2005

diff --git a/CHANGELOG b/CHANGELOG
index df3003e4ca59499aa36a51fbcd5b93be83b85ea3..5c6d68fff06c147d41f34dc6454be587cd5de248 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Fix MPC85xx PCI support (pci_register_hose() before pci config access)
+  Patch by Stefan Roese, 07 Nov 2005
+
 * Correct PPC Timebase register definitions (SPRN_TBRL...)
   Patch by Stefan Roese, 07 Nov 2005
 

diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 069fe4e69a6911c5104612d39557ba330b071182..a94493e0802c9424e575b0cd94cd98ff7debf586 100644 (file)
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -61,16 +61,6 @@ pci_mpc85xx_init(struct pci_controller *hose)
                           (CFG_IMMR+0x8000),
                           (CFG_IMMR+0x8004));
 
-       pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
-       reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-       pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
-       /*
-        * Clear non-reserved bits in status register.
-        */
-       pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
-       pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
-
        pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
        pcix->potear1  = 0x00000000;
        pcix->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
@@ -93,6 +83,16 @@ pci_mpc85xx_init(struct pci_controller *hose)
         */
        pci_register_hose(hose);
 
+       pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+       reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+       pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+       /*
+        * Clear non-reserved bits in status register.
+        */
+       pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+       pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+
 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
        /*
         * This is a SW workaround for an apparent HW problem