i.MX31: Fix mx31_gpio_mux() function and MUX_-macros.

Correct the mx31_gpio_mux() function to allow changing all i.MX31 IOMUX
contacts instead of only the first 256 ones as is the case prior to
this patch.

Add missing MUX_* macros and update board files to use the new macros.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>

diff --git a/board/imx31_litekit/imx31_litekit.c b/board/imx31_litekit/imx31_litekit.c
index 8cbc26ed11c886b186bb0b2b53e6f9234243a057..cb3e174841838351ba8c66c8cfc63e5531961ccd 100644 (file)
--- a/board/imx31_litekit/imx31_litekit.c
+++ b/board/imx31_litekit/imx31_litekit.c
@@ -53,13 +53,13 @@ int board_init (void)
        mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
        /* SPI2 */
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
+       mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+       mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+       mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+       mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+       mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+       mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+       mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
 
        /* start SPI2 clock */
        __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);

diff --git a/board/mx31ads/mx31ads.c b/board/mx31ads/mx31ads.c
index b6928fc241f71168c8aeffd75598eb993d9634da..c24c47c57f885a6f006db0b6eb7080d00338b260 100644 (file)
--- a/board/mx31ads/mx31ads.c
+++ b/board/mx31ads/mx31ads.c
@@ -58,13 +58,13 @@ int board_init (void)
        mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
        /* SPI2 */
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
-       mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
+       mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+       mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+       mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+       mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+       mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+       mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+       mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
 
        /* start SPI2 clock */
        __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);

diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c
index 29c08c105f1e1d601b3f1ec0002cb914c3038324..dc031c92ea936ab7104c5d19bcce5a2c11eed8a9 100644 (file)
--- a/cpu/arm1136/mx31/generic.c
+++ b/cpu/arm1136/mx31/generic.c
@@ -81,12 +81,12 @@ void mx31_gpio_mux(unsigned long mode)
 {
        unsigned long reg, shift, tmp;
 
-       reg = IOMUXC_BASE + (mode & 0xfc);
+       reg = IOMUXC_BASE + (mode & 0x1fc);
        shift = (~mode & 0x3) * 8;
 
        tmp = __REG(reg);
        tmp &= ~(0xff << shift);
-       tmp |= ((mode >> 8) & 0xff) << shift;
+       tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
        __REG(reg) = tmp;
 }
 

diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index abe61f09f3e8f3d044d554603318d452e378b841..b04a718e6a6ab7e9b0e5113dbb260d1756548bd8 100644 (file)
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -126,17 +126,32 @@
 #define MUX_CTL_CSPI2_SS2      0x87
 #define MUX_CTL_CSPI2_MOSI     0x8b
 
-/* The modes a specific pin can be in
- * these macros can be used in mx31_gpio_mux() and have the form
- * MUX_[contact name]__[pin function]
+/*
+ * Helper macros for the MUX_[contact name]__[pin function] macros
  */
-#define MUX_RXD1__UART1_RXD_MUX        ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
-#define MUX_TXD1__UART1_TXD_MUX        ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
-#define MUX_RTS1__UART1_RTS_B  ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
-#define MUX_CTS1__UART1_CTS_B  ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
+#define IOMUX_MODE_POS 9
+#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
 
-#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
-#define MUX_CSPI2_MISO__I2C2_SDA ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
+/*
+ * These macros can be used in mx31_gpio_mux() and have the form
+ * MUX_[contact name]__[pin function]
+ */
+#define MUX_RXD1__UART1_RXD_MUX        IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
+#define MUX_TXD1__UART1_TXD_MUX        IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
+#define MUX_RTS1__UART1_RTS_B  IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
+#define MUX_CTS1__UART1_CTS_B  IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
+
+#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
+       IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
+
+#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
+#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 
 /*
  * Memory regions and CS