ppc4xx: Enable cache support on the ALPR board

Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>

diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
index 135674c26a72e933c5ae84fa110ff39acef6644e..76164ce1db8a349eab2709a4353955b43f5480bc 100644 (file)
--- a/board/prodrive/alpr/init.S
+++ b/board/prodrive/alpr/init.S
@@ -90,7 +90,16 @@ tlbtab:
        tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
        tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
        tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+#ifdef CONFIG_4xx_DCACHE
+       tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
+#else
        tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#endif
+
+#ifdef CFG_INIT_RAM_DCACHE
+       /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+       tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
        tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
 
        /* PCI */

diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 38fb7c6c789dae1adc4189f9cf91ebcddff17113..2d04f698f1f37423da599cf9bd1646871316f36b 100644 (file)
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -35,6 +35,7 @@
 #define CONFIG_LAST_STAGE_INIT 1           /* call last_stage_init()   */
 #undef CFG_DRAM_TEST                       /* Disable-takes long time! */
 #define CONFIG_SYS_CLK_FREQ    33333333    /* external freq to pll     */
+#define CONFIG_4xx_DCACHE              /* Enable i- and d-cache        */
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the