ARM: tegra: pull Tegra20 SoC DT from Linux v4.7

This brings in a few minor fixes since the last sync. The largest change
is the removal of the definition for TEGRA20_CLK_PCIE_XCLK. This clock
doesn't actually exist.

Remaining deltas:
* Addition of u-boot,dm-pre-reloc property to a couple of nodes.
* Addition of the NAND controller, which Linux doesn't yet support.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 31223e4fc9aa6d55afa380e165ad23f760d271d4..84bb1b0215c8cf83ebc88b033027c055251379c5 100644 (file)
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -147,7 +147,7 @@
                interrupt-parent = <&intc>;
                reg = <0x50040600 0x20>;
                interrupts = <GIC_PPI 13
-                       (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                       (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
                clocks = <&tegra_car TEGRA20_CLK_TWD>;
        };
 
@@ -311,7 +311,7 @@
         * driver and APB DMA based serial driver for higher baudrate
         * and performace. To enable the 8250 based driver, the compatible
         * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
-        * driver, the comptible is "nvidia,tegra20-hsuart".
+        * driver, the compatible is "nvidia,tegra20-hsuart".
         */
        uarta: serial@70006000 {
                compatible = "nvidia,tegra20-uart";

diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index a1ae9a8fdd6c5bbb5bd0472d65791b650b660a6c..04500b243a4d89be0731a326baca289ee4efbd29 100644 (file)
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -49,7 +49,7 @@
 /* 30 */
 #define TEGRA20_CLK_CACHE2 31
 
-#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_MC 32
 #define TEGRA20_CLK_AHBDMA 33
 #define TEGRA20_CLK_APBDMA 34
 /* 35 */
@@ -92,7 +92,7 @@
 #define TEGRA20_CLK_OWR 71
 #define TEGRA20_CLK_AFI 72
 #define TEGRA20_CLK_CSITE 73
-#define TEGRA20_CLK_PCIE_XCLK 74
+/* 74 */
 #define TEGRA20_CLK_AVPUCQ 75
 #define TEGRA20_CLK_LA 76
 /* 77 */