powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata

In the current u-boot code, the value of these fields are the reserved
value (0b100), through the signal integrity measurement on freescale's
board with these reserved setting, the signal eye is out of the recommended
spec for non-transition amplitude at 500mV nominal.
According to the errata for MPC8379E, we should make a change to the
recommended setting from essentially nothing at this time to 0b001 for SATA.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c
index fecfc80f81d35867c0d78e70b1085c30a092362d..a88fab91b2cc8f0f045cc19e32df95a336a5b774 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/serdes.c
+++ b/arch/powerpc/cpu/mpc83xx/serdes.c
@@ -1,7 +1,7 @@
 /*
  * Freescale SerDes initialization routine
  *
- * Copyright (C) 2007 Freescale Semicondutor, Inc.
+ * Copyright (C) 2007,2011 Freescale Semicondutor, Inc.
  * Copyright (C) 2008 MontaVista Software, Inc.
  *
  * Author: Li Yang <leoli@freescale.com>
@@ -20,6 +20,10 @@
 /* SerDes registers */
 #define FSL_SRDSCR0_OFFS               0x0
 #define FSL_SRDSCR0_DPP_1V2            0x00008800
+#define FSL_SRDSCR0_TXEQA_MASK         0x00007000
+#define FSL_SRDSCR0_TXEQA_SATA         0x00001000
+#define FSL_SRDSCR0_TXEQE_MASK         0x00000700
+#define FSL_SRDSCR0_TXEQE_SATA         0x00000100
 #define FSL_SRDSCR1_OFFS               0x4
 #define FSL_SRDSCR1_PLLBW              0x00000040
 #define FSL_SRDSCR2_OFFS               0x8
@@ -71,6 +75,11 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
                tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
                out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
 
+               /* Configure SRDSCR0 */
+               clrsetbits_be32(regs + FSL_SRDSCR0_OFFS,
+                       FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK,
+                       FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA);
+
                /* Configure SRDSCR1 */
                tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
                tmp &= ~FSL_SRDSCR1_PLLBW;