CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
- CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
- CONFIG_SYS_NAND_ECCBYTES
+ CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
+ CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
- CONFIG_SYS_NAND_U_BOOT_DST
+ CFG_SYS_NAND_U_BOOT_DST
Location in memory to load U-Boot to
- CONFIG_SYS_NAND_U_BOOT_SIZE
+ CFG_SYS_NAND_U_BOOT_SIZE
Size of image to load
- CONFIG_SYS_NAND_U_BOOT_START
+ CFG_SYS_NAND_U_BOOT_START
Entry point in loaded image to jump to
CONFIG_SPL_RAM_DEVICE
#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
+#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
#else
#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
#endif
-#define CONFIG_SYS_NAND_ECCSIZE 0x100
-#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCSIZE 0x100
+#define CFG_SYS_NAND_ECCBYTES 3
#endif /* CONFIG_NAND_LPC32XX_SLC */
/* NOR Flash */
#define MASK_CLE 0x10
#define MASK_ALE 0x08
-#ifdef CONFIG_SYS_NAND_MASK_CLE
+#ifdef CFG_SYS_NAND_MASK_CLE
#undef MASK_CLE
-#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#define MASK_CLE CFG_SYS_NAND_MASK_CLE
#endif
-#ifdef CONFIG_SYS_NAND_MASK_ALE
+#ifdef CFG_SYS_NAND_MASK_ALE
#undef MASK_ALE
-#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#define MASK_ALE CFG_SYS_NAND_MASK_ALE
#endif
struct davinci_emif_regs {
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
+#define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
#endif
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
case MTD_DEV_TYPE_NAND:
gpmc_regs = gpmc_regs_nand;
- base = CONFIG_SYS_NAND_BASE;
+ base = CFG_SYS_NAND_BASE;
size = GPMC_SIZE_16M;
break;
#endif
#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
#endif
* has been determined
*/
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) \
- && defined(CONFIG_SYS_NAND_OR_PRELIM) \
+#if defined(CFG_SYS_NAND_BR_PRELIM) \
+ && defined(CFG_SYS_NAND_OR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+ set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
#else
-#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
+#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
#endif
}
&smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
at91_periph_clk_enable(ATMEL_ID_PIOCDE);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
at91_periph_clk_enable(ATMEL_ID_PIOD);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
at91_periph_clk_enable(ATMEL_ID_PIOCD);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
- ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+ ret = gpio_request(CFG_SYS_NAND_READY_PIN, "nand_rdy");
if (ret)
return ret;
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+ ret = gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand_ce");
if (ret)
return ret;
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
return 0;
}
at91_periph_clk_enable(ATMEL_ID_PIOCDE);
/* Configure RDY/BSY */
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_request(CFG_SYS_NAND_READY_PIN, "NAND ready/busy");
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_request(CFG_SYS_NAND_ENABLE_PIN, "NAND enable");
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
/* Ready pin is optional. */
- at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_pio_input(CFG_SYS_NAND_READY_PIN, 1);
#endif
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
&smc->cs[3].mode);
/* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif /* CONFIG_CMD_NAND */
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
};
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_4M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
},
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
},
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
return;
/* Change NAND Flash PGS/SPRZ configuration */
- csor = CONFIG_SYS_NAND_CSOR;
+ csor = CFG_SYS_NAND_CSOR;
if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
},
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
},
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
- CONFIG_SYS_NAND_CSPR,
- CONFIG_SYS_NAND_CSPR_EXT,
- CONFIG_SYS_NAND_AMASK,
- CONFIG_SYS_NAND_CSOR,
+ CFG_SYS_NAND_CSPR,
+ CFG_SYS_NAND_CSPR_EXT,
+ CFG_SYS_NAND_AMASK,
+ CFG_SYS_NAND_CSOR,
{
- CONFIG_SYS_NAND_FTIM0,
- CONFIG_SYS_NAND_FTIM1,
- CONFIG_SYS_NAND_FTIM2,
- CONFIG_SYS_NAND_FTIM3
+ CFG_SYS_NAND_FTIM0,
+ CFG_SYS_NAND_FTIM1,
+ CFG_SYS_NAND_FTIM2,
+ CFG_SYS_NAND_FTIM3
},
},
{
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
};
int num_law_entries = ARRAY_SIZE(law_table);
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
#endif
/* initialize selected port with appropriate baud rate */
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
};
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
#endif
/* initialize selected port with appropriate baud rate */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+#ifdef CFG_SYS_NAND_BASE
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
#endif
};
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
#endif
};
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_32M, 1),
#endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
/*
* *I*G - NAND
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for nand.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_64K, 1),
#endif
at91_periph_clk_enable(ATMEL_ID_PIOCD);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+ SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
/* other application LAW are not used in u-boot */
0, 9, BOOKE_PAGESZ_4M, 1),
/* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
/* QRIO */
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
&smc->cs[3].mode);
/* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
at91_periph_clk_enable(ATMEL_ID_PIOC);
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
/* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+ gpio_direction_input(CFG_SYS_NAND_READY_PIN);
#endif
/* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
static void corvus_request_gpio(void)
{
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+ gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+ gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(AT91_PIN_PD7, "d0");
gpio_request(AT91_PIN_PD8, "d1");
gpio_request(AT91_PIN_PA12, "d2");
at91_periph_clk_enable(ATMEL_ID_PIOA);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
}
#if defined(CONFIG_SPL_BUILD)
static void smartweb_request_gpio(void)
{
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+ gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+ gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(AT91_PIN_PA26, "ena PHY");
}
&smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
static void smartweb_macb_hw_init(void)
static void taurus_request_gpio(void)
{
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+ gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+ gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
gpio_request(AT91_PIN_PA25, "ena PHY");
}
&smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
#if defined(CONFIG_SPL_BUILD)
} else {
puts("erase spi flash sector 0\n");
spi_flash_erase(flash, 0,
- CONFIG_SYS_NAND_U_BOOT_SIZE);
+ CFG_SYS_NAND_U_BOOT_SIZE);
}
}
}
#include <common.h>
-#if defined(CONFIG_SYS_NAND_BASE)
+#if defined(CFG_SYS_NAND_BASE)
#include <nand.h>
#include <linux/errno.h>
#include <linux/mtd/rawnand.h>
nand_init();
printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n",
- CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- CONFIG_SYS_NAND_U_BOOT_DST);
+ CONFIG_SYS_NAND_U_BOOT_OFFS, CFG_SYS_NAND_U_BOOT_SIZE,
+ CFG_SYS_NAND_U_BOOT_DST);
nand_spl_load_image(spl_nand_get_uboot_raw_page(),
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CFG_SYS_NAND_U_BOOT_DST);
spl_set_header_raw_uboot(spl_image);
nand_deselect();
d) this initialize CPU, RAM, ... and copy itself to RAM
(this bin must fit in one page, so board_init_f()
don;t fit in it ... )
-e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and
- starts this image @ CONFIG_SYS_NAND_U_BOOT_START
+e) there it copy u-boot to CFG_SYS_NAND_U_BOOT_DST and
+ starts this image @ CFG_SYS_NAND_U_BOOT_START
f) u-boot code steps through board_init_f() and calculates
the relocation address and copy itself to it
- The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c
which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads
- the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
- @CONFIG_SYS_NAND_U_BOOT_START
+ the "real" u-boot to CFG_SYS_NAND_U_BOOT_DST and starts execution
+ @CFG_SYS_NAND_U_BOOT_START
- This u-boot does no RAM init, nor CPU register setup. Just look
where it has to copy and relocate itself to this address. If
When you require the SPL to read with BCH8 there are two more configs to
change:
- * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
+ * CFG_SYS_NAND_ECCPOS (must be the same as .eccpos in
GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
arch/arm/include/asm/arch-omap3/omap_gpmc.h)
- * CONFIG_SYS_NAND_ECCSIZE must be 512
- * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
+ * CFG_SYS_NAND_ECCSIZE must be 512
+ * CFG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
Acknowledgements
================
CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block
- CONFIG_SYS_NAND_ECCPOS ECC map for NAND page
+ CFG_SYS_NAND_ECCPOS ECC map for NAND page
CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand)
Step-2: Flashing NAND via MMC/SD
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+ CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
/*
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
uint32_t data_pos = 0;
*/
mtd = nand_to_mtd(&nand_chip);
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
- (void __iomem *)CONFIG_SYS_NAND_BASE;
+ (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
- | CONFIG_SYS_NAND_MASK_CLE);
+ IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE
+ | CFG_SYS_NAND_MASK_CLE);
if (ctrl & NAND_CLE)
- IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
+ IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE;
if (ctrl & NAND_ALE)
- IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
+ IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE;
-#ifdef CONFIG_SYS_NAND_ENABLE_PIN
- at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
+#ifdef CFG_SYS_NAND_ENABLE_PIN
+ at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN,
!(ctrl & NAND_NCE));
#endif
this->IO_ADDR_W = (void *) IO_ADDR_W;
writeb(cmd, this->IO_ADDR_W);
}
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
static int at91_nand_ready(struct mtd_info *mtd)
{
- return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
+ return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN);
}
#endif
}
#ifdef CONFIG_SPL_NAND_ECC
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+ CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
static int nand_read_page(int block, int page, void *dst)
{
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
int i;
uint8_t *p = dst;
nand->read_buf = nand_read_buf;
#endif
nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#else
nand->dev_ready = at91_nand_wait_ready;
mtd = nand_to_mtd(&nand_chip);
mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
- nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
- nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+ nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#ifdef CONFIG_SPL_NAND_ECC
#else
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
int atmel_nand_chip_init(int devnum, ulong base_addr)
{
nand->options = NAND_BUSWIDTH_16;
#endif
nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#endif
nand->chip_delay = 75;
u_int32_t ecc = 0;
ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ CFG_SYS_NAND_CS - 2]));
return ecc;
}
nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
- val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
- val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS);
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
*/
val = __raw_readl(&davinci_emif_regs->nandfcr);
val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
- val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
- val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_START;
__raw_writel(val, &davinci_emif_regs->nandfcr);
break;
struct mtd_info *mtd = nand_to_mtd(nand);
int ret;
- nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
- nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+ nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
davinci_nand_init(nand);
#define BANK(x) ((x) << 24)
static void __iomem *denali_flash_mem =
- (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+ (void __iomem *)CFG_SYS_NAND_DATA_BASE;
static void __iomem *denali_flash_reg =
- (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+ (void __iomem *)CFG_SYS_NAND_REGS_BASE;
static const int flash_bank;
static int page_size, oob_size, pages_per_block;
#ifndef CONFIG_NAND_FSL_ELBC_DT
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
- CONFIG_SYS_NAND_BASE_LIST;
+ CFG_SYS_NAND_BASE_LIST;
void board_nand_init(void)
{
#endif
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
- uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
- const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
+ uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
+ const int large = CFG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
const int block_shift = large ? 17 : 14;
const int block_size = 1 << block_shift;
const int page_size = large ? 2048 : 512;
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
- flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+ flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
#endif
puts("transfering control\n");
/*
* Jump to U-Boot image
*/
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
(*uboot)();
}
return 0;
}
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
- CONFIG_SYS_NAND_BASE_LIST;
+ CFG_SYS_NAND_BASE_LIST;
void board_nand_init(void)
{
{
struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
struct fsl_ifc_runtime *ifc = NULL;
- uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
+ uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
int page_size;
int port_size;
int pages_per_blk;
ifc = runtime_regs_address();
/* Get NAND Flash configuration */
- csor = CONFIG_SYS_NAND_CSOR;
- cspr = CONFIG_SYS_NAND_CSPR;
+ csor = CFG_SYS_NAND_CSOR;
+ cspr = CFG_SYS_NAND_CSPR;
port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
- flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+ flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
* calculate U-boot header address using U-boot header size.
*/
#define CONFIG_U_BOOT_HDR_ADDR \
- ((CONFIG_SYS_NAND_U_BOOT_START + \
- CONFIG_SYS_NAND_U_BOOT_SIZE) - \
+ ((CFG_SYS_NAND_U_BOOT_START + \
+ CFG_SYS_NAND_U_BOOT_SIZE) - \
CONFIG_U_BOOT_HDR_SIZE)
spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
- CONFIG_SYS_NAND_U_BOOT_START);
+ CFG_SYS_NAND_U_BOOT_START);
/*
* In case of failure in validation, spl_validate_uboot would
* not return back in case of Production environment with ITS=1.
*/
#endif
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
uboot();
}
nand->ecc.hwctl = fsmc_enable_hwecc;
nand->cmd_ctrl = fsmc_nand_hwcontrol;
nand->IO_ADDR_R = nand->IO_ADDR_W =
- (void __iomem *)CONFIG_SYS_NAND_BASE;
+ (void __iomem *)CFG_SYS_NAND_BASE;
nand->badblockbits = 7;
mtd = nand_to_mtd(nand);
#include <linux/delay.h>
#include <linux/mtd/rawnand.h>
-#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000)
-#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000)
+#define CONFIG_NAND_MODE_REG (void *)(CFG_SYS_NAND_BASE + 0x20000)
+#define CONFIG_NAND_DATA_REG (void *)(CFG_SYS_NAND_BASE + 0x30000)
#define read_mode() in_8(CONFIG_NAND_MODE_REG)
#define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val)
};
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
-#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE)
/*
* DMA Descriptors
DMAC_CHAN_DEST_AHB1;
/* CTRL descriptor entry for reading/writing Data */
- ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
+ ctrl = (CFG_SYS_NAND_ECCSIZE / 4) |
DMAC_CHAN_SRC_BURST_4 |
DMAC_CHAN_DEST_BURST_4 |
DMAC_CHAN_SRC_WIDTH_32 |
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
*/
- for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
+ for (i = 0; i < size/CFG_SYS_NAND_ECCSIZE; i++) {
dmalist_cur = &dmalist[i * 2];
dmalist_cur_ecc = &dmalist[(i * 2) + 1];
static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
{
int i;
- for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
- i += CONFIG_SYS_NAND_ECCBYTES) {
- u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
+ for (i = 0; i < (count * CFG_SYS_NAND_ECCBYTES);
+ i += CFG_SYS_NAND_ECCBYTES) {
+ u32 ce = ecc[i / CFG_SYS_NAND_ECCBYTES];
ce = ~(ce << 2) & 0xFFFFFF;
spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
u16 data_offset = 0;
for (i = 0 ; i < ECCSTEPS ; i++) {
- r += CONFIG_SYS_NAND_ECCBYTES;
- c += CONFIG_SYS_NAND_ECCBYTES;
- data_offset += CONFIG_SYS_NAND_ECCSIZE;
+ r += CFG_SYS_NAND_ECCBYTES;
+ c += CFG_SYS_NAND_ECCBYTES;
+ data_offset += CFG_SYS_NAND_ECCSIZE;
ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
if (ret1 < 0)
* These values are predefined
* for both small and large page NAND flash devices.
*/
- lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+ lpc32xx_chip->ecc.size = CFG_SYS_NAND_ECCSIZE;
+ lpc32xx_chip->ecc.bytes = CFG_SYS_NAND_ECCBYTES;
lpc32xx_chip->ecc.strength = 1;
if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
/* OOB placement block for use with hardware ecc generation */
#if defined(MXC_NFC_V1)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 5,
.eccpos = {6, 7, 8, 9, 10},
};
#endif
#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
if (is_16bit_nand())
this->options |= NAND_BUSWIDTH_16;
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
+#ifdef CFG_SYS_NAND_LARGEPAGE
host->pagesize_2k = 1;
this->ecc.layout = &nand_hw_eccoob2k;
#else
__attribute__((noreturn)) void (*uboot)(void);
/*
- * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
+ * CONFIG_SYS_NAND_U_BOOT_OFFS and CFG_SYS_NAND_U_BOOT_SIZE must
* be aligned to full pages
*/
if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CFG_SYS_NAND_U_BOOT_DST)) {
/* Copy from NAND successful, start U-Boot */
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
uboot();
} else {
/* Unrecoverable error when copying from NAND */
#include <linux/mtd/concat.h>
#include <linux/mtd/rawnand.h>
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
int nand_curr_device = -1;
#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
#endif
static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
/*
* Jump to U-Boot image
*/
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
(*uboot)();
}
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+ CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
*/
mtd = nand_to_mtd(&nand_chip);
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
- (void __iomem *)CONFIG_SYS_NAND_BASE;
+ (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#ifdef CONFIG_SPL_NAND_SOFTECC
cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) {
- *buf++ = readl(CONFIG_SYS_NAND_BASE);
+ *buf++ = readl(CFG_SYS_NAND_BASE);
len -= 4;
}
} while (len);
return;
}
- nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE;
err = vf610_nfc_nand_init(nfc, 0);
if (err)
printf("VF610 NAND init failed (err %d)\n", err);
#endif
#ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
-# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
+# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#endif
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
-# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
+# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
/* Ethernet configuration part */
/* NAND configuration part */
-#define CONFIG_SYS_NAND_BASE 0x0C000000
+#define CFG_SYS_NAND_BASE 0x0C000000
#endif /* __CONFIG_H */
/*
* NAND Flash on the Local Bus
*/
-#define CONFIG_SYS_NAND_BASE 0xE0600000
+#define CFG_SYS_NAND_BASE 0xE0600000
/* Vitesse 7385 */
#ifdef CONFIG_MTD_RAW_NAND
#ifdef CONFIG_NXP_ESBC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
+#define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#else
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CFG_SYS_NAND_U_BOOT_START (0x11000000)
#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
+#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0xD0000000
+#define CFG_SYS_NAND_U_BOOT_START 0xD0000000
#endif
#endif
#endif
/* CFI for NOR Flash */
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
+#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
#define CONFIG_MTD_PARTITION
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_TARGET_P1010RDB_PA)
/* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
+#define CFG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
FTIM0_NAND_TWP(0x0C) | \
FTIM0_NAND_TWCHT(0x04) | \
FTIM0_NAND_TWH(0x05)
-#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
+#define CFG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
FTIM1_NAND_TWBE(0x1d) | \
FTIM1_NAND_TRR(0x07) | \
FTIM1_NAND_TRP(0x0c)
-#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
+#define CFG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
FTIM2_NAND_TREH(0x05) | \
FTIM2_NAND_TWHRE(0x0f)
-#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
+#define CFG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
#elif defined(CONFIG_TARGET_P1010RDB_PB)
/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
#endif
/* Set up IFC registers for boot location NOR/NAND */
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
/* CPLD on IFC */
/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CFG_SYS_NAND_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
+#define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull
#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
+#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE}
/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+#define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
+#define CFG_SYS_NAND_U_BOOT_START 0x30000000
#endif
#ifdef CONFIG_SPIFLASH
#endif
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
#endif
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image.
*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
+#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
CONFIG_U_BOOT_HDR_SIZE)
#else
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#endif
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
+#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
+#define CFG_SYS_NAND_U_BOOT_START 0x30000000
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_SYS_CS3_FTIM3 0x0
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0x00200000
+#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0xf)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
| CSOR_NAND_PB(128)) /*Page Per Block = 128*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* !CONFIG_MTD_RAW_NAND */
/* USB Device Firmware Update support */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 26
#define MTDIDS_DEFAULT "nand0=nand.0"
#endif /* CONFIG_MTD_RAW_NAND */
/* NAND support */
/* NAND config */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* ! __CONFIG_IGEP003X_H */
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
11, 12, 13, 14, 16, 17, 18, 19, 20, \
21, 22, 23, 24, 25, 26, 27, 28, 30, \
31, 32, 33, 34, 35, 36, 37, 38, 39, \
40, 41, 42, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56 }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 13
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* NAND block size is 128 KiB. Synchronize these values with
* corresponding Device Tree entries in Linux:
* MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 26
#define NANDARGS \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
#endif
/* USB */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD22 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
+#define CFG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
+#define CFG_SYS_NAND_MASK_CLE (1 << 21)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC15
#endif
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PA22
#endif
/* USB */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif
#ifdef CONFIG_SD_BOOT
#elif CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
+#define CFG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
+#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD17
#endif
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
#endif
/* SPL */
#ifndef CONFIG_NOR_BOOT
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
#endif
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* ! __CONFIG_CHILIBOARD_H */
#include <config_distro_bootcmd.h>
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* APBH DMA is required for NAND support */
/* Ethernet */
#endif
/* NAND support */
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
/* NAND stuff */
-/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
-#define CONFIG_SYS_NAND_BASE -1
+/* used to initialize CFG_SYS_NAND_BASE_LIST which is unused */
+#define CFG_SYS_NAND_BASE -1
#endif
/* USB Configs */
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
#endif
/* USB Configs */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif
/* DFU class support */
/* Defines for SPL */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
* Flash & Environment
*/
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_ECCPOS { \
+#define CFG_SYS_NAND_CS 3
+#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_SYS_NAND_MASK_CLE 0x10
+#define CFG_SYS_NAND_MASK_ALE 0x8
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x40000
+#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
+#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_ECCPOS { \
24, 25, 26, 27, 28, \
29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 10
#endif
#ifdef CONFIG_MTD_NOR_FLASH
/*
* NAND controller
*/
-#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE SLC_NAND_BASE
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/*
* NAND chip timings
*/
/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x60000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
/* See common/spl/spl.c spl_set_header_raw_uboot() */
/* Defines for SPL */
/* NAND boot config */
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x200000
#endif /* __CONFIG_H */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* !CONFIG_MTD_RAW_NAND */
/* Parallel NOR Support */
#include "siemens-am33x-common.h"
/* NAND specific changes for etamin due to different page size */
-#undef CONFIG_SYS_NAND_ECCPOS
+#undef CFG_SYS_NAND_ECCPOS
#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
-#undef CONFIG_SYS_NAND_ECCSIZE
-#undef CONFIG_SYS_NAND_ECCBYTES
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
+#undef CFG_SYS_NAND_ECCSIZE
+#undef CFG_SYS_NAND_ECCBYTES
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 26
-#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
- CONFIG_SYS_NAND_BASE2}
+#define CFG_SYS_NAND_BASE2 (0x18000000) /* physical address */
+#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE, \
+ CFG_SYS_NAND_BASE2}
#define DDR_PLL_FREQ 303
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#endif
/* JFFS2 */
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NAND flash */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+#define CFG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CFG_SYS_NAND_MASK_CLE BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
/* SPL */
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
#endif
* NAND
*/
#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
-#define CONFIG_SYS_NAND_BASE 0xd8000000
+#define CFG_SYS_NAND_BASE 0xd8000000
#define CONFIG_MXC_NAND_HWECC
/*
/* NAND */
#ifdef CONFIG_NAND_MXS
-# define CONFIG_SYS_NAND_BASE 0x40000000
-# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+# define CFG_SYS_NAND_BASE 0x40000000
+# define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* MTD device */
#endif
/* Environment organization */
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* USB Configs */
#ifdef CONFIG_CMD_USB
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CFG_SYS_NAND_BASE 0x20000000
#endif
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CFG_SYS_NAND_BASE 0x20000000
#endif /* __IMX8MN_BSH_SMM_S2_H */
#ifdef CONFIG_NAND_MXS
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CFG_SYS_NAND_BASE 0x20000000
#endif /* CONFIG_NAND_MXS */
#endif /* __IMX8MP_RSB3720_H */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
+#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
#endif
/*
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
/* NAND Flash Definitions */
-#define CONFIG_SYS_NAND_BASE 0x68000000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x68000000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_TE | \
CSPR_MSEL_NAND | \
CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
| CSOR_NAND_ECC_DEC_EN \
| CSOR_NAND_ECC_MODE_4 \
| CSOR_NAND_RAL_3 \
| CSOR_NAND_TRHZ_40 \
| CSOR_NAND_BCTLD)
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
FTIM0_NAND_TWP(0x8) | \
FTIM0_NAND_TWCHT(0x3) | \
FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
FTIM1_NAND_TWBE(0x1e) | \
FTIM1_NAND_TRR(0x6) | \
FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
FTIM2_NAND_TREH(0x5) | \
FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */
#define CONFIG_SYS_QRIO_BASE 0x70000000
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC CS1*/
-#define CONFIG_SYS_NAND_BASE 0xfa000000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE 0xfa000000
+#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0f)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT (0x0f)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
0x00000010 | /* drive TE high */\
CSPR_MSEL_NAND | /* MSEL = NAND */\
CSPR_V) /* valid */
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \
CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \
CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \
CSOR_NAND_BCTLD) /**/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
FTIM0_NAND_TWP(0x8) | \
FTIM0_NAND_TWCHT(0x3) | \
FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
FTIM1_NAND_TWBE(0x1e) | \
FTIM1_NAND_TRR(0x6) | \
FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
FTIM2_NAND_TREH(0x5) | \
FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
/* More NAND Flash Params */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO on IFC CS2 */
#define CONFIG_SYS_QRIO_BASE 0xfb000000
#define CONFIG_NAND_ECC_BCH
#define CONFIG_NAND_KMETER1
#define NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
/*
#endif
#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE (640 << 10)
#endif
#if defined(CONFIG_TFABOOT) || \
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
#endif
/*
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#endif
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
/* GPIO */
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
/* EEPROM */
#define I2C_RETIMER_ADDR 0x18
* NAND Flash Definitions
*/
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#endif
#if defined(CONFIG_TFABOOT) || \
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_UBOOT_BASE 0x40100000
#endif
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0xe) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
FTIM2_NAND_TREH(0xa) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
/*
#define CONFIG_SYS_CPLD_FTIM3 0x0
/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
#define QIXIS_BASE_PHYS_EARLY 0xC000000
-#define CONFIG_SYS_NAND_BASE 0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
+#define CFG_SYS_NAND_BASE 0x530000000ULL
+#define CFG_SYS_NAND_BASE_PHYS 0x30000000
/* MC firmware */
#endif
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
#else
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
#endif
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
#define QIXIS_SDID_MASK 0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
-#define CONFIG_SYS_NAND_BASE 0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
+#define CFG_SYS_NAND_BASE 0x530000000ULL
+#define CFG_SYS_NAND_BASE_PHYS 0x30000000
/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
" 0x580e00000 \0"
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_U_BOOT_DST 0x80400000
+#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
#endif
#include <asm/arch/soc.h>
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
#endif
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PB(128)) /* Pages Per Block 128*/
/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
FTIM0_NAND_TWP(0x30) | \
FTIM0_NAND_TWCHT(0x0e) | \
FTIM0_NAND_TWH(0x14))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
FTIM1_NAND_TWBE(0xab) | \
FTIM1_NAND_TRR(0x1c) | \
FTIM1_NAND_TRP(0x30))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
FTIM2_NAND_TREH(0x14) | \
FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3 0x0
+#define CFG_SYS_NAND_FTIM3 0x0
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
+#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
* NAND
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
+#define CFG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_LARGEPAGE
+#define CFG_SYS_NAND_LARGEPAGE
#define CONFIG_MXC_NAND_HWECC
#endif
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
-# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
+# define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
+# define CFG_SYS_NAND_MASK_ALE (1 << 21)
+# define CFG_SYS_NAND_MASK_CLE (1 << 22)
+# define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
+# define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
#endif
/* hw-controller addresses */
#define CFG_SYS_FSL_USDHC_NUM 2
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */
*/
#ifdef CONFIG_NAND_MXS
/* NAND stuff */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */
#endif
/* NAND */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CFG_SYS_NAND_BASE 0x60000000
#endif
/* OCOTP */
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 3
/* NAND: SPL falcon mode configs */
#endif /* CONFIG_MTD_RAW_NAND */
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 3
#endif /* CONFIG_MTD_RAW_NAND */
#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
/* NAND config */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* __IGEP00X0_H */
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND devices */
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
13, 14, 16, 17, 18, 19, 20, 21, 22, \
23, 24, 25, 26, 27, 28, 30, 31, 32, \
33, 34, 35, 36, 37, 38, 39, 40, 41, \
42, 44, 45, 46, 47, 48, 49, 50, 51, \
52, 53, 54, 55, 56}
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 13
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 13
#endif
/* Environment information */
* Flash & Environment
*/
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
+#define CFG_SYS_NAND_CS 3
+#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_SYS_NAND_MASK_CLE 0x10
+#define CFG_SYS_NAND_MASK_ALE 0x8
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_ECCPOS { \
+#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
+#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
+#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_ECCPOS { \
6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 10
#endif
/*
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
+#define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
+#define CFG_SYS_NAND_U_BOOT_START (0x11000000)
#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
+#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST 0xf8f80000
+#define CFG_SYS_NAND_U_BOOT_START 0xf8f80000
#endif /* not CONFIG_TPL_BUILD */
#endif
/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
+#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
+#define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#else
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
+#define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
#endif /* !CONFIG_MTD_RAW_NAND */
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* NAND flash */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD22 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
+#define CFG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
+#define CFG_SYS_NAND_MASK_CLE (1 << 21)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
/* NOR flash */
#define PHYS_FLASH_1 0x10000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
+#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
#endif
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+#define CFG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3
+#define CFG_SYS_NAND_MASK_CLE BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD3
#endif
#ifdef CONFIG_NAND_BOOT
#ifdef CONFIG_SD_BOOT
#elif CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
/* nand driver parameters */
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
- #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
- #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+ #define CFG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
+ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
#endif /* __PRESIDIO_ASIC_H */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
-#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CFG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_MASK_ALE BIT(21)
+#define CFG_SYS_NAND_MASK_CLE BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
#endif
#endif
/* NAND Flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+#define CFG_SYS_NAND_MASK_ALE BIT(21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
+#define CFG_SYS_NAND_MASK_CLE BIT(22)
#endif
#endif /* __CONFIG_H */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CFG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#endif
/* SPL */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CFG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#endif
/* SPL */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x80000000
+#define CFG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#endif
/* SPL */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x80000000
+#define CFG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#endif
/* SPL */
/* Defines for SPL */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
*/
-#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
+#define CFG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
/* CS0 */
#endif
*/
/* NAND flash settings */
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
/* serial console */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
/* Defines for SPL */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
/* Mem test settings */
/* NAND Flash */
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
+#define CFG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
/* UARTs/Serial console */
* NAND Support
*/
#ifdef CONFIG_NAND_DENALI
-#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
-#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
+#define CFG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
+#define CFG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
/*
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
-#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
+#define CFG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
#endif
#if defined(CONFIG_BOARD_TAURUS)
/* Defines for SPL */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
* GPMC NAND block. We support 1 device and the physical address to
* access CS0 at is 0x8000000.
*/
-#define CONFIG_SYS_NAND_BASE 0x8000000
+#define CFG_SYS_NAND_BASE 0x8000000
/* NAND: SPL related configs */
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 14
/* SPL */
/* Defines for SPL */
/* General parts of the framework, required. */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
#endif /* !CONFIG_NOR_BOOT */
/* EEPROM definitions */
/* NAND Configuration */
-#define CONFIG_SYS_NAND_MASK_CLE 0x4000
-#define CONFIG_SYS_NAND_MASK_ALE 0x2000
-#define CONFIG_SYS_NAND_CS 2
+#define CFG_SYS_NAND_MASK_CLE 0x4000
+#define CFG_SYS_NAND_MASK_ALE 0x2000
+#define CFG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
+#define CFG_SYS_NAND_LARGEPAGE
+#define CFG_SYS_NAND_BASE_LIST { 0x30000000, }
#define DFU_ALT_INFO_MMC \
"dfu_alt_info_mmc=" \
* access CS0 at is 0x8000000.
*/
#ifdef CONFIG_MTD_RAW_NAND
-#ifndef CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_BASE 0x8000000
+#ifndef CFG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x8000000
#endif
#endif
/* SPL */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_BASE 0x30000000
+#define CFG_SYS_NAND_BASE 0x30000000
#endif
/* Now bring in the rest of the common code. */
#define CONFIG_SYS_TIMER_RATE 1000000
#endif
-#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
-#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
+#define CFG_SYS_NAND_REGS_BASE 0x68100000
+#define CFG_SYS_NAND_DATA_BASE 0x68000000
/*
* Network Configuration
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
+#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
#endif
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
/* NAND support */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
+#define CFG_SYS_NAND_BASE NFC_BASE_ADDR
/* Dynamic MTD partition support */
#endif
/* driver configuration */
#define CONFIG_SYS_MAX_NAND_CHIPS 1
-#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
+#define CFG_SYS_NAND_BASE MLC_NAND_BASE
/*
* GPIO
/* SPL will use serial */
/* SPL will load U-Boot from NAND offset 0x40000 */
/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
/*
* Include SoC specific configuration
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