pci: pci-uclass: Add multi entry support for memory regions

Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 1d8956abbebab52d700d89c9a269fc262b259815..9f45c48e4e0c5f561314ad314db4bd0a23c1705e 100644 (file)
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -666,8 +666,9 @@
                bus-range = <0x00 0xff>;
                #address-cells = <3>;
                #size-cells = <2>;
-               ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
-                               0x01000000 0 0x40000000 0x40000000 0 0x2000>;
+               ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
+                         0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
+                         0x01000000 0 0x40000000 0x40000000 0 0x2000>;
                sandbox,dev-info = <0x08 0x00 0x1234 0x5678
                                    0x0c 0x00 0x1234 0x5678
                                    0x10 0x00 0x1234 0x5678>;

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 41de434d1ab5d715602d55f35d49f0f967bba642..18bfdc0162d19da74171e8f3a9b77484c425ff3d 100644 (file)
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -181,6 +181,7 @@ CONFIG_NVME=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y

diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 46e9dff9240a23eac98d435f263fb475f066a4e4..dd93167e1b70944e27f1464a18f6fd19b4f759cf 100644 (file)
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -136,6 +136,7 @@ CONFIG_NVME=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 5e0a39396bb019d596de0baefd3e571dd340a0f0..1c47a21101d98cab201c7cb14fe5494ca33ea696 100644 (file)
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -43,6 +43,16 @@ config PCI_PNP
        help
          Enable PCI memory and I/O space resource allocation and assignment.
 
+config PCI_REGION_MULTI_ENTRY
+       bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
+       depends on PCI || DM_PCI
+       default n
+       help
+         Enable PCI memory regions to be of multiple entry. Multiple entry
+         here refers to allow more than one count of address ranges for MEMORY
+         region type. This helps to add support for SoC's like OcteonTX/TX2
+         where every peripheral is on the PCI bus.
+
 config PCIE_ECAM_GENERIC
        bool "Generic ECAM-based PCI host controller support"
        default n

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index cf1bbccbba331516a4922ef063d971b2b293b758..19ea3ae9c1e83c07ad89d7f60632157f61a4a446 100644 (file)
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -936,10 +936,13 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
                }
 
                pos = -1;
-               for (i = 0; i < hose->region_count; i++) {
-                       if (hose->regions[i].flags == type)
-                               pos = i;
+               if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
+                       for (i = 0; i < hose->region_count; i++) {
+                               if (hose->regions[i].flags == type)
+                                       pos = i;
+                       }
                }
+
                if (pos == -1)
                        pos = hose->region_count++;
                debug(" - type=%d, pos=%d\n", type, pos);

diff --git a/test/dm/pci.c b/test/dm/pci.c
index fd66ed7899f9a0d1fa3fb759965d3c4ffdb8b9f6..76490befdf50d0c0a61e3a8f2ec6d16e99b13993 100644 (file)
--- a/test/dm/pci.c
+++ b/test/dm/pci.c
@@ -354,3 +354,25 @@ static int dm_test_pci_on_bus(struct unit_test_state *uts)
        return 0;
 }
 DM_TEST(dm_test_pci_on_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/*
+ * Test support for multiple memory regions enabled via
+ * CONFIG_PCI_REGION_MULTI_ENTRY. When this feature is not enabled,
+ * only the last region of one type is stored. In this test-case,
+ * we have 2 memory regions, the first at 0x3000.0000 and the 2nd
+ * at 0x3100.0000. A correct test results now in BAR1 located at
+ * 0x3000.0000.
+ */
+static int dm_test_pci_region_multi(struct unit_test_state *uts)
+{
+       struct udevice *dev;
+       ulong mem_addr;
+
+       /* Test memory BAR1 on bus#1 */
+       ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev));
+       mem_addr = dm_pci_read_bar32(dev, 1);
+       ut_asserteq(mem_addr, 0x30000000);
+
+       return 0;
+}
+DM_TEST(dm_test_pci_region_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);