development platform that supports the QorIQ LS1046A
Layerscape Architecture processor.
+config TARGET_SL28
+ bool "Support sl28"
+ select ARCH_LS1028A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
+ select BINMAN
+ help
+ Support for Kontron SMARC-sAL28 board.
+
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
source "board/hisilicon/hikey960/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
+source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
fsl-ls1012a-2g5rdb.dtb \
fsl-ls1012a-frdm.dtb \
fsl-ls1012a-frwy.dtb
+dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
+ fsl-ls1028a-kontron-sl28-var3.dtb \
+ fsl-ls1028a-kontron-sl28-var4.dtb \
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <config.h>
+
+/ {
+ aliases {
+ mmc0 = &esdhc0;
+ mmc1 = &esdhc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c3;
+ i2c2 = &i2c4;
+ rtc0 = &rtc;
+ ethernet0 = &enetc0;
+ ethernet1 = &enetc1;
+ ethernet2 = &enetc2;
+ ethernet3 = &enetc6;
+ };
+
+ binman {
+ filename = "u-boot.rom";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ };
+
+ fit {
+ offset = <CONFIG_SPL_PAD_TO>;
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ description = "U-Boot";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ u-boot-nodtb {
+ };
+ };
+
+ fdt-1 {
+ description = "fsl-ls1028a-kontron-sl28";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ blob {
+ filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28.dtb";
+ };
+ };
+
+ fdt-2 {
+ description = "fsl-ls1028a-kontron-sl28-var3";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ blob {
+ filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dtb";
+ };
+ };
+
+ fdt-3 {
+ description = "fsl-ls1028a-kontron-sl28-var4";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ blob {
+ filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-1";
+
+ conf-1 {
+ description = "fsl-ls1028a-kontron-sl28";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-1";
+ };
+
+ conf-2 {
+ description = "fsl-ls1028a-kontron-sl28-var3";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-2";
+ };
+
+ conf-3 {
+ description = "fsl-ls1028a-kontron-sl28-var4";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-3";
+ };
+ };
+ };
+ };
+};
+
+&i2c0 {
+ rtc: rtc@32 {
+ };
+};
+
+&fspi {
+ u-boot,dm-pre-reloc;
+ flash@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&dspi2 {
+ u-boot,dm-pre-reloc;
+};
+
+&esdhc0 {
+ u-boot,dm-pre-reloc;
+};
+
+&esdhc1 {
+ u-boot,dm-pre-reloc;
+};
+
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&sysclk {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the Kontron SMARC-sAL28 board.
+ *
+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ *
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-kontron-sl28.dts"
+
+/ {
+ model = "Kontron SMARC-sAL28 (Single PHY)";
+ compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the Kontron SMARC-sAL28 board.
+ *
+ * This is for the network variant 4 which has two ethernet ports. It
+ * extends the base and provides one more port connected via RGMII.
+ *
+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ *
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-kontron-sl28.dts"
+#include <dt-bindings/net/qca-ar803x.h>
+
+/ {
+ model = "Kontron SMARC-sAL28 (Dual PHY)";
+ compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
+};
+
+&enetc1 {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&mdio0 {
+ phy1: ethernet-phy@4 {
+ reg = <0x4>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+
+ qca,clk-out-frequency = <125000000>;
+ qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+
+ vddio-supply = <&vddh>;
+
+ vddio: vddio-regulator {
+ regulator-name = "VDDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddh: vddh-regulator {
+ regulator-name = "VDDH";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the Kontron SMARC-sAL28 board.
+ *
+ * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ *
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a.dtsi"
+
+/ {
+ model = "Kontron SMARC-sAL28";
+ compatible = "kontron,sl28", "fsl,ls1028a";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &lpuart1;
+ spi0 = &fspi;
+ spi1 = &dspi2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&dspi2 {
+ status = "okay";
+};
+
+&enetc0 {
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&enetc2 {
+ status = "disabled";
+};
+
+&enetc6 {
+ status = "disabled";
+};
+
+&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ status = "okay";
+};
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&fspi {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ spi-max-frequency = <133000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
+ spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
+ spi-tx-bus-width = <1>; /* 1 SPI Tx line */
+
+ partition@0 {
+ reg = <0x000000 0x010000>;
+ label = "rcw";
+ read-only;
+ };
+
+ partition@10000 {
+ reg = <0x010000 0x0f0000>;
+ label = "failsafe bootloader";
+ read-only;
+ };
+
+ partition@100000 {
+ reg = <0x100000 0x040000>;
+ label = "failsafe DP firmware";
+ read-only;
+ };
+
+ partition@140000 {
+ reg = <0x140000 0x0a0000>;
+ label = "failsafe trusted firmware";
+ read-only;
+ };
+
+ partition@1e0000 {
+ reg = <0x1e0000 0x020000>;
+ label = "reserved";
+ read-only;
+ };
+
+ partition@200000 {
+ reg = <0x200000 0x010000>;
+ label = "configuration store";
+ };
+
+ partition@210000 {
+ reg = <0x210000 0x0f0000>;
+ label = "bootloader";
+ };
+
+ partition@300000 {
+ reg = <0x300000 0x040000>;
+ label = "DP firmware";
+ };
+
+ partition@340000 {
+ reg = <0x340000 0x0a0000>;
+ label = "trusted firmware";
+ };
+
+ partition@3e0000 {
+ reg = <0x3e0000 0x020000>;
+ label = "bootloader environment";
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ rtc@32 {
+ compatible = "microcrystal,rv8803";
+ reg = <0x32>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&lpuart1 {
+ status = "okay";
+};
+
+&mdio0 {
+ status = "okay";
+ phy0: ethernet-phy@5 {
+ reg = <0x5>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
--- /dev/null
+if TARGET_SL28
+
+config SYS_BOARD
+ default "sl28"
+
+config SYS_VENDOR
+ default "kontron"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "kontron_sl28"
+
+config SYS_TEXT_BASE
+ default 0x96000000
+
+endif
--- /dev/null
+Kontron SMARC-sAL28 board
+M: Michael Walle <michael@walle.cc>
+S: Maintained
+F: arch/arm/dts/fsl-ls1028a-kontron-sl28-*
+F: board/kontron/sl28/
+F: configs/kontron_sl28_defconfig
+F: include/configs/kontron_sl28.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+ifndef CONFIG_SPL_BUILD
+obj-y += sl28.o
+endif
+
+obj-y += common.o ddr.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+
+int board_early_init_f(void)
+{
+ fsl_lsch3_early_init_f();
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DCFG_GPPORCR1 0x20
+
+#define GPPORCR1_MEM_MASK (0x7 << 5)
+#define GPPORCR1_MEM_512MB_CS0 (0x0 << 5)
+#define GPPORCR1_MEM_1GB_CS0 (0x1 << 5)
+#define GPPORCR1_MEM_2GB_CS0 (0x2 << 5)
+#define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5)
+#define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5)
+
+static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
+ .cs[0].bnds = 0x0000007f,
+ .cs[0].config = 0x80044402,
+ .cs[1].bnds = 0x008000ff,
+ .cs[1].config = 0x80004402,
+
+ .timing_cfg_0 = 0x9011010c,
+ .timing_cfg_3 = 0x010c1000,
+ .timing_cfg_1 = 0xbcb48c66,
+ .timing_cfg_2 = 0x0fc0d118,
+ .ddr_sdram_cfg = 0xe70c000c,
+ .ddr_sdram_cfg_2 = 0x24401111,
+ .ddr_sdram_mode = 0x00441c70,
+ .ddr_sdram_mode_3 = 0x00001c70,
+ .ddr_sdram_mode_5 = 0x00001c70,
+ .ddr_sdram_mode_7 = 0x00001c70,
+ .ddr_sdram_mode_2 = 0x00180000,
+ .ddr_sdram_mode_4 = 0x00180000,
+ .ddr_sdram_mode_6 = 0x00180000,
+ .ddr_sdram_mode_8 = 0x00180000,
+
+ .ddr_sdram_interval = 0x0c30030c,
+ .ddr_data_init = 0xdeadbeef,
+
+ .ddr_sdram_clk_cntl = 0x02400000,
+
+ .timing_cfg_4 = 0x00000001,
+ .timing_cfg_5 = 0x04401400,
+
+ .ddr_zq_cntl = 0x89080600,
+ .ddr_wrlvl_cntl = 0x8675f606,
+ .ddr_wrlvl_cntl_2 = 0x04080700,
+ .ddr_wrlvl_cntl_3 = 0x00000009,
+
+ .ddr_cdr1 = 0x80040000,
+ .ddr_cdr2 = 0x0000bc01,
+};
+
+int fsl_initdram(void)
+{
+ u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1);
+ phys_size_t dram_size;
+
+ switch (gpporcr1 & GPPORCR1_MEM_MASK) {
+ case GPPORCR1_MEM_2GB_CS0:
+ dram_size = 0x80000000;
+ ddr_cfg_regs.cs[1].bnds = 0;
+ ddr_cfg_regs.cs[1].config = 0;
+ ddr_cfg_regs.cs[1].config_2 = 0;
+ break;
+ case GPPORCR1_MEM_4GB_CS0_1:
+ dram_size = 0x100000000ULL;
+ break;
+ case GPPORCR1_MEM_512MB_CS0:
+ dram_size = 0x20000000;
+ fallthrough; /* for now */
+ case GPPORCR1_MEM_1GB_CS0:
+ dram_size = 0x40000000;
+ fallthrough; /* for now */
+ case GPPORCR1_MEM_4GB_CS0_2:
+ dram_size = 0x100000000ULL;
+ fallthrough; /* for now */
+ case GPPORCR1_MEM_8GB_CS0_1:
+ case GPPORCR1_MEM_8GB_CS0_1_2_3:
+ dram_size = 0x200000000ULL;
+ fallthrough; /* for now */
+ default:
+ panic("Unsupported memory configuration (%08x)\n",
+ gpporcr1 & GPPORCR1_MEM_MASK);
+ break;
+ }
+
+ if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+ gd->ram_size = dram_size;
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <env_internal.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ if (CONFIG_IS_ENABLED(FSL_CAAM))
+ sec_init();
+
+ return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int checkboard(void)
+{
+ printf("EL: %d\n", current_el());
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+ int nbanks = CONFIG_NR_DRAM_BANKS;
+ int i;
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the two GPP DDR banks */
+ for (i = 0; i < nbanks; i++) {
+ base[i] = gd->bd->bi_dram[i].start;
+ size[i] = gd->bd->bi_dram[i].size;
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, nbanks);
+
+ fdt_fixup_icid(blob);
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/spl.h>
+
+#define DCFG_RCWSR25 0x160
+#define GPINFO_HW_VARIANT_MASK 0xff
+
+int sl28_variant(void)
+{
+ return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ int variant = sl28_variant();
+
+ switch (variant) {
+ case 3:
+ return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
+ case 4:
+ return strcmp(name, "fsl-ls1028a-kontron-sl28-var4");
+ default:
+ return strcmp(name, "fsl-ls1028a-kontron-sl28");
+ }
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_SL28=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x3e0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x18010000
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SIZE_LIMIT=0x20000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x3f0000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28"
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_PCI_INIT_R=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RNG=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST=""
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_FSL_CAAM=y
+CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_FSL_ENETC=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_DM_RNG=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
+CONFIG_OF_LIBFDT_OVERLAY=y
freescale/index
google/index
intel/index
+ kontron/index
renesas/index
rockchip/index
sifive/index
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron
+=======
+
+.. toctree::
+ :maxdepth: 2
+
+ sl28
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Summary
+=======
+
+The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72
+processor module with an on-chip 6-port TSN switch and a 3D GPU.
+
+
+Quickstart
+==========
+
+Compile U-Boot
+--------------
+
+Configure and compile the binary::
+
+ $ make kontron_sl28_defconfig
+ $ CROSS_COMPILE=aarch64-linux-gnu make
+
+Copy u-boot.rom to a TFTP server.
+
+Install the bootloader on the board
+-----------------------------------
+
+Please note, this bootloader doesn't support the builtin watchdog (yet),
+therefore you have to disable it, see below. Otherwise you'll end up in
+the failsafe bootloader on every reset::
+
+ > tftp path/to/u-boot.rom
+ > sf probe 0
+ > sf update $fileaddr 0x210000 $filesize
+
+The board is fully failsafe, you can't break anything. But because you've
+disabled the builtin watchdog you might have to manually enter failsafe
+mode by asserting the ``FORCE_RECOV#`` line during board reset.
+
+Disable the builtin watchdog
+----------------------------
+
+- boot into the failsafe bootloader, either by asserting the
+ ``FORCE_RECOV#`` line or if you still have the original bootloader
+ installed you can use the command::
+
+ > wdt dev cpld_watchdog@4a; wdt expire 1
+
+- in the failsafe bootloader use the "sl28 nvm" command to disable
+ the automatic start of the builtin watchdog::
+
+ > sl28 nvm 0008
+
+- power-cycle the board
+
+
+Useful I2C tricks
+=================
+
+The board has a board management controller which is not supported in
+u-boot (yet). But you can use the i2c command to access it.
+
+- reset into failsafe bootloader::
+
+ > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42
+
+- read board management controller version::
+
+ > i2c md 4a 3.1 1
+
+
+Non-volatile Board Configuration Bits
+=====================================
+
+The board has 16 configuration bits which are stored in the CPLD and are
+non-volatile. These can be changed by the `sl28 nvm` command.
+
+=== ===============================================================
+Bit Description
+=== ===============================================================
+ 0 Power-on inhibit
+ 1 Enable eMMC boot
+ 2 Enable watchdog by default
+ 3 Disable failsafe watchdog by default
+ 4 Clock generator selection bit 0
+ 5 Clock generator selection bit 1
+ 6 Disable CPU SerDes clock #2 and PCIe-A clock output
+ 7 Disable PCIe-B and PCIe-C clock output
+ 8 Keep onboard PHYs in reset
+ 9 Keep USB hub in reset
+ 10 Keep eDP-to-LVDS converter in reset
+ 11 Enable I2C stuck recovery on I2C PM and I2C GP busses
+ 12 Enable automatic onboard PHY H/W reset
+ 13 reserved
+ 14 Used by the RCW to determine boot source
+ 15 Used by the RCW to determine boot source
+=== ===============================================================
+
+Please note, that if the board is in failsafe mode, the bits will have the
+factory defaults, ie. all bits are off.
+
+Power-On Inhibit
+----------------
+
+If this is set, the board doesn't automatically turn on when power is
+applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or
+use any other wake-up source such as RTC alarm or Wake-on-LAN.
+
+eMMC Boot
+---------
+
+If this is set, the RCW will be fetched from the on-board eMMC at offset
+1MiB. For further details, have a look at the `Reset Configuration Word
+Documentation`_.
+
+Watchdog
+--------
+
+By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and
+3, the user can change its mode or disable it altogether.
+
+===== ===== ===============================
+Bit 2 Bit 3 Description
+===== ===== ===============================
+ 0 0 Watchdog enabled, failsafe mode
+ 0 1 Watchdog disabled
+ 1 0 Watchdog enabled, failsafe mode
+ 1 1 Watchdog enabled, normal mode
+===== ===== ===============================
+
+Clock Generator Select
+----------------------
+
+The board is prepared to supply different SerDes clock speeds. But for now,
+only setting 0 is supported, otherwise the CPU will hang because the PLL
+will not lock.
+
+Clock Output Disable And Keep Devices In Reset
+----------------------------------------------
+
+To safe power, the user might disable different devices and clock output of
+the board. It is not supported to disable the "CPU SerDes clock #2" for
+now, otherwise the CPU will hang because the PLL will not lock.
+
+Automatic reset of the onboard PHYs
+-----------------------------------
+
+By default, there is no hardware reset of the onboard PHY. This is because
+for Wake-on-LAN, some registers have to retain their values. If you don't
+use the WOL feature and a soft reset of the PHY is not enough you can
+enable the hardware reset. The onboard PHY hardware reset follows the
+power-on reset.
+
+
+Further documentation
+=====================
+
+- `Vendor Documentation`_
+- `Reset Configuration Word Documentation`_
+
+.. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md
+.. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __SL28_H
+#define __SL28_H
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+/* we don't use hwconfig but this has to be defined.. */
+#define HWCONFIG_BUFFER_SIZE 256
+
+/* we don't have secure memory unless we have a BL31 */
+#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#undef CONFIG_SYS_MEM_RESERVE_SECURE
+#endif
+
+/* DDR */
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
+
+/* early stack pointer */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0)
+
+/* memtest command */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/* SMP */
+#define CPU_RELEASE_ADDR secondary_boot_addr
+
+/* generic timer */
+#define COUNTER_FREQUENCY 25000000
+
+/* size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* early heap for SPL DM */
+#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE
+
+/* serial port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* ethernet */
+#define CONFIG_SYS_RX_ETH_BUFFER 8
+
+/* SPL */
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SPL_MAX_SIZE 0x20000
+#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
+
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
+#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
+
+/* environment */
+/* see include/configs/ti_armv7_common.h */
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "kernel_addr_r=0x82000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "bootm_size=0x10000000\0" \
+ "pxefile_addr_r=0x80100000\0" \
+ "scriptaddr=0x80000000\0" \
+ "ramdisk_addr_r=0x88080000\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(NVME, nvme, 0) \
+ func(USB, usb, 0) \
+ func(DHCP, dhcp, 0) \
+ func(PXE, pxe, 0)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "env_addr=0x203e0004\0" \
+ "envload=env import -d -b ${env_addr}\0" \
+ "install_rcw=source 20200000\0" \
+ "fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV
+
+#endif /* __SL28_H */
projects / u-boot.git / commitdiff