ARM: Factor out reusable psci_cpu_entry

_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.

As with psci_disable_smp, also the enabling is designed to be overloaded
in cased SMP is not controlled via ACTLR.

CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index cdcdccdc47f16d55be9ccaedda675b73c697df4c..7d89b43983e50412ee212b06fe00f40bca10f8b0 100644 (file)
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -165,6 +165,15 @@ ENTRY(psci_disable_smp)
 ENDPROC(psci_disable_smp)
 .weak psci_disable_smp
 
+ENTRY(psci_enable_smp)
+       mrc     p15, 0, r0, c1, c0, 1           @ ACTLR
+       orr     r0, r0, #(1 << 6)               @ Set SMP bit
+       mcr     p15, 0, r0, c1, c0, 1           @ ACTLR
+       isb
+       bx      lr
+ENDPROC(psci_enable_smp)
+.weak psci_enable_smp
+
 ENTRY(psci_cpu_off_common)
        push    {lr}
 
@@ -184,4 +193,18 @@ ENTRY(psci_cpu_off_common)
        bx      lr
 ENDPROC(psci_cpu_off_common)
 
+ENTRY(psci_cpu_entry)
+       bl      psci_enable_smp
+
+       bl      _nonsec_init
+
+       adr     r0, _psci_target_pc
+       ldr     r0, [r0]
+       b       _do_nonsec_entry
+ENDPROC(psci_cpu_entry)
+
+.globl _psci_target_pc
+_psci_target_pc:
+       .word   0
+
        .popsection

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 05d047b2a5c07b7ea86f2c2d1f111ab14c0da8e5..90dcff172ca2b38ed2c978b871264c0e28b9cf63 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -139,7 +139,7 @@ out:        mcr     p15, 0, r7, c1, c1, 0
        @ r2 = target PC
 .globl psci_cpu_on
 psci_cpu_on:
-       adr     r0, _target_pc
+       ldr     r0, =_psci_target_pc
        str     r2, [r0]
        dsb
 
@@ -151,7 +151,7 @@ psci_cpu_on:
        mov     r4, #1
        lsl     r4, r4, r1
 
-       adr     r6, _sunxi_cpu_entry
+       ldr     r6, =psci_cpu_entry
        str     r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
 
        @ Assert reset on target CPU
@@ -197,22 +197,6 @@ psci_cpu_on:
        mov     r0, #ARM_PSCI_RET_SUCCESS       @ Return PSCI_RET_SUCCESS
        mov     pc, lr
 
-_target_pc:
-       .word   0
-
-_sunxi_cpu_entry:
-       @ Set SMP bit
-       mrc     p15, 0, r0, c1, c0, 1
-       orr     r0, r0, #0x40
-       mcr     p15, 0, r0, c1, c0, 1
-       isb
-
-       bl      _nonsec_init
-
-       adr     r0, _target_pc
-       ldr     r0, [r0]
-       b       _do_nonsec_entry
-
 .globl psci_cpu_off
 psci_cpu_off:
        bl      psci_cpu_off_common