powerpc/t4240: update serdes table

Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3
support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes
A/B/C/D are not available, updated the serdes table accordingly with
some minor fix.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 74c4c81887c2b66507aef51ea2d761dd2a056e71..7b43b282bb6f5014c6f13933777aeb56bcf5d993 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -214,8 +214,8 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
        {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
        {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
        {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
-       {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
-       {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+       {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+       {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
        {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
        {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -266,37 +266,30 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
 #elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
 static const struct serdes_config serdes1_cfg_tbl[] = {
        /* SerDes 1 */
-       {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
-               XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+       {1, {NONE, NONE, NONE, NONE,
                XAUI_FM1_MAC10, XAUI_FM1_MAC10,
                XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
-       {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
-               HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+       {2, {NONE, NONE, NONE, NONE,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-       {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
-               HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+       {4, {NONE, NONE, NONE, NONE,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-       {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+       {27, {NONE, NONE, NONE, NONE,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-       {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+       {28, {NONE, NONE, NONE, NONE,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-       {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+       {35, {NONE, NONE, NONE, NONE,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-       {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+       {36, {NONE, NONE, NONE, NONE,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-       {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+       {37, {NONE, NONE, NONE, NONE,
                NONE, NONE, QSGMII_FM1_A, NONE} },
-       {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+       {38, {NONE, NONE, NONE, NONE,
                NONE, NONE, QSGMII_FM1_A, NONE} },
        {}
 };
@@ -363,45 +356,45 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {37, {NONE, NONE, QSGMII_FM2_B, NONE,
-               NONE, QSGMII_FM1_A, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {38, {NONE, NONE, QSGMII_FM2_B, NONE,
-               NONE, QSGMII_FM1_A, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, QSGMII_FM1_A, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, QSGMII_FM1_A, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, QSGMII_FM1_A, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, QSGMII_FM1_A, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, QSGMII_FM1_A, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, QSGMII_FM1_A, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               NONE, NONE, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               NONE, NONE, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, NONE, NONE} },
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {55, {NONE, XFI_FM1_MAC10,
                XFI_FM2_MAC10, NONE,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -424,51 +417,51 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
        {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
        {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
        {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
-       {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
-       {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
+       {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+       {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
        {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
        {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
-       {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+       {11, {NONE, NONE, NONE, NONE,
                PCIE2, PCIE2, PCIE2, PCIE2} },
-       {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+       {12, {NONE, NONE, NONE, NONE,
                PCIE2, PCIE2, PCIE2, PCIE2} },
        {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                PCIE2, PCIE2, PCIE2, PCIE2} },
        {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                PCIE2, PCIE2, PCIE2, PCIE2} },
-       {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+       {15, {NONE, NONE, NONE, NONE,
                SRIO1, SRIO1, SRIO1, SRIO1} },
-       {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+       {16, {NONE, NONE, NONE, NONE,
                SRIO1, SRIO1, SRIO1, SRIO1} },
-       {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+       {17, {NONE, NONE, NONE, NONE,
                SRIO1, SRIO1, SRIO1, SRIO1} },
        {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1} },
        {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1} },
        {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
-                       NONE, NONE, NONE, NONE} },
+               SRIO1, SRIO1, SRIO1, SRIO1} },
        {}
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
        /* SerDes 4 */
-       {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
-       {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
-       {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
-       {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
-       {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
-       {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
-       {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
-       {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
+       {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
+       {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
+       {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
+       {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
+       {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
+       {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
+       {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+       {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+       {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+       {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+       {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
        {}
 }
 ;