x86: ivybridge: Set up the LPC device using driver model

Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index c000aca856a8e1c61406c43d405c2b7188dbfdcb..72f2ed4d712c929210450ff6d5383eaed899cbc5 100644 (file)
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -65,6 +65,9 @@ static int bd82x6x_probe(struct udevice *dev)
        int sata_node, gma_node;
        int ret;
 
+       if (!(gd->flags & GD_FLG_RELOC))
+               return 0;
+
        hose = pci_bus_to_hose(0);
        lpc_enable(PCH_LPC_DEV);
        lpc_init(hose, PCH_LPC_DEV);

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 343bfb4e98e264a7e5fa91f7e9f58c89427f73f3..6ffc843a86b7420cd64526e0e6a1ba636b5a08cd 100644 (file)
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -126,7 +126,7 @@ int arch_cpu_init_dm(void)
 {
        const void *blob = gd->fdt_blob;
        struct pci_controller *hose;
-       struct udevice *bus;
+       struct udevice *bus, *dev;
        int node;
        int ret;
 
@@ -141,6 +141,10 @@ int arch_cpu_init_dm(void)
        /* TODO(sjg@chromium.org): Get rid of gd->hose */
        gd->hose = hose;
 
+       ret = uclass_first_device(UCLASS_LPC, &dev);
+       if (!dev)
+               return -ENODEV;
+
        node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
        if (node < 0)
                return -ENOENT;

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index af5d4a89089bad99778d5aef6799af6781143e86..51a407379adb222741e1246b2f9498946771ad4a 100644 (file)
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -559,6 +559,11 @@ void lpc_enable(pci_dev_t dev)
        setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
 }
 
+static int bd82x6x_lpc_probe(struct udevice *dev)
+{
+       return 0;
+}
+
 static const struct udevice_id bd82x6x_lpc_ids[] = {
        { .compatible = "intel,bd82x6x-lpc" },
        { }
@@ -568,4 +573,5 @@ U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
        .name           = "lpc",
        .id             = UCLASS_LPC,
        .of_match       = bd82x6x_lpc_ids,
+       .probe          = bd82x6x_lpc_probe,
 };

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index a5c5dc126ca238d8fc0f0ee48092f1a74ca987a8..d5c5bfdd08299ccee1f4119572fe029b9a7e1ccb 100644 (file)
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -223,6 +223,7 @@
                                compatible = "intel,bd82x6x-lpc";
                                #address-cells = <1>;
                                #size-cells = <0>;
+                               u-boot,dm-pre-reloc;
                                cros-ec@200 {
                                        compatible = "google,cros-ec";
                                        reg = <0x204 1 0x200 1 0x880 0x80>;