fsl_esdhc: Add function to reset the eSDHC controller

To support multiple block read command we must set abort or use auto
CMD12.  If we booted from eSDHC controller neither of these are used
and thus we need to reset the controller to allow multiple block read
to function.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 85354e893a4483ada568967b997d94f3105e6185..999b58103a250508165a68d6529679d37a426f7b 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -344,6 +344,20 @@ static int esdhc_init(struct mmc *mmc)
        return ret;
 }
 
+static void esdhc_reset(struct fsl_esdhc *regs)
+{
+       unsigned long timeout = 100; /* wait max 100 ms */
+
+       /* reset the controller */
+       esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
+
+       /* hardware clears the bit when it is done */
+       while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
+               udelay(1000);
+       if (!timeout)
+               printf("MMC/SD: Reset never completed.\n");
+}
+
 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 {
        struct fsl_esdhc *regs;
@@ -358,6 +372,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
        sprintf(mmc->name, "FSL_ESDHC");
        regs = (struct fsl_esdhc *)cfg->esdhc_base;
 
+       /* First reset the eSDHC controller */
+       esdhc_reset(regs);
+
        mmc->priv = cfg;
        mmc->send_cmd = esdhc_send_cmd;
        mmc->set_ios = esdhc_set_ios;

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 57a08cd4c55a8198f45e1d879d1014d74c120b27..5f020187c239caeea5412721851c999106caa470 100644 (file)
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -39,6 +39,7 @@
 #define SYSCTL_PEREN           0x00000004
 #define SYSCTL_HCKEN           0x00000002
 #define SYSCTL_IPGEN           0x00000001
+#define SYSCTL_RSTA            0x01000000
 
 #define IRQSTAT                        0x0002e030
 #define IRQSTAT_DMAE           (0x10000000)