pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N

According to the R-Car Gen3 Hardware Manual Rev.1.50, the MOD_SEL0
bit16 is set to 0 when NFALE_A and NFRB_N_A pin functions are
selected.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index 92be19a8bf3e987137871d1ded12cd1f6718c520..992910087e2f06fbcfeab5e43a486220d891b369 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -1027,7 +1027,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP10_23_20,            NFCLE),
 
        PINMUX_IPSR_GPSR(IP10_27_24,            SD0_CD),
-       PINMUX_IPSR_GPSR(IP10_27_24,            NFALE_A),
+       PINMUX_IPSR_MSEL(IP10_27_24,            NFALE_A,        SEL_NDFC_0),
        PINMUX_IPSR_GPSR(IP10_27_24,            SD3_CD),
        PINMUX_IPSR_MSEL(IP10_27_24,            RIF0_CLK_B,     SEL_DRIF0_1),
        PINMUX_IPSR_MSEL(IP10_27_24,            SCL2_B,         SEL_I2C2_1),
@@ -1036,7 +1036,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP10_27_24,            TS_SCK0),
 
        PINMUX_IPSR_GPSR(IP10_31_28,            SD0_WP),
-       PINMUX_IPSR_GPSR(IP10_31_28,            NFRB_N_A),
+       PINMUX_IPSR_MSEL(IP10_31_28,            NFRB_N_A,       SEL_NDFC_0),
        PINMUX_IPSR_GPSR(IP10_31_28,            SD3_WP),
        PINMUX_IPSR_MSEL(IP10_31_28,            RIF0_D0_B,      SEL_DRIF0_1),
        PINMUX_IPSR_MSEL(IP10_31_28,            SDA2_B,         SEL_I2C2_1),