ARM: AM43xx: EMIF: configure self-refresh entry delay

Per a suggestion from the hardware team, program the emif_pwr_mgmt_ctrl
and emif_pwr_mgmt_ctrl_shdw registers within the EMIF to hold the
desired delay in cycles that the EMIF waits without an access to enter
self-refresh, in this case 8192 cycles. With this, code desiring to
enter self refresh only has to toggle one bit to enable it.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index d05e666a742f5a4e1d6920046d0ab511ebc8b709..4173a10b143b10b2f21b1c9d881324f9f3f6d2f2 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -80,8 +80,8 @@ static void configure_mr(int nr, u32 cs)
  */
 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 {
-       writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
-       writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+       writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+       writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
        writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
        writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);