sunxi: dram: Support more sun[457]i dram parameters in Kconfig

This patch allows to configure all the important DRAM parameters in Kconfig.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index da4e8ba51803865571103b3ba99dece174446b29..4a2158988fc9bce0d1991d51e72586e7c2af5615 100644 (file)
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -41,6 +41,15 @@ config DRAM_CLK
        Set the dram clock speed, valid range 240 - 480, must be a multiple
        of 24.
 
+if MACH_SUN5I || MACH_SUN7I
+config DRAM_MBUS_CLK
+       int "sunxi mbus clock speed"
+       default 300
+       ---help---
+       Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
+
+endif
+
 config DRAM_ZQ
        int "sunxi dram zq value"
        default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
@@ -56,6 +65,40 @@ config DRAM_EMR1
        ---help---
        Set the dram controller emr1 value.
 
+config DRAM_ODT_EN
+       int "sunxi dram odt_en value"
+       default 0
+       ---help---
+       Set the dram controller odt_en parameter. This can be used to
+       enable/disable the ODT feature.
+
+config DRAM_TPR3
+       hex "sunxi dram tpr3 value"
+       default 0
+       ---help---
+       Set the dram controller tpr3 parameter. This parameter configures
+       the delay on the command lane and also phase shifts, which are
+       applied for sampling incoming read data. The default value 0
+       means that no phase/delay adjustments are necessary. Properly
+       configuring this parameter increases reliability at high DRAM
+       clock speeds.
+
+config DRAM_DQS_GATING_DELAY
+       hex "sunxi dram dqs_gating_delay value"
+       default 0
+       ---help---
+       Set the dram controller dqs_gating_delay parmeter. Each byte
+       encodes the DQS gating delay for each byte lane. The delay
+       granularity is 1/4 cycle. For example, the value 0x05060606
+       means that the delay is 5 quarter-cycles for one lane (1.25
+       cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
+       The default value 0 means autodetection. The results of hardware
+       autodetection are not very reliable and depend on the chip
+       temperature (sometimes producing different results on cold start
+       and warm reboot). But the accuracy of hardware autodetection
+       is usually good enough, unless running at really high DRAM
+       clocks speeds (up to 600MHz). If unsure, keep as 0.
+
 choice
        prompt "sunxi dram timings"
        default DRAM_TIMINGS_VENDOR_MAGIC

diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c
index ed54150ff407a5eb2ff9a4a828346ccd5feb2cf5..09e0c9ae2ec5dfa0cde56e31c81d812a7ca9e1c8 100644 (file)
--- a/board/sunxi/dram_sun4i_auto.c
+++ b/board/sunxi/dram_sun4i_auto.c
@@ -9,7 +9,7 @@ static struct dram_para dram_para = {
        .io_width = 0,
        .bus_width = 0,
        .zq = CONFIG_DRAM_ZQ,
-       .odt_en = 0,
+       .odt_en = CONFIG_DRAM_ODT_EN,
        .size = 0,
 #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
        .cas = 6,
@@ -19,12 +19,14 @@ static struct dram_para dram_para = {
        .emr2 = 0,
 #else
 #      include "dram_timings_sun4i.h"
+       .active_windowing = 1,
 #endif
-       .tpr3 = 0,
+       .tpr3 = CONFIG_DRAM_TPR3,
        .tpr4 = 0,
        .tpr5 = 0,
        .emr1 = CONFIG_DRAM_EMR1,
        .emr3 = 0,
+       .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
 };
 
 unsigned long sunxi_dram_init(void)

diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c
index bd9fd4bd27ed587b062d5854a8666d1a902588a8..e52d54c32e4304e3892a68f4267be6727a3cbbfe 100644 (file)
--- a/board/sunxi/dram_sun5i_auto.c
+++ b/board/sunxi/dram_sun5i_auto.c
@@ -5,13 +5,14 @@
 
 static struct dram_para dram_para = {
        .clock = CONFIG_DRAM_CLK,
+       .mbus_clock = CONFIG_DRAM_MBUS_CLK,
        .type = 3,
        .rank_num = 1,
        .density = 0,
        .io_width = 0,
        .bus_width = 0,
        .zq = CONFIG_DRAM_ZQ,
-       .odt_en = 0,
+       .odt_en = CONFIG_DRAM_ODT_EN,
        .size = 0,
 #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
        .cas = 9,
@@ -21,12 +22,14 @@ static struct dram_para dram_para = {
        .emr2 = 0x10,
 #else
 #      include "dram_timings_sun4i.h"
+       .active_windowing = 1,
 #endif
        .tpr3 = 0,
        .tpr4 = 0,
        .tpr5 = 0,
        .emr1 = CONFIG_DRAM_EMR1,
        .emr3 = 0,
+       .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
 };
 
 unsigned long sunxi_dram_init(void)