riscv: Move timer portions of SiFive CLINT to drivers/timer

Half of this driver is a DM-based timer driver, and half is RISC-V-specific
IPI code. Move the timer portions in with the other timer drivers. The
KConfig is not moved, since it also enables IPIs. It could also be split
into two configs, but no boards use the timer but not the IPI atm, so I
haven't split it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 5d022352c433c89a875d1151a2f044adcd56f098..69a5bc37689315cb7e77d1b7093f75eb367c9b7c 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -939,6 +939,7 @@ T:  git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
 F:     arch/riscv/
 F:     cmd/riscv/
 F:     drivers/timer/andes_plmt_timer.c
+F:     drivers/timer/sifive_clint_timer.c
 F:     tools/prelink-riscv.c
 
 RISC-V KENDRYTE

diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index a5572cb82551a6d88f99d95cffdf6c89c874cee9..c8079dc510c271722163a771b249a4513981436e 100644 (file)
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  *
  * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
@@ -8,19 +9,13 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <dm.h>
-#include <timer.h>
 #include <asm/io.h>
-#include <asm/syscon.h>
+#include <asm/smp.h>
 #include <linux/err.h>
 
 /* MSIP registers */
 #define MSIP_REG(base, hart)           ((ulong)(base) + (hart) * 4)
-/* mtime compare register */
-#define MTIMECMP_REG(base, hart)       ((ulong)(base) + 0x4000 + (hart) * 8)
-/* mtime register */
-#define MTIME_REG(base)                        ((ulong)(base) + 0xbff8)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -61,35 +56,3 @@ int riscv_get_ipi(int hart, int *pending)
 
        return 0;
 }
-
-static u64 sifive_clint_get_count(struct udevice *dev)
-{
-       return readq((void __iomem *)MTIME_REG(dev->priv));
-}
-
-static const struct timer_ops sifive_clint_ops = {
-       .get_count = sifive_clint_get_count,
-};
-
-static int sifive_clint_probe(struct udevice *dev)
-{
-       dev->priv = dev_read_addr_ptr(dev);
-       if (!dev->priv)
-               return -EINVAL;
-
-       return timer_timebase_fallback(dev);
-}
-
-static const struct udevice_id sifive_clint_ids[] = {
-       { .compatible = "riscv,clint0" },
-       { }
-};
-
-U_BOOT_DRIVER(sifive_clint) = {
-       .name           = "sifive_clint",
-       .id             = UCLASS_TIMER,
-       .of_match       = sifive_clint_ids,
-       .probe          = sifive_clint_probe,
-       .ops            = &sifive_clint_ops,
-       .flags          = DM_FLAG_PRE_RELOC,
-};

diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 226227c8ecbfcbb4ad57823fc560ffecdf61dc0a..eb5c48cc6cec28fe444a579f3adf1073fdc37ec5 100644 (file)
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
 obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
 obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
 obj-$(CONFIG_SANDBOX_TIMER)    += sandbox_timer.o
+obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o
 obj-$(CONFIG_STI_TIMER)                += sti-timer.o
 obj-$(CONFIG_STM32_TIMER)      += stm32_timer.o
 obj-$(CONFIG_X86_TSC_TIMER)    += tsc_timer.o

diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c
new file mode 100644 (file)
index 0000000..00ce0f0
--- /dev/null
+++ b/drivers/timer/sifive_clint_timer.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <linux/err.h>
+
+/* mtime register */
+#define MTIME_REG(base)                        ((ulong)(base) + 0xbff8)
+
+static u64 sifive_clint_get_count(struct udevice *dev)
+{
+       return readq((void __iomem *)MTIME_REG(dev->priv));
+}
+
+static const struct timer_ops sifive_clint_ops = {
+       .get_count = sifive_clint_get_count,
+};
+
+static int sifive_clint_probe(struct udevice *dev)
+{
+       dev->priv = dev_read_addr_ptr(dev);
+       if (!dev->priv)
+               return -EINVAL;
+
+       return timer_timebase_fallback(dev);
+}
+
+static const struct udevice_id sifive_clint_ids[] = {
+       { .compatible = "riscv,clint0" },
+       { }
+};
+
+U_BOOT_DRIVER(sifive_clint) = {
+       .name           = "sifive_clint",
+       .id             = UCLASS_TIMER,
+       .of_match       = sifive_clint_ids,
+       .probe          = sifive_clint_probe,
+       .ops            = &sifive_clint_ops,
+       .flags          = DM_FLAG_PRE_RELOC,
+};