clk: renesas: Synchronize R8A779G0 V4H clock tables with Linux 6.5.3

Synchronize R-Car R8A779G0 V4H clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

The PLL2_VAR is not implemented yet and PLL2 is still configured
as regular PLL2 only.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 8625e8a2d36e291768ba45e40db2e37a745f837a..219024a7416e2c98fe9fb215b220ad313526e46b 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -56,7 +56,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a779g0_core_clks[] = {
+static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("extalr",     CLK_EXTALR),
@@ -142,6 +142,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] = {
        DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
        DEF_FIXED("vcbusd2",    R8A779G0_CLK_VCBUSD2,   CLK_VC,         2, 1),
        DEF_DIV6P1("canfd",     R8A779G0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
+       DEF_DIV6P1("csi",       R8A779G0_CLK_CSI,       CLK_PLL5_DIV4,  0x880),
        DEF_FIXED("dsiref",     R8A779G0_CLK_DSIREF,    CLK_PLL5_DIV4,  48, 1),
        DEF_DIV6P1("dsiext",    R8A779G0_CLK_DSIEXT,    CLK_PLL5_DIV4,  0x884),
 
@@ -156,11 +157,13 @@ static const struct cpg_core_clk r8a779g0_core_clks[] = {
        DEF_GEN4_MDSEL("r",     R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
 };
 
-static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("avb0",         211,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("avb1",         212,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("avb2",         213,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("canfd0",       328,    R8A779G0_CLK_SASYNCPERD2),
+       DEF_MOD("csi40",        331,    R8A779G0_CLK_CSI),
+       DEF_MOD("csi41",        400,    R8A779G0_CLK_CSI),
        DEF_MOD("dis0",         411,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("dsitxlink0",   415,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("dsitxlink1",   416,    R8A779G0_CLK_VIOBUSD2),
@@ -177,6 +180,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
        DEF_MOD("i2c4",         522,    R8A779G0_CLK_S0D6_PER),
        DEF_MOD("i2c5",         523,    R8A779G0_CLK_S0D6_PER),
        DEF_MOD("irqc",         611,    R8A779G0_CLK_CL16M),
+       DEF_MOD("ispcs0",       612,    R8A779G0_CLK_S0D2_VIO),
+       DEF_MOD("ispcs1",       613,    R8A779G0_CLK_S0D2_VIO),
        DEF_MOD("msi0",         618,    R8A779G0_CLK_MSO),
        DEF_MOD("msi1",         619,    R8A779G0_CLK_MSO),
        DEF_MOD("msi2",         620,    R8A779G0_CLK_MSO),
@@ -198,6 +203,22 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
        DEF_MOD("tmu3",         716,    R8A779G0_CLK_SASYNCPERD2),
        DEF_MOD("tmu4",         717,    R8A779G0_CLK_SASYNCPERD2),
        DEF_MOD("tpu0",         718,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("vin00",        730,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin01",        731,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin02",        800,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin03",        801,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin04",        802,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin05",        803,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin06",        804,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin07",        805,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin10",        806,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin11",        807,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin12",        808,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin13",        809,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin14",        810,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin15",        811,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin16",        812,    R8A779G0_CLK_S0D4_VIO),
+       DEF_MOD("vin17",        813,    R8A779G0_CLK_S0D4_VIO),
        DEF_MOD("vspd0",        830,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("vspd1",        831,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("wdt1:wdt0",    907,    R8A779G0_CLK_R),
@@ -209,6 +230,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
        DEF_MOD("pfc1",         916,    R8A779G0_CLK_CL16M),
        DEF_MOD("pfc2",         917,    R8A779G0_CLK_CL16M),
        DEF_MOD("pfc3",         918,    R8A779G0_CLK_CL16M),
+       DEF_MOD("tsc",          919,    R8A779G0_CLK_CL16M),
+       DEF_MOD("ssiu",         2926,   R8A779G0_CLK_S0D6_PER),
+       DEF_MOD("ssi",          2927,   R8A779G0_CLK_S0D6_PER),
 };
 
 /*