arm: dts: k3-am65: add support for PCIe and SERDES

Add needed device-tree nodes to support PCIe 0
and SERDES on AM65x SoC. The nodes are kept
disabled by default.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 7d037060576960d622890cf7769be438f75b3391..0f5da9a563d3efeed7ac5529fbb8fb3dcd495463 100644 (file)
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -5,6 +5,9 @@
  * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
  */
 
+#include <dt-bindings/phy/phy-am654-serdes.h>
+#include <dt-bindings/phy/phy.h>
+
 &cbass_main {
        gic500: interrupt-controller@1800000 {
                compatible = "arm,gic-v3";
@@ -143,4 +146,109 @@
                clocks = <&k3_clks 113 1>;
                power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
        };
+
+       scm_conf: scm_conf@100000 {
+               compatible = "syscon", "simple-mfd";
+               reg = <0 0x00100000 0 0x1c000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0x00100000 0x1c000>;
+
+               serdes_mux: mux-controller {
+                       compatible = "mmio-mux";
+                       #mux-control-cells = <1>;
+                       mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
+                                       <0x4090 0x3>; /* SERDES1 lane select */
+               };
+
+               pcie0_mode: pcie-mode@4060 {
+                       compatible = "syscon";
+                       reg = <0x00004060 0x4>;
+               };
+
+               pcie1_mode: pcie-mode@4070 {
+                       compatible = "syscon";
+                       reg = <0x00004070 0x4>;
+               };
+
+               serdes0_clk: serdes_clk@4080 {
+                       compatible = "syscon";
+                       reg = <0x00004080 0x4>;
+               };
+
+               serdes1_clk: serdes_clk@4090 {
+                       compatible = "syscon";
+                       reg = <0x00004090 0x4>;
+               };
+
+               pcie_devid: pcie-devid@210 {
+                       compatible = "syscon";
+                       reg = <0x00000210 0x4>;
+               };
+       };
+
+       serdes0: serdes@900000 {
+               compatible = "ti,phy-am654-serdes";
+               reg = <0x0 0x900000 0x0 0x2000>;
+               reg-names = "serdes";
+               #phy-cells = <2>;
+               power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
+               clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
+               assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+               assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
+               ti,serdes-clk = <&serdes0_clk>;
+               mux-controls = <&serdes_mux 0>;
+               #clock-cells = <1>;
+       };
+
+       serdes1: serdes@910000 {
+               compatible = "ti,phy-am654-serdes";
+               reg = <0x0 0x910000 0x0 0x2000>;
+               reg-names = "serdes";
+               #phy-cells = <2>;
+               power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
+               clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
+               assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
+               assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
+               ti,serdes-clk = <&serdes1_clk>;
+               mux-controls = <&serdes_mux 1>;
+               #clock-cells = <1>;
+       };
+
+       pcie0_rc: pcie@5500000 {
+               compatible = "ti,am654-pcie-rc";
+               reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
+               reg-names = "app", "dbics", "config", "atu";
+               power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               ranges = <0x81000000 0 0          0x0   0x10020000 0 0x00010000
+                         0x82000000 0 0x10030000 0x0   0x10030000 0 0x07FD0000>;
+               ti,syscon-pcie-id = <&pcie_devid>;
+               ti,syscon-pcie-mode = <&pcie0_mode>;
+               bus-range = <0x0 0xff>;
+               status = "disabled";
+               device_type = "pci";
+               num-lanes = <1>;
+               num-ob-windows = <16>;
+               num-viewport = <16>;
+               max-link-speed = <3>;
+               interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 7>;
+               interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
+                               <0 0 0 2 &pcie0_intc 0>, /* INT B */
+                               <0 0 0 3 &pcie0_intc 0>, /* INT C */
+                               <0 0 0 4 &pcie0_intc 0>; /* INT D */
+               msi-map = <0x0 &gic_its 0x0 0x10000>;
+
+               pcie0_intc: legacy-interrupt-controller@1 {
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       interrupt-parent = <&gic500>;
+                       interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
+               };
+       };
 };

diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
index a3abd146d104f929a01b5b10bfab94537b8083db..a1467a4dd4d4372950401d6ebd5763b78e5e5b66 100644 (file)
--- a/arch/arm/dts/k3-am65.dtsi
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -69,6 +69,7 @@
                         <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
                         <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
                         <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
+                        <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
                         /* MCUSS Range */
                         <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
                         <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,

diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h
new file mode 100644 (file)
index 0000000..e8d9017
--- /dev/null
+++ b/include/dt-bindings/phy/phy-am654-serdes.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for AM654 SERDES.
+ */
+
+#ifndef _DT_BINDINGS_AM654_SERDES
+#define _DT_BINDINGS_AM654_SERDES
+
+#define AM654_SERDES_CMU_REFCLK        0
+#define AM654_SERDES_LO_REFCLK 1
+#define AM654_SERDES_RO_REFCLK 2
+
+#endif /* _DT_BINDINGS_AM654_SERDES */