This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt
because it's not really migrated at this point.
Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file]
Signed-off-by: Tom Rini <trini@konsulko.com>
bool "Support kmcent2"
select VENDOR_KM
-config TARGET_UCP1020
- bool "Support uCP1020"
- select ARCH_P1020
- imply CMD_SATA
- imply PANIC_HANG
-
endchoice
config ARCH_B4420
source "board/freescale/t4rdb/Kconfig"
source "board/keymile/Kconfig"
source "board/socrates/Kconfig"
-source "board/Arcturus/ucp1020/Kconfig"
endmenu
+++ /dev/null
-if TARGET_UCP1020
-
-config SYS_BOARD
- string
- default "ucp1020"
-
-config SYS_VENDOR
- string
- default "Arcturus"
-
-config SYS_CONFIG_NAME
- string
- default "UCP1020"
-
-choice
- prompt "Target image select"
-
-config TARGET_UCP1020_NOR
- bool "NOR flash u-boot image"
-
-config TARGET_UCP1020_SPIFLASH
- bool "SPI flash u-boot image"
-
-endchoice
-
-if TARGET_UCP1020_SPIFLASH
-config UCBOOT
- bool
- default y
-
-config SPIFLASH
- bool
- default y
-endif
-
-endif
+++ /dev/null
-UCP1020 BOARD
-M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
-S: Maintained
-F: board/Arcturus/ucp1020/
-F: include/configs/UCP1020.h
-F: configs/UCP1020_defconfig
-F: configs/UCP1020_SPIFLASH_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013-2015 Arcturus Networks, Inc.
-# based on board/freescale/p1_p2_rdb_pc/Makefile
-# original copyright follows:
-# Copyright 2010-2011 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-endif
-
-obj-y += ucp1020.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-obj-y += cmd_arc.o
-
-endif
+++ /dev/null
-The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
-product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
-DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
-
-Information on the generic product family can be found here:
- http://www.arcturusnetworks.com/products/ucp1020
-
-The UCP1020 several configurable options
-========================================
-
-- the selection of populated phy(s):
- KSZ9031 (current default for eTSEC 1 and 3)
-
-- the selection of boot location:
- SPI Flash or NOR flash
-
-The UCP1020 includes 2 default configurations
-=============================================
-NOR boot image:
- configs/UCP1020_defconfig
-SPI boot image:
- configs/UCP1020_SPIFLASH_defconfig
-
-The UCP1020 adds an additional command in cmd_arc.c to access and program
-SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
-HW Addresses.
-
-
-Build example
-=============
-
-make distclean
-make UCP1020_defconfig
-make
-
-Default Scripts
-===============
-A default upgrade scripts is included in the default environment variable example:
-
-B$ run tftpflash
-
-Dual Environment
-================
-
-This build enables dual / failover environment environment.
-
-NOR Flash Partition declarations and scripts
-============================================
-Several scripts are available to allow TFTP of images and programming directly
-into defined NOR flash partitions. Examples:
-
-B$ run program0
-B$ run program1
-B$ run program2
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Command for accessing Arcturus factory environment.
- *
- * Copyright 2013-2019 Arcturus Networks Inc.
- * https://www.arcturusnetworks.com/products/
- * by Oleksandr G Zhadan et al.
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <cpu_func.h>
-#include <div64.h>
-#include <env.h>
-#include <flash.h>
-#include <malloc.h>
-#include <spi_flash.h>
-#include <mmc.h>
-#include <version.h>
-#include <asm/io.h>
-#include <linux/stringify.h>
-
-static ulong fwenv_addr[MAX_FWENV_ADDR];
-const char mystrerr[] = "ERROR: Failed to save factory info";
-
-static int ishwaddr(char *hwaddr)
-{
- if (strlen(hwaddr) == MAX_HWADDR_SIZE)
- if (hwaddr[2] == ':' &&
- hwaddr[5] == ':' &&
- hwaddr[8] == ':' &&
- hwaddr[11] == ':' &&
- hwaddr[14] == ':')
- return 0;
- return -1;
-}
-
-#if (FWENV_TYPE == FWENV_MMC)
-
-static char smac[29][18] __attribute__ ((aligned(0x200))); /* 1 MMC block is 512 bytes */
-
-int set_mmc_arc_product(int argc, char *const argv[])
-{
- struct mmc *mmc;
- u32 blk, cnt, n;
- int i, err = 1;
- void *addr;
- const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
-
- mmc = find_mmc_device(mmc_dev_num);
- if (!mmc) {
- printf("No SD/MMC/eMMC card found\n");
- return 0;
- }
- if (mmc_init(mmc)) {
- printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
- mmc_dev_num);
- return 0;
- }
- if (mmc_getwp(mmc) == 1) {
- printf("Error: card is write protected!\n");
- return CMD_RET_FAILURE;
- }
-
- /* Save factory defaults */
- addr = (void *)smac;
- cnt = 1; /* One 512 bytes block */
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- blk = fwenv_addr[i] / 512;
- n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
- if (n != cnt)
- printf("%s: %s [%d]\n", __func__, mystrerr, i);
- else
- err = 0;
- }
- if (err)
- return -2;
-
- return err;
-}
-
-static int read_mmc_arc_info(void)
-{
- struct mmc *mmc;
- u32 blk, cnt, n;
- int i;
- void *addr;
- const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV;
-
- mmc = find_mmc_device(mmc_dev_num);
- if (!mmc) {
- printf("No SD/MMC/eMMC card found\n");
- return 0;
- }
- if (mmc_init(mmc)) {
- printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC",
- mmc_dev_num);
- return 0;
- }
-
- addr = (void *)smac;
- cnt = 1; /* One 512 bytes block */
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- blk = fwenv_addr[i] / 512;
- n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
- flush_cache((ulong) addr, 512);
- if (n == cnt)
- return (i + 1);
- }
- return 0;
-}
-#endif
-
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
-
-static struct spi_flash *flash;
-static char smac[4][18];
-
-int set_spi_arc_product(int argc, char *const argv[])
-{
- int i, err = 1;
-
- flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
- if (!flash) {
- printf("Failed to initialize SPI flash at %u:%u\n",
- CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
- return -1;
- }
-
- /* Save factory defaults */
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1)
- if (spi_flash_write
- (flash, fwenv_addr[i], sizeof(smac), smac))
- printf("%s: %s [%d]\n", __func__, mystrerr, i);
- else
- err = 0;
- if (err)
- return -2;
-
- return err;
-}
-
-static int read_spi_arc_info(void)
-{
- int i;
-
- flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
- if (!flash) {
- printf("Failed to initialize SPI flash at %u:%u\n",
- CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS);
- return 0;
- }
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1)
- if (!spi_flash_read
- (flash, fwenv_addr[i], sizeof(smac), smac))
- return (i + 1);
- return 0;
-}
-#endif
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
-
-static char smac[4][18];
-
-int set_nor_arc_product(int argc, char *const argv[])
-{
- int i, err = 1;
-
- /* Save factory defaults */
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- ulong fwenv_end = fwenv_addr[i] + 4;
-
- flash_sect_roundb(&fwenv_end);
- flash_sect_protect(0, fwenv_addr[i], fwenv_end);
- if (flash_write
- ((char *)smac, fwenv_addr[i], sizeof(smac)))
- printf("%s: %s [%d]\n", __func__, mystrerr, i);
- else
- err = 0;
- flash_sect_protect(1, fwenv_addr[i], fwenv_end);
- }
- if (err)
- return -2;
-
- return err;
-}
-
-static int read_nor_arc_info(void)
-{
- int i;
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1) {
- memcpy(smac, (void *)fwenv_addr[i], sizeof(smac));
- return (i + 1);
- }
-
- return 0;
-}
-#endif
-
-int set_arc_product(int argc, char *const argv[])
-{
- if (argc != 5)
- return -1;
-
- /* Check serial number */
- if (strlen(argv[1]) != MAX_SERIAL_SIZE)
- return -1;
-
- /* Check HWaddrs */
- if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
- return -1;
-
- strcpy(smac[0], argv[1]);
- strcpy(smac[1], argv[2]);
- strcpy(smac[2], argv[3]);
- strcpy(smac[3], argv[4]);
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
- return set_nor_arc_product(argc, argv);
-#endif
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
- return set_spi_arc_product(argc, argv);
-#endif
-#if (FWENV_TYPE == FWENV_MMC)
- return set_mmc_arc_product(argc, argv);
-#endif
- return -2;
-}
-
-static int read_arc_info(void)
-{
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
- return read_nor_arc_info();
-#endif
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
- return read_spi_arc_info();
-#endif
-#if (FWENV_TYPE == FWENV_MMC)
- return read_mmc_arc_info();
-#endif
- return 0;
-}
-
-static int do_get_arc_info(void)
-{
- int l = read_arc_info();
- char *oldserial = env_get("SERIAL");
- char *oldversion = env_get("VERSION");
-
- if (oldversion != NULL)
- if (strcmp(oldversion, U_BOOT_VERSION) != 0)
- oldversion = NULL;
-
- if (l == 0) {
- printf("%s: failed to read factory info\n", __func__);
- return -2;
- }
-
- printf("\rSERIAL: ");
- if (smac[0][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- printf("%s\n", smac[0]);
- env_set("SERIAL", smac[0]);
- }
-
- if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
- env_set("ethaddr", NULL);
- env_set("eth1addr", NULL);
- env_set("eth2addr", NULL);
- goto done;
- }
-
- printf("HWADDR0: ");
- if (smac[1][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- char *ret = env_get("ethaddr");
-
- if (ret == NULL) {
- env_set("ethaddr", smac[1]);
- printf("%s\n", smac[1]);
- } else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
- env_set("ethaddr", smac[1]);
- printf("%s (factory)\n", smac[1]);
- } else {
- printf("%s\n", ret);
- }
- }
-
- if (strcmp(smac[2], "00:00:00:00:00:00") == 0) {
- env_set("eth1addr", NULL);
- env_set("eth2addr", NULL);
- goto done;
- }
-
- printf("HWADDR1: ");
- if (smac[2][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- char *ret = env_get("eth1addr");
-
- if (ret == NULL) {
- env_set("ethaddr", smac[2]);
- printf("%s\n", smac[2]);
- } else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
- env_set("eth1addr", smac[2]);
- printf("%s (factory)\n", smac[2]);
- } else {
- printf("%s\n", ret);
- }
- }
-
- if (strcmp(smac[3], "00:00:00:00:00:00") == 0) {
- env_set("eth2addr", NULL);
- goto done;
- }
-
- printf("HWADDR2: ");
- if (smac[3][0] == EMPY_CHAR) {
- printf("<not found>\n");
- } else {
- char *ret = env_get("eth2addr");
-
- if (ret == NULL) {
- env_set("ethaddr", smac[3]);
- printf("%s\n", smac[3]);
- } else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
- env_set("eth2addr", smac[3]);
- printf("%s (factory)\n", smac[3]);
- } else {
- printf("%s\n", ret);
- }
- }
-done:
- if (oldserial == NULL || oldversion == NULL) {
- if (oldversion == NULL)
- env_set("VERSION", U_BOOT_VERSION);
- env_save();
- }
-
- return 0;
-}
-
-static int init_fwenv(void)
-{
- int i, ret = -1;
-
- fwenv_addr[0] = FWENV_ADDR1;
- fwenv_addr[1] = FWENV_ADDR2;
- fwenv_addr[2] = FWENV_ADDR3;
- fwenv_addr[3] = FWENV_ADDR4;
-
- for (i = 0; i < MAX_FWENV_ADDR; i++)
- if (fwenv_addr[i] != -1)
- ret = 0;
- if (ret)
- printf("%s: No firmfare info storage address is defined\n",
- __func__);
- return ret;
-}
-
-void get_arc_info(void)
-{
- if (!init_fwenv())
- do_get_arc_info();
-}
-
-static int do_arc_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- const char *cmd;
- int ret = -1;
-
- cmd = argv[1];
- --argc;
- ++argv;
-
- if (init_fwenv())
- return ret;
-
- if (strcmp(cmd, "product") == 0)
- ret = set_arc_product(argc, argv);
- else if (strcmp(cmd, "info") == 0)
- ret = do_get_arc_info();
-
- if (ret == -1)
- return CMD_RET_USAGE;
-
- return ret;
-}
-
-U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
- "Arcturus product command sub-system",
- "product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n"
- "info - show Arcturus factory env\n\n");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
-/*
- * Micron MT41J128M16HA-15E
- * */
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 536870912u,
- .capacity = 536870912u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 1650,
- .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
- .taa_ps = 14050,
- .twr_ps = 15000,
- .trcd_ps = 13500,
- .trrd_ps = 75000,
- .trp_ps = 13500,
- .tras_ps = 40000,
- .trc_ps = 49500,
- .trfc_ps = 160000,
- .twtr_ps = 75000,
- .trtp_ps = 75000,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 30000,
-};
-
-#else
-#error Missing raw timing data for this board
-#endif
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
-
-#ifdef CONFIG_SYS_DDR_CS0_BNDS
-/* Fixed sdram init -- doesn't use serial presence detect. */
-phys_size_t fixed_sdram(void)
-{
- sys_info_t sysinfo;
- char buf[32];
- size_t ddr_size;
- fsl_ddr_cfg_regs_t ddr_cfg_regs = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
- .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
- .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
-#endif
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
- .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
- };
-
- get_sys_info(&sysinfo);
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, sysinfo.freq_ddrbus));
-
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-
- return ddr_size;
-}
-#endif
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- int i;
-
- popts->clk_adjust = 6;
- popts->cpo_override = 0x1f;
- popts->write_data_delay = 2;
- popts->half_strength_driver_enable = 1;
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x8;
- popts->trwt_override = 1;
- popts->trwt = 0;
-
- if (pdimm->primary_sdram_width == 64)
- popts->data_bus_width = 0;
- else if (pdimm->primary_sdram_width == 32)
- popts->data_bus_width = 1;
- else
- printf("Error in DDR bus width configuration!\n");
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
- popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
- }
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_VSC7385_ENET
- SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#endif
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const u32 sysclk_tbl[] = {
- 66666000, 7499900, 83332500, 8999900,
- 99999000, 11111000, 12499800, 13333200
-};
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
-#ifdef CONFIG_SPL_SPI_BOOT
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- gd->bus_clk = bus_clk;
-
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- struct bd_info *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(struct bd_info));
- gd->bd = bd;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
-
-#ifndef CONFIG_SPL_NAND_BOOT
- env_init();
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
- gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-#else
- env_relocate();
-#endif
-
-#ifdef CONFIG_SYS_I2C_LEGACY
- i2c_init_all();
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- dram_init();
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("Tertiary program loader running in sram...");
-#else
- puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc.
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
- * original copyright follows:
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
-
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2015 Arcturus Networks, Inc
- * http://www.arcturusnetworks.com/products/ucp1020/
- * based on board/freescale/p1_p2_rdb_pc/tlb.c
- * original copyright follows:
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX | MAS3_SW | MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
- 0, 2, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_PCI
- /* *I*G* - PCI memory 1.5G */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O effective: 192K */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#ifdef CONFIG_VSC7385_ENET
- /* *I*G - VSC7385 Switch */
- SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-#endif
-#endif /* not SPL */
-
-#ifdef CONFIG_SYS_NAND_BASE
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- /* *I*G - eSDHC/eSPI/NAND boot */
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-
-#endif /* RAMBOOT/SPL */
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#if CONFIG_SYS_L2_SIZE >= (256 << 10)
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
- 0, 12, BOOKE_PAGESZ_256K, 1)
-#endif
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * by Oleksandr G Zhadan et al.
- * based on board/freescale/p1_p2_rdb_pc/spl.c
- * original copyright follows:
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <hwconfig.h>
-#include <image.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <ioports.h>
-#include <netdev.h>
-#include <micrel.h>
-#include <spi_flash.h>
-#include <mmc.h>
-#include <linux/ctype.h>
-#include <asm/fsl_serdes.h>
-#include <asm/gpio.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_lbc.h>
-#include <asm/mp.h>
-#include "ucp1020.h"
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- /* TO DO: It's actially have to be in spi/ */
-}
-
-/*
- * To be compatible with cmd_gpio
- */
-int name_to_gpio(const char *name)
-{
- int gpio = 31 - dectoul(name, NULL);
-
- if (gpio < 16)
- gpio = -1;
-
- return gpio;
-}
-
-void board_gpio_init(void)
-{
- int i;
- char envname[8], *val;
-
- for (i = 0; i < GPIO_MAX_NUM; i++) {
- sprintf(envname, "GPIO%d", i);
- val = env_get(envname);
- if (val) {
- char direction = toupper(val[0]);
- char level = toupper(val[1]);
-
- if (direction == 'I') {
- gpio_direction_input(i);
- } else {
- if (direction == 'O') {
- if (level == '1')
- gpio_direction_output(i, 1);
- else
- gpio_direction_output(i, 0);
- }
- }
- }
- }
-
- val = env_get("PCIE_OFF");
- if (val) {
- gpio_direction_input(GPIO_PCIE1_EN);
- gpio_direction_input(GPIO_PCIE2_EN);
- } else {
- gpio_direction_output(GPIO_PCIE1_EN, 1);
- gpio_direction_output(GPIO_PCIE2_EN, 1);
- }
-
- val = env_get("SDHC_CDWP_OFF");
- if (!val) {
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
- }
-}
-
-int board_early_init_f(void)
-{
- return 0; /* Just in case. Could be disable in config file */
-}
-
-int checkboard(void)
-{
- printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
- board_gpio_init();
-#ifdef CONFIG_MMC
- printf("SD/MMC: 4-bit Mode\n");
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-#if defined(CONFIG_PHY_MICREL_KSZ9021)
- int regval;
- static int cnt;
-
- if (cnt++ == 0)
- printf("PHYs address [");
-
- if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
- regval =
- ksz9021_phy_extended_read(phydev,
- MII_KSZ9021_EXT_STRAP_STATUS);
- /*
- * min rx data delay
- */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x6666);
- /*
- * max rx/tx clock delay, min rx/tx control
- */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf6f6);
- printf("0x%x", (regval & 0x1f));
- } else {
- printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
- }
- if (cnt == 3)
- printf("] ");
- else
- printf(",");
-#endif
-
-#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
- regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
- if (regval >= 0)
- printf(" (ADDR 0x%x) ", regval & 0x1f);
-#endif
-
- return 0;
-}
-
-int last_stage_init(void)
-{
- static char newkernelargs[256];
- static u8 id1[16];
- static u8 id2;
-#ifdef CONFIG_MMC
- struct mmc *mmc;
-#endif
- char *sval, *kval;
-
- if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
- printf("Error reading i2c IDT6V49205B information!\n");
- } else {
- printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
- i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
- if (!(id1[1] & 0x02)) {
- id1[1] |= 0x02;
- i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
- asm("nop; nop");
- }
- }
-
- if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
- printf("Error reading i2c NCT72 information!\n");
- else
- printf("NCT72(0x%x): ready\n", id2);
-
- kval = env_get("kernelargs");
-
-#ifdef CONFIG_MMC
- mmc = find_mmc_device(0);
- if (mmc)
- if (!mmc_init(mmc)) {
- printf("MMC/SD card detected\n");
- if (kval) {
- int n = strlen(defkargs);
- char *tmp = strstr(kval, defkargs);
-
- *tmp = 0;
- strcpy(newkernelargs, kval);
- strcat(newkernelargs, " ");
- strcat(newkernelargs, mmckargs);
- strcat(newkernelargs, " ");
- strcat(newkernelargs, &tmp[n]);
- env_set("kernelargs", newkernelargs);
- } else {
- env_set("kernelargs", mmckargs);
- }
- }
-#endif
- get_arc_info();
-
- if (kval) {
- sval = env_get("SERIAL");
- if (sval) {
- strcpy(newkernelargs, "SN=");
- strcat(newkernelargs, sval);
- strcat(newkernelargs, " ");
- strcat(newkernelargs, kval);
- env_set("kernelargs", newkernelargs);
- }
- } else {
- printf("Error reading kernelargs env variable!\n");
- }
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
-#ifdef CONFIG_TSEC2
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
- }
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- phys_addr_t base;
- phys_size_t size;
- const char *soc_usb_compat = "fsl-usb2-dr";
- int err, usb1_off, usb2_off;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- FT_FSL_PCI_SETUP;
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- /* Delete eLBC node as it is muxed with USB2 controller */
- if (hwconfig("usb2")) {
- const char *soc_elbc_compat = "fsl,p1020-elbc";
- int off = fdt_node_offset_by_compatible(blob, -1,
- soc_elbc_compat);
- if (off < 0) {
- printf
- ("WARNING: could not find compatible node %s: %s\n",
- soc_elbc_compat, fdt_strerror(off));
- return off;
- }
- err = fdt_del_node(blob, off);
- if (err < 0) {
- printf("WARNING: could not remove %s: %s\n",
- soc_elbc_compat, fdt_strerror(err));
- }
- return err;
- }
-#endif
-
-/* Delete USB2 node as it is muxed with eLBC */
- usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
- if (usb1_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat, fdt_strerror(usb1_off));
- return usb1_off;
- }
- usb2_off =
- fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
- if (usb2_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat, fdt_strerror(usb2_off));
- return usb2_off;
- }
- err = fdt_del_node(blob, usb2_off);
- if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- soc_usb_compat, fdt_strerror(err));
- }
- return 0;
-}
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * by Oleksandr G Zhadan et al.
- */
-
-#ifndef __UCP1020_H__
-#define __UCP1020_H__
-
-#define GPIO0 31
-#define GPIO1 30
-#define GPIO2 29
-#define GPIO3 28
-#define GPIO4 27
-#define GPIO5 26
-#define GPIO6 25
-#define GPIO7 24
-#define GPIO8 23
-#define GPIO9 22
-#define GPIO10 21
-#define GPIO11 20
-#define GPIO12 19
-#define GPIO13 18
-#define GPIO14 17
-#define GPIO15 16
-#define GPIO_MAX_NUM 16
-
-#define GPIO_SDHC_CD GPIO8
-#define GPIO_SDHC_WP GPIO9
-#define GPIO_USB_PCTL0 GPIO10
-#define GPIO_PCIE1_EN GPIO11
-#define GPIO_PCIE2_EN GPIO10
-#define GPIO_USB_PCTL1 GPIO11
-
-#define GPIO_WD GPIO15
-
-#ifdef CONFIG_MMC
-static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
-static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
-#endif
-
-int get_arc_info(void);
-
-#endif
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF80000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_UCP1020=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="B$ "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_PCI is not set
-# CONFIG_CMD_SATA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_CRAMFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEC0C0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_FS_CRAMFS=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * based on include/configs/p1_p2_rdb_pc.h
- * original copyright follows:
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * QorIQ uCP1020-xx boards configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*** Arcturus FirmWare Environment */
-
-#define MAX_SERIAL_SIZE 15
-#define MAX_HWADDR_SIZE 17
-
-#define MAX_FWENV_ADDR 4
-
-#define FWENV_MMC 1
-#define FWENV_SPI_FLASH 2
-#define FWENV_NOR_FLASH 3
-/*
- #define FWENV_TYPE FWENV_MMC
- #define FWENV_TYPE FWENV_SPI_FLASH
-*/
-#define FWENV_TYPE FWENV_NOR_FLASH
-
-#if (FWENV_TYPE == FWENV_MMC)
-#define FWENV_ADDR1 -1
-#define FWENV_ADDR2 -1
-#define FWENV_ADDR3 -1
-#define FWENV_ADDR4 -1
-#define EMPY_CHAR 0
-#endif
-
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
-#ifndef CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_SF_DEFAULT_SPEED 1000000
-#endif
-#ifndef CONFIG_SF_DEFAULT_MODE
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE0
-#endif
-#ifndef CONFIG_SF_DEFAULT_CS
-#define CONFIG_SF_DEFAULT_CS 0
-#endif
-#ifndef CONFIG_SF_DEFAULT_BUS
-#define CONFIG_SF_DEFAULT_BUS 0
-#endif
-#define FWENV_ADDR1 (0x200 - sizeof(smac))
-#define FWENV_ADDR2 (0x400 - sizeof(smac))
-#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
-#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
-#define EMPY_CHAR 0xff
-#endif
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
-#define FWENV_ADDR1 0xEC080000
-#define FWENV_ADDR2 -1
-#define FWENV_ADDR3 -1
-#define FWENV_ADDR4 -1
-#define EMPY_CHAR 0xff
-#endif
-/***********************************/
-
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#if defined(CONFIG_TARTGET_UCP1020T1)
-
-#define CONFIG_UCP1020_REV_1_3
-
-#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC3
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
-#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
-#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
-#define CONFIG_IPADDR 10.80.41.229
-#define CONFIG_SERVERIP 10.80.41.227
-#define CONFIG_NETMASK 255.255.252.0
-#define CONFIG_ETHPRIME "eTSEC3"
-
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-
-#endif
-
-#if defined(CONFIG_TARGET_UCP1020)
-
-#define CONFIG_UCP1020
-#define CONFIG_UCP1020_REV_1_3
-
-#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC3
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
-#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
-#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
-#define CONFIG_IPADDR 192.168.1.81
-#define CONFIG_IPADDR1 192.168.1.82
-#define CONFIG_IPADDR2 192.168.1.83
-#define CONFIG_SERVERIP 192.168.1.80
-#define CONFIG_GATEWAYIP 102.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
-#endif
-
-#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LBA48
-
-#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_DDR_CLK_FREQ 66666666
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-#define CONFIG_BTB
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
- SPL code*/
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_DDR_ECC_ENABLE
-#ifndef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#endif
-#define CONFIG_SYS_SPD_BUS_NUM 1
-
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-/* Default settings for DDR3 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#ifdef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
-#else
-#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
-#endif
-#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_MODE_1 0x40461520
-#define CONFIG_SYS_DDR_MODE_2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
- * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
- * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
- * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
- * (early boot only)
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
-#define CONFIG_SYS_FLASH_BASE 0xec000000
-
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | BR_PS_16 | BR_V)
-
-#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-/* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
-
-#define CONFIG_SYS_PMC_BASE 0xff980000
-#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
- BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
- OR_GPCM_EAD)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
-
-#define CONFIG_RTC_DS1337
-#define CONFIG_RTC_DS1337_NOOSC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
-#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
-#define CONFIG_SYS_I2C_IDT6V49205B 0x69
-
-#if defined(CONFIG_PCI)
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/*
- * Environment
- */
-#if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/* Misc Extra Settings */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
-#else
-#error "UCP1020 module revision is not defined !!!"
-#endif
-
-#define CONFIG_BOOTP_SERVERIP
-
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 4
-#define TSEC2_PHY_ADDR 0
-#define TSEC2_PHY_ADDR_SGMII 0x00
-#define TSEC3_PHY_ADDR 6
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#endif
-
-#define CONFIG_HOSTNAME "UCP1020"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#if defined(CONFIG_DONGLE)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run prog_spi_mbrbootcramfs\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"cramfsfile=image.cramfs\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
- "protect off $nor_recoveryaddr +$filesize; " \
- "erase $nor_recoveryaddr +$filesize; " \
- "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
- "protect on $nor_recoveryaddr +$filesize\0 " \
-"flashuboot=tftp $ubootaddr $ubootfile; " \
- "protect off $nor_ubootaddr +$filesize; " \
- "erase $nor_ubootaddr +$filesize; " \
- "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
- "protect on $nor_ubootaddr +$filesize\0 " \
-"flashworking=tftp $workingaddr $cramfsfile; " \
- "protect off $nor_workingaddr +$filesize; " \
- "erase $nor_workingaddr +$filesize; " \
- "cp.b $workingaddr $nor_workingaddr $filesize; " \
- "protect on $nor_workingaddr +$filesize\0 " \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020d.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"mmbr=uCP1020Quiet.mbr\0" \
-"mmcpart=0:2\0" \
-"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
- "mmc erase 1 1; " \
- "mmc write $loadaddr 1 1\0" \
-"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
- "mmc erase 0x40 0x400; " \
- "mmc write $loadaddr 0x40 0x400\0" \
-"netdev=eth0\0" \
-"nor_recoveryaddr=0xEC0A0000\0" \
-"nor_ubootaddr=0xEFF80000\0" \
-"nor_workingaddr=0xECFA0000\0" \
-"norbootrecovery=setenv bootargs $recoverybootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadrecovery; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norbootworking=setenv bootargs $workingbootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadworking; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_recoveryaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_workingaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"prog_spi_mbr=run spi__mbr\0" \
-"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
-"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
- "run spi__cramfs\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"recoveryaddr=0x02F00000\0" \
-"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeC000000 +$filesize; " \
- "erase 0xEC000000 +$filesize; " \
- "cp.b $loadaddr 0xEC000000 $filesize; " \
- "cmp.b $loadaddr 0xEC000000 $filesize; " \
- "protect on 0xeC000000 +$filesize\0" \
-"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeFF80000 +$filesize; " \
- "erase 0xEFF80000 +$filesize; " \
- "cp.b $loadaddr 0xEFF80000 $filesize; " \
- "cmp.b $loadaddr 0xEFF80000 $filesize; " \
- "protect on 0xeFF80000 +$filesize\0" \
-"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
- "sf probe 0; sf erase 0x8000 +$filesize; " \
- "sf write $loadaddr 0x8000 $filesize\0" \
-"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
- "protect off 0xec0a0000 +$filesize; " \
- "erase 0xeC0A0000 +$filesize; " \
- "cp.b $loadaddr 0xeC0A0000 $filesize; " \
- "protect on 0xec0a0000 +$filesize\0" \
-"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
- "sf probe 1; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
- "sf probe 0; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=0x01000000\0" \
-"ubootfile=u-boot.bin\0" \
-"ubootd=u-boot4dongle.bin\0" \
-"upgrade=run flashworking\0" \
-"usb_phy_type=ulpi\0 " \
-"workingaddr=0x02F00000\0" \
-"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
-
-#else
-
-#if defined(CONFIG_UCP1020T1)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"cramfsfile=image.cramfs\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
- "protect off $nor_recoveryaddr +$filesize; " \
- "erase $nor_recoveryaddr +$filesize; " \
- "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
- "protect on $nor_recoveryaddr +$filesize\0 " \
-"flashuboot=tftp $ubootaddr $ubootfile; " \
- "protect off $nor_ubootaddr +$filesize; " \
- "erase $nor_ubootaddr +$filesize; " \
- "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
- "protect on $nor_ubootaddr +$filesize\0 " \
-"flashworking=tftp $workingaddr $cramfsfile; " \
- "protect off $nor_workingaddr +$filesize; " \
- "erase $nor_workingaddr +$filesize; " \
- "cp.b $workingaddr $nor_workingaddr $filesize; " \
- "protect on $nor_workingaddr +$filesize\0 " \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"netdev=eth0\0" \
-"nor_recoveryaddr=0xEC0A0000\0" \
-"nor_ubootaddr=0xEFF80000\0" \
-"nor_workingaddr=0xECFA0000\0" \
-"norbootrecovery=setenv bootargs $recoverybootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadrecovery; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norbootworking=setenv bootargs $workingbootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadworking; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_recoveryaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_workingaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"othbootargs=quiet\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"recoveryaddr=0x02F00000\0" \
-"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"silent=1\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=0x01000000\0" \
-"ubootfile=u-boot.bin\0" \
-"upgrade=run flashworking\0" \
-"workingaddr=0x02F00000\0" \
-"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
-
-#else /* For Arcturus Modules */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run norkernel\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashuboot=tftp $loadaddr $ubootfile; " \
- "protect off $nor_ubootaddr0 +$filesize; " \
- "erase $nor_ubootaddr0 +$filesize; " \
- "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
- "protect on $nor_ubootaddr0 +$filesize; " \
- "protect off $nor_ubootaddr1 +$filesize; " \
- "erase $nor_ubootaddr1 +$filesize; " \
- "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
- "protect on $nor_ubootaddr1 +$filesize\0 " \
-"format0=protect off $part0base +$part0size; " \
- "erase $part0base +$part0size\0" \
-"format1=protect off $part1base +$part1size; " \
- "erase $part1base +$part1size\0" \
-"format2=protect off $part2base +$part2size; " \
- "erase $part2base +$part2size\0" \
-"format3=protect off $part3base +$part3size; " \
- "erase $part3base +$part3size\0" \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"netdev=eth0\0" \
-"nor_ubootaddr0=0xEC000000\0" \
-"nor_ubootaddr1=0xEFF80000\0" \
-"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
- "run norkernelload; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $part0base; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"part0base=0xEC100000\0" \
-"part0size=0x00700000\0" \
-"part1base=0xEC800000\0" \
-"part1size=0x02000000\0" \
-"part2base=0xEE800000\0" \
-"part2size=0x00800000\0" \
-"part3base=0xEF000000\0" \
-"part3size=0x00F80000\0" \
-"partENVbase=0xEC080000\0" \
-"partENVsize=0x00080000\0" \
-"program0=tftp part0-000000.bin; " \
- "protect off $part0base +$filesize; " \
- "erase $part0base +$filesize; " \
- "cp.b $loadaddr $part0base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part0base $filesize\0" \
-"program1=tftp part1-000000.bin; " \
- "protect off $part1base +$filesize; " \
- "erase $part1base +$filesize; " \
- "cp.b $loadaddr $part1base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part1base $filesize\0" \
-"program2=tftp part2-000000.bin; " \
- "protect off $part2base +$filesize; " \
- "erase $part2base +$filesize; " \
- "cp.b $loadaddr $part2base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part2base $filesize\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
- "sf probe 0; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeC000000 +$filesize; " \
- "erase 0xEC000000 +$filesize; " \
- "cp.b $loadaddr 0xEC000000 $filesize; " \
- "cmp.b $loadaddr 0xEC000000 $filesize; " \
- "protect on 0xeC000000 +$filesize\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootfile=u-boot.bin\0" \
-"upgrade=run flashuboot\0" \
-"usb_phy_type=ulpi\0 " \
-"boot_nfs= " \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr\0" \
-"boot_hd = " \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr\0" \
-"boot_usb_fat = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "usb start;" \
- "fatload usb 0:2 $loadaddr $bootfile;" \
- "fatload usb 0:2 $fdtaddr $fdtfile;" \
- "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
-"boot_usb_ext2 = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
-"boot_nor = " \
- "setenv bootargs root=/dev/$jffs2nor rw " \
- "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
- "bootm $norbootaddr - $norfdtaddr\0 " \
-"boot_ram = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
-
-#endif
-#endif
-
-#endif /* __CONFIG_H */
CONFIG_SOFT_I2C_GPIO_SDA
CONFIG_SOFT_I2C_READ_REPEATED_START
CONFIG_SPD_EEPROM
+CONFIG_SPIFLASH
CONFIG_SPI_ADDR
CONFIG_SPI_BOOTING
CONFIG_SPI_DATAFLASH_WRITE_VERIFY
projects / u-boot.git / commitdiff