arm: ls1021a: Add sata support on qds and twr board

Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2d557827495303955390213be15350de6acd80e1..2311468ac98ee6a4577a46e1d166a44f06d45585 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -9,6 +9,7 @@ obj-y   += clock.o
 obj-y  += timer.o
 obj-y  += fsl_epu.o
 
+obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o

diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
new file mode 100644 (file)
index 0000000..deeb674
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <ahci.h>
+#include <scsi.h>
+
+/* port register default value */
+#define AHCI_PORT_PHY_1_CFG    0xa003fffe
+#define AHCI_PORT_PHY_2_CFG    0x28183411
+#define AHCI_PORT_PHY_3_CFG    0x0e081004
+#define AHCI_PORT_PHY_4_CFG    0x00480811
+#define AHCI_PORT_PHY_5_CFG    0x192c96a4
+#define AHCI_PORT_TRANS_CFG    0x08000025
+
+#define SATA_ECC_REG_ADDR      0x20220520
+#define SATA_ECC_DISABLE       0x00020000
+
+int ls1021a_sata_init(void)
+{
+       struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+       out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
+#endif
+
+       out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+       out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+       out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+       out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
+       out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
+       out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+       ahci_init((void __iomem *)AHCI_BASE_ADDR);
+       scsi_scan(0);
+
+       return 0;
+}

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index bcaf7bf2e418ddc587e23fb692c461bca1165a8e..f066480c0c546fbadf699345b4c38098d1e8d58d 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -79,6 +79,21 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             (CONFIG_SYS_PCIE2_PHYS_BASE + \
                                                 CONFIG_SYS_PCIE2_VIRT_ADDR)
 
+/* SATA */
+#define AHCI_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x02200000)
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID            1
+#define CONFIG_SYS_SCSI_MAX_LUN                1
+#define CONFIG_SYS_SCSI_MAX_DEVICE             (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+                                               CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_ERRATUM_A008407
+
 #ifdef CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_VERY_BIG_RAM

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index fbd06bafce31a78d4163d0ab78a56055a2088a69..09ed9809f11606d2f3f75dce34a0d931dfef7f40 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -398,4 +398,28 @@ struct ccsr_cci400 {
        u8 res_e004[0x10000 - 0xe004];
 };
 
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+       u32 res1[0xa4/4];       /* 0x0 - 0xa4 */
+       u32 pcfg;       /* port config */
+       u32 ppcfg;      /* port phy1 config */
+       u32 pp2c;       /* port phy2 config */
+       u32 pp3c;       /* port phy3 config */
+       u32 pp4c;       /* port phy4 config */
+       u32 pp5c;       /* port phy5 config */
+       u32 paxic;      /* port AXI config */
+       u32 axicc;      /* AXI cache control */
+       u32 axipc;      /* AXI PROT control */
+       u32 ptc;        /* port Trans Config */
+       u32 pts;        /* port Trans Status */
+       u32 plc;        /* port link config */
+       u32 plc1;       /* port link config1 */
+       u32 plc2;       /* port link config2 */
+       u32 pls;        /* port link status */
+       u32 pls1;       /* port link status1 */
+       u32 pcmdc;      /* port CMD config */
+       u32 ppcs;       /* port phy control status */
+       u32 pberr;      /* port 0/1 BIST error */
+       u32 cmds;       /* port 0/1 CMD status error */
+};
 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */

diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
new file mode 100644 (file)
index 0000000..d097a6a
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FSL_SATA_H_
+#define __FSL_SATA_H_
+
+int ls1021a_sata_init(void);
+#endif

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 612f17eab1aa27d59cd5e39db120bf5a3a93a606..d889ad50fd04d83d88197234c9fc70f6d0ac35bd 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -12,6 +12,7 @@
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_stream_id.h>
 #include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_sata.h>
 #include <hwconfig.h>
 #include <mmc.h>
 #include <fsl_csu.h>
@@ -407,6 +408,17 @@ int config_serdes_mux(void)
        return 0;
 }
 
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+       ls1021a_sata_init();
+#endif
+
+       return 0;
+}
+#endif
+
 int misc_init_r(void)
 {
        int conflict_flag;

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index c12c2fcefdffb88d359865c4ae74a3aa045de41a..445ea2424dc09283fcd2de8515e927231b2fdf70 100644 (file)
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -12,6 +12,7 @@
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_stream_id.h>
 #include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_sata.h>
 #include <hwconfig.h>
 #include <mmc.h>
 #include <fsl_csu.h>
@@ -565,6 +566,17 @@ int board_init(void)
        return 0;
 }
 
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+       ls1021a_sata_init();
+#endif
+
+       return 0;
+}
+#endif
+
 #if defined(CONFIG_MISC_INIT_R)
 int misc_init_r(void)
 {