sunxi: Introduce a hidden SUNXI_GEN_SUNxI Kconfig bool

sun6i and newer (derived) SoCs such as the sun8i-a23, sun8i-a33 and sun9i
have a various things in common, like having separate ahb reset control
registers, the SID living inside the pmic, custom pmic busses, new style
watchdog, etc.

This commit introduces a new hidden SUNXI_GEN_SUN6I Kconfig bool which can be
used to check for these features avoiding the need for an ever growing list
of "#if defined CONFIG_MACH_SUN?I" conditionals as we add support for more
"new style" sunxi SoCs.

Note that this commit changes the behavior of the gmac and hdmi code for
sun8i and the upcoming sun9i devices. This does not matter as sun8i does
not have gmac nor hdmi, and sun9i has new hardware-blocks for these so
the old code will not work there.

Also this is intentional as if a sun8i / sun9i variant which does use the
old hwblocks shows up then the GEN_SUN6I code paths will be the right ones
to use.

For completeness this also adds a SUNXI_GEN_SUN4I bool for A10/A13/A20.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6471c6b7b2aab12740081f695dc17639023a4f13..260b42d2cf5f51c1a6e1be35a6d0fb25af67bc73 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -173,7 +173,7 @@ void board_init_f(ulong dummy)
 
 void reset_cpu(ulong addr)
 {
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+#ifdef CONFIG_SUNXI_GEN_SUN4I
        static const struct sunxi_wdog *wdog =
                 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 
@@ -185,7 +185,8 @@ void reset_cpu(ulong addr)
                /* sun5i sometimes gets stuck without this */
                writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
        }
-#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        static const struct sunxi_wdog *wdog =
                 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 

diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c
index 80e4fc9d0bd5a4d4cbbe0c287330f0393df46b2b..7d55e413f1687469f339e025952bdcdfbd028478 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/usbc.c
+++ b/arch/arm/cpu/armv7/sunxi/usbc.c
@@ -218,7 +218,7 @@ void sunxi_usbc_enable(int index)
 
        setbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask);
        setbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        setbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
 #endif
 
@@ -238,7 +238,7 @@ void sunxi_usbc_disable(int index)
        if (sunxi_usbc->id != 0)
                sunxi_usb_passby(sunxi_usbc, !SUNXI_USB_PASSBY_EN);
 
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
 #endif
        clrbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index f403742d3ad0b73299c768245707c59234edd2f2..63b161ab032635335165e66c0f36d0f6557d5d29 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -37,7 +37,7 @@
 #define SUNXI_MMC1_BASE                        0x01c10000
 #define SUNXI_MMC2_BASE                        0x01c11000
 #define SUNXI_MMC3_BASE                        0x01c12000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN4I
 #define SUNXI_USB0_BASE                        0x01c13000
 #define SUNXI_USB1_BASE                        0x01c14000
 #endif
@@ -45,12 +45,13 @@
 #define SUNXI_HDMI_BASE                        0x01c16000
 #define SUNXI_SPI2_BASE                        0x01c17000
 #define SUNXI_SATA_BASE                        0x01c18000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN4I
 #define SUNXI_PATA_BASE                        0x01c19000
 #define SUNXI_ACE_BASE                 0x01c1a000
 #define SUNXI_TVE1_BASE                        0x01c1b000
 #define SUNXI_USB2_BASE                        0x01c1c000
-#else
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
 #define SUNXI_USB0_BASE                        0x01c19000
 #define SUNXI_USB1_BASE                        0x01c1a000
 #define SUNXI_USB2_BASE                        0x01c1b000

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 74833b51d1285e12db5865946eb6a34526c645bf..cb52e648731ce9687b7c9cb472463fd54d8da38d 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,8 +43,7 @@ struct sunxi_mmc {
        u32 chda;               /* 0x90 */
        u32 cbda;               /* 0x94 */
        u32 res1[26];
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
-    defined(CONFIG_MACH_SUN9I)
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        u32 res2[64];
 #endif
        u32 fifo;               /* 0x100 / 0x200 FIFO access address */

diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index 9a5e488a38080f489494fd1f45a987c68142d1b6..a665309803cbb02c5ce4e94a0b1cee8d218edd19 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -67,7 +67,7 @@ struct sunxi_timer_reg {
        struct sunxi_timer timer[6];    /* We have 6 timers */
        u8 res2[16];
        struct sunxi_avs avs;
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+#ifdef CONFIG_SUNXI_GEN_SUN4I
        struct sunxi_wdog wdog; /* 0x90 */
        /* XXX the following is not accurate for sun5i/sun7i */
        struct sunxi_64cnt cnt64;       /* 0xa0 */
@@ -77,7 +77,8 @@ struct sunxi_timer_reg {
        struct sunxi_tgp tgp[4];
        u8 res5[8];
        u32 cpu_cfg;
-#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        u8 res3[16];
        struct sunxi_wdog wdog[5];      /* We have 5 watchdogs */
 #endif

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 88e335836d7c48cd4e0333d61989383dff81e7af..b716a8ba1eee78af136477ab612aae149b4d4520 100644 (file)
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -1,21 +1,40 @@
 if ARCH_SUNXI
 
+# Note only one of these may be selected at a time! But hidden choices are
+# not supported by Kconfig
+config SUNXI_GEN_SUN4I
+       bool
+       ---help---
+       Select this for sunxi SoCs which have resets and clocks set up
+       as the original A10 (mach-sun4i).
+
+config SUNXI_GEN_SUN6I
+       bool
+       ---help---
+       Select this for sunxi SoCs which have sun6i like periphery, like
+       separate ahb reset control registers, custom pmic bus, new style
+       watchdog, etc.
+
+
 choice
        prompt "Sunxi SoC Variant"
 
 config MACH_SUN4I
        bool "sun4i (Allwinner A10)"
        select CPU_V7
+       select SUNXI_GEN_SUN4I
        select SUPPORT_SPL
 
 config MACH_SUN5I
        bool "sun5i (Allwinner A13)"
        select CPU_V7
+       select SUNXI_GEN_SUN4I
        select SUPPORT_SPL
 
 config MACH_SUN6I
        bool "sun6i (Allwinner A31)"
        select CPU_V7
+       select SUNXI_GEN_SUN6I
        select SUPPORT_SPL
 
 config MACH_SUN7I
@@ -23,12 +42,14 @@ config MACH_SUN7I
        select CPU_V7
        select CPU_V7_HAS_NONSEC
        select CPU_V7_HAS_VIRT
+       select SUNXI_GEN_SUN4I
        select SUPPORT_SPL
        select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN8I
        bool "sun8i (Allwinner A23)"
        select CPU_V7
+       select SUNXI_GEN_SUN6I
        select SUPPORT_SPL
 
 endchoice

diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index d90eed48f7858c177da2507dcdde422bb6c2fdb7..4e222d88c0d3a9d543ace1f1c17665394f8f25cb 100644 (file)
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -13,11 +13,11 @@ int sunxi_gmac_initialize(bd_t *bis)
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
        /* Set up clock gating */
-#ifndef CONFIG_MACH_SUN6I
-       setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-#else
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
        setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
+#else
+       setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
 #endif
 
        /* Set MII clock */

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 22335452c56c7e241a4744d0a7ed779226464571..1c234e2eda2164f5ed52d949299d3dca05f262da 100644 (file)
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -151,8 +151,7 @@ static int mmc_clk_io_on(int sdc_no)
        /* config ahb clock */
        setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
-    defined(CONFIG_MACH_SUN9I)
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        /* unassert reset */
        setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 #endif

diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index d2341b0e36b24aefae427d325abb6a2d712b3b2f..2ee105690f44d813f4a7aa544c1f81dd3651ddff 100644 (file)
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -84,7 +84,7 @@ static int sunxi_hdmi_hpd_detect(int hpd_delay)
                        CCM_HDMI_CTRL_PLL3);
 
        /* Set ahb gating to pass */
-#ifdef CONFIG_MACH_SUN6I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 #endif
        setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
@@ -113,7 +113,7 @@ static void sunxi_hdmi_shutdown(void)
        clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
        clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
        clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-#ifdef CONFIG_MACH_SUN6I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 #endif
        clock_set_pll3(0);
@@ -404,7 +404,7 @@ static void sunxi_composer_init(void)
 
        sunxi_frontend_init();
 
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        /* Reset off */
        setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 #endif
@@ -549,7 +549,7 @@ static void sunxi_lcdc_init(void)
                (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 
        /* Reset off */
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 #else
        setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
@@ -942,7 +942,7 @@ static void sunxi_vga_enable(void)
 
 static void sunxi_drc_init(void)
 {
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
        struct sunxi_ccm_reg * const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;