ARM: UniPhier: fix IECTRL set code for PH1-Pro4

For PH1-Pro4, the bit 6 of the IECTRL must be set.  It is the only
available bit in this register.  There is no effect of the write
access to the other bits.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
index 2cc5df608f833151e82cc27d2d15183815dbb5a0..b7c4b1096963ec72dcd195058af33d0ebc1acfcc 100644 (file)
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
@@ -23,6 +23,6 @@ void sg_init(void)
 
        /* Input ports must be enabled before deasserting reset of cores */
        tmp = readl(SG_IECTRL);
-       tmp |= 0x1;
+       tmp |= 1 << 6;
        writel(tmp, SG_IECTRL);
 }