mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT

This should make it clear that this symbol is meant to be defined by
board headers.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h
index 25c34fb01151b9c5c588e597d5e4f909b58ff14e..8549fe8babaa37d62d0e49e90094a903a3e3ee0d 100644 (file)
--- a/drivers/ddr/marvell/axp/ddr3_axp_config.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h
@@ -51,7 +51,7 @@
 #define DRAM_ECC                               0
 #endif
 
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
 #define BUS_WIDTH                               32
 #else
 #define BUS_WIDTH                              64

diff --git a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h
index 2c0e9075e96d2ce20f6884c05f49ca889a8ccb82..71794ad312a1b92e60d5255f804f42ce2e5953f6 100644 (file)
--- a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h
@@ -8,9 +8,9 @@
 #define __AXP_MC_STATIC_H
 
 MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
        {0x00001400, 0x7301c924},       /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
        {0x00001400, 0x7301CA28},       /*DDR SDRAM Configuration Register */
 #endif
        {0x00001404, 0x3630b800},       /*Dunit Control Low Register */
@@ -66,9 +66,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
 };
 
 MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
        {0x00001400, 0x7301c924},       /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
        {0x00001400, 0x7301CA28},       /*DDR SDRAM Configuration Register */
 #endif
        {0x00001404, 0x3630b800},       /*Dunit Control Low Register */
@@ -124,9 +124,9 @@ MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
 };
 
 MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
        {0x00001400, 0x73004C30},       /*DDR SDRAM Configuration Register */
-#else /* MV_DDR_64BIT */
+#else /* CONFIG_DDR_64BIT */
        {0x00001400, 0x7300CC30},       /*DDR SDRAM Configuration Register */
 #endif
        {0x00001404, 0x3630B840},       /*Dunit Control Low Register */
@@ -176,9 +176,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
 };
 
 MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
        {0x00001400, 0x73014A28},       /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
        {0x00001400, 0x7301CA28},       /*DDR SDRAM Configuration Register */
 #endif
        {0x00001404, 0x3630B040},       /*Dunit Control Low Register */
@@ -233,9 +233,9 @@ MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
 };
 
 MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
        {0x00001400, 0x73004C30},       /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
        {0x00001400, 0x7300CC30},       /*DDR SDRAM Configuration Register */
        /*{0x00001400, 0x7304CC30},  *//*DDR SDRAM Configuration Register */
 #endif