arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPL

When running on the AXP I sometimes noticed a strange behavior. As some
characters are not echoed on the U-Boot prompt. Not disabling the
lowlevel_init code, especially calling cpu_init_cp15() in the main
U-Boot seems to solve this issue.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index efd4d04ea85126365a3907246cc5bb550c3efe6e..895ad929b10721e4f1d28c0402efd71fc97ade42 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -27,6 +27,14 @@ static struct mbus_win windows[] = {
          CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
 };
 
+void lowlevel_init(void)
+{
+       /*
+        * Dummy implementation, we only need LOWLEVEL_INIT
+        * on Armada to configure CP15 in start.S / cpu_init_cp15()
+        */
+}
+
 void reset_cpu(unsigned long ignored)
 {
        struct mvebu_system_registers *reg =
@@ -214,7 +222,10 @@ static void setup_usb_phys(void)
 
 int arch_cpu_init(void)
 {
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X)
+#if !defined(CONFIG_SPL_BUILD)
+       struct pl310_regs *const pl310 =
+               (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
        /*
         * Only with disabled MMU its possible to switch the base
         * register address on Armada 38x. Without this the SDRAM
@@ -234,18 +245,14 @@ int arch_cpu_init(void)
         * configured the internal register base to the value used
         * in the macros / defines in the U-Boot header (soc.h).
         */
-       if (mvebu_soc_family() == MVEBU_SOC_A38X) {
-               struct pl310_regs *const pl310 =
-                       (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
-               /*
-                * To fully release / unlock this area from cache, we need
-                * to flush all caches and disable the L2 cache.
-                */
-               icache_disable();
-               dcache_disable();
-               clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-       }
+       /*
+        * To fully release / unlock this area from cache, we need
+        * to flush all caches and disable the L2 cache.
+        */
+       icache_disable();
+       dcache_disable();
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 #endif
 
        /*

diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 1dd41821366f5d6e61c194a99189911d8ece225b..15f7bdfac5392f864a8fd977343a38c35ce36665 100644 (file)
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -16,7 +16,9 @@
 
 #define CONFIG_SYS_L2_PL310
 
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
+#endif
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index f612e72d885858943cc521119f189be31d6b0a2e..5b39762303fc3d51511cb6dd81e468daeeb54588 100644 (file)
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -13,7 +13,9 @@
 #define CONFIG_ARMADA_XP               /* SOC Family Name */
 #define CONFIG_DB_784MP_GP             /* Board target name for DDR training */
 
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
+#endif
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 

diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 3530a2621389c9df30ed8aecffbc6b07dcfdc764..3bed9c7ca403d7fce054201c9a3ada3a4acf8aa5 100644 (file)
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -11,7 +11,9 @@
  * High Level Configuration Options (easy to change)
  */
 #define CONFIG_ARMADA_XP               /* SOC Family Name */
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
+#endif
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO_LATE